Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-tegra/pci.c |
| 3 | * |
| 4 | * PCIe host controller driver for TEGRA(2) SOCs |
| 5 | * |
| 6 | * Copyright (c) 2010, CompuLab, Ltd. |
| 7 | * Author: Mike Rapoport <mike@compulab.co.il> |
| 8 | * |
| 9 | * Based on NVIDIA PCIe driver |
| 10 | * Copyright (c) 2008-2009, NVIDIA Corporation. |
| 11 | * |
| 12 | * Bits taken from arch/arm/mach-dove/pcie.c |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 20 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 22 | * more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License along |
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 26 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 27 | */ |
| 28 | |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/irq.h> |
| 33 | #include <linux/clk.h> |
| 34 | #include <linux/delay.h> |
Paul Gortmaker | dc28094 | 2011-07-31 16:17:29 -0400 | [diff] [blame^] | 35 | #include <linux/export.h> |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 36 | |
| 37 | #include <asm/sizes.h> |
| 38 | #include <asm/mach/pci.h> |
| 39 | |
| 40 | #include <mach/pinmux.h> |
| 41 | #include <mach/iomap.h> |
| 42 | #include <mach/clk.h> |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 43 | #include <mach/powergate.h> |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 44 | |
| 45 | /* register definitions */ |
| 46 | #define AFI_OFFSET 0x3800 |
| 47 | #define PADS_OFFSET 0x3000 |
| 48 | #define RP0_OFFSET 0x0000 |
| 49 | #define RP1_OFFSET 0x1000 |
| 50 | |
| 51 | #define AFI_AXI_BAR0_SZ 0x00 |
| 52 | #define AFI_AXI_BAR1_SZ 0x04 |
| 53 | #define AFI_AXI_BAR2_SZ 0x08 |
| 54 | #define AFI_AXI_BAR3_SZ 0x0c |
| 55 | #define AFI_AXI_BAR4_SZ 0x10 |
| 56 | #define AFI_AXI_BAR5_SZ 0x14 |
| 57 | |
| 58 | #define AFI_AXI_BAR0_START 0x18 |
| 59 | #define AFI_AXI_BAR1_START 0x1c |
| 60 | #define AFI_AXI_BAR2_START 0x20 |
| 61 | #define AFI_AXI_BAR3_START 0x24 |
| 62 | #define AFI_AXI_BAR4_START 0x28 |
| 63 | #define AFI_AXI_BAR5_START 0x2c |
| 64 | |
| 65 | #define AFI_FPCI_BAR0 0x30 |
| 66 | #define AFI_FPCI_BAR1 0x34 |
| 67 | #define AFI_FPCI_BAR2 0x38 |
| 68 | #define AFI_FPCI_BAR3 0x3c |
| 69 | #define AFI_FPCI_BAR4 0x40 |
| 70 | #define AFI_FPCI_BAR5 0x44 |
| 71 | |
| 72 | #define AFI_CACHE_BAR0_SZ 0x48 |
| 73 | #define AFI_CACHE_BAR0_ST 0x4c |
| 74 | #define AFI_CACHE_BAR1_SZ 0x50 |
| 75 | #define AFI_CACHE_BAR1_ST 0x54 |
| 76 | |
| 77 | #define AFI_MSI_BAR_SZ 0x60 |
| 78 | #define AFI_MSI_FPCI_BAR_ST 0x64 |
| 79 | #define AFI_MSI_AXI_BAR_ST 0x68 |
| 80 | |
| 81 | #define AFI_CONFIGURATION 0xac |
| 82 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) |
| 83 | |
| 84 | #define AFI_FPCI_ERROR_MASKS 0xb0 |
| 85 | |
| 86 | #define AFI_INTR_MASK 0xb4 |
| 87 | #define AFI_INTR_MASK_INT_MASK (1 << 0) |
| 88 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) |
| 89 | |
| 90 | #define AFI_INTR_CODE 0xb8 |
| 91 | #define AFI_INTR_CODE_MASK 0xf |
| 92 | #define AFI_INTR_MASTER_ABORT 4 |
| 93 | #define AFI_INTR_LEGACY 6 |
| 94 | |
| 95 | #define AFI_INTR_SIGNATURE 0xbc |
| 96 | #define AFI_SM_INTR_ENABLE 0xc4 |
| 97 | |
| 98 | #define AFI_AFI_INTR_ENABLE 0xc8 |
| 99 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) |
| 100 | #define AFI_INTR_EN_INI_DECERR (1 << 1) |
| 101 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) |
| 102 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) |
| 103 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) |
| 104 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) |
| 105 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) |
| 106 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) |
| 107 | |
| 108 | #define AFI_PCIE_CONFIG 0x0f8 |
| 109 | #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) |
| 110 | #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) |
| 111 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) |
| 112 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) |
| 113 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) |
| 114 | |
| 115 | #define AFI_FUSE 0x104 |
| 116 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) |
| 117 | |
| 118 | #define AFI_PEX0_CTRL 0x110 |
| 119 | #define AFI_PEX1_CTRL 0x118 |
| 120 | #define AFI_PEX_CTRL_RST (1 << 0) |
| 121 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
| 122 | |
| 123 | #define RP_VEND_XP 0x00000F00 |
| 124 | #define RP_VEND_XP_DL_UP (1 << 30) |
| 125 | |
| 126 | #define RP_LINK_CONTROL_STATUS 0x00000090 |
| 127 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 |
| 128 | |
| 129 | #define PADS_CTL_SEL 0x0000009C |
| 130 | |
| 131 | #define PADS_CTL 0x000000A0 |
| 132 | #define PADS_CTL_IDDQ_1L (1 << 0) |
| 133 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) |
| 134 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) |
| 135 | |
| 136 | #define PADS_PLL_CTL 0x000000B8 |
| 137 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) |
| 138 | #define PADS_PLL_CTL_LOCKDET (1 << 8) |
| 139 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) |
| 140 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) |
| 141 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) |
| 142 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) |
| 143 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) |
| 144 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) |
| 145 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) |
| 146 | |
| 147 | /* PMC access is required for PCIE xclk (un)clamping */ |
| 148 | #define PMC_SCRATCH42 0x144 |
| 149 | #define PMC_SCRATCH42_PCX_CLAMP (1 << 0) |
| 150 | |
| 151 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); |
| 152 | |
| 153 | #define pmc_writel(value, reg) \ |
| 154 | __raw_writel(value, (u32)reg_pmc_base + (reg)) |
| 155 | #define pmc_readl(reg) \ |
| 156 | __raw_readl((u32)reg_pmc_base + (reg)) |
| 157 | |
| 158 | /* |
| 159 | * Tegra2 defines 1GB in the AXI address map for PCIe. |
| 160 | * |
| 161 | * That address space is split into different regions, with sizes and |
| 162 | * offsets as follows: |
| 163 | * |
| 164 | * 0x80000000 - 0x80003fff - PCI controller registers |
| 165 | * 0x80004000 - 0x80103fff - PCI configuration space |
| 166 | * 0x80104000 - 0x80203fff - PCI extended configuration space |
| 167 | * 0x80203fff - 0x803fffff - unused |
| 168 | * 0x80400000 - 0x8040ffff - downstream IO |
| 169 | * 0x80410000 - 0x8fffffff - unused |
| 170 | * 0x90000000 - 0x9fffffff - non-prefetchable memory |
| 171 | * 0xa0000000 - 0xbfffffff - prefetchable memory |
| 172 | */ |
| 173 | #define TEGRA_PCIE_BASE 0x80000000 |
| 174 | |
| 175 | #define PCIE_REGS_SZ SZ_16K |
| 176 | #define PCIE_CFG_OFF PCIE_REGS_SZ |
| 177 | #define PCIE_CFG_SZ SZ_1M |
| 178 | #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF) |
| 179 | #define PCIE_EXT_CFG_SZ SZ_1M |
| 180 | #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) |
| 181 | |
| 182 | #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) |
| 183 | #define MMIO_SIZE SZ_64K |
| 184 | #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) |
| 185 | #define MEM_SIZE_0 SZ_128M |
| 186 | #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) |
| 187 | #define MEM_SIZE_1 SZ_128M |
| 188 | #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) |
| 189 | #define PREFETCH_MEM_SIZE_0 SZ_128M |
| 190 | #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) |
| 191 | #define PREFETCH_MEM_SIZE_1 SZ_128M |
| 192 | |
| 193 | #define PCIE_CONF_BUS(b) ((b) << 16) |
| 194 | #define PCIE_CONF_DEV(d) ((d) << 11) |
| 195 | #define PCIE_CONF_FUNC(f) ((f) << 8) |
| 196 | #define PCIE_CONF_REG(r) \ |
| 197 | (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) |
| 198 | |
| 199 | struct tegra_pcie_port { |
| 200 | int index; |
| 201 | u8 root_bus_nr; |
| 202 | void __iomem *base; |
| 203 | |
| 204 | bool link_up; |
| 205 | |
| 206 | char io_space_name[16]; |
| 207 | char mem_space_name[16]; |
| 208 | char prefetch_space_name[20]; |
| 209 | struct resource res[3]; |
| 210 | }; |
| 211 | |
| 212 | struct tegra_pcie_info { |
| 213 | struct tegra_pcie_port port[2]; |
| 214 | int num_ports; |
| 215 | |
| 216 | void __iomem *regs; |
| 217 | struct resource res_mmio; |
| 218 | |
| 219 | struct clk *pex_clk; |
| 220 | struct clk *afi_clk; |
| 221 | struct clk *pcie_xclk; |
| 222 | struct clk *pll_e; |
| 223 | }; |
| 224 | |
| 225 | static struct tegra_pcie_info tegra_pcie = { |
| 226 | .res_mmio = { |
| 227 | .name = "PCI IO", |
| 228 | .start = MMIO_BASE, |
| 229 | .end = MMIO_BASE + MMIO_SIZE - 1, |
| 230 | .flags = IORESOURCE_MEM, |
| 231 | }, |
| 232 | }; |
| 233 | |
| 234 | void __iomem *tegra_pcie_io_base; |
| 235 | EXPORT_SYMBOL(tegra_pcie_io_base); |
| 236 | |
| 237 | static inline void afi_writel(u32 value, unsigned long offset) |
| 238 | { |
| 239 | writel(value, offset + AFI_OFFSET + tegra_pcie.regs); |
| 240 | } |
| 241 | |
| 242 | static inline u32 afi_readl(unsigned long offset) |
| 243 | { |
| 244 | return readl(offset + AFI_OFFSET + tegra_pcie.regs); |
| 245 | } |
| 246 | |
| 247 | static inline void pads_writel(u32 value, unsigned long offset) |
| 248 | { |
| 249 | writel(value, offset + PADS_OFFSET + tegra_pcie.regs); |
| 250 | } |
| 251 | |
| 252 | static inline u32 pads_readl(unsigned long offset) |
| 253 | { |
| 254 | return readl(offset + PADS_OFFSET + tegra_pcie.regs); |
| 255 | } |
| 256 | |
| 257 | static struct tegra_pcie_port *bus_to_port(int bus) |
| 258 | { |
| 259 | int i; |
| 260 | |
| 261 | for (i = tegra_pcie.num_ports - 1; i >= 0; i--) { |
| 262 | int rbus = tegra_pcie.port[i].root_bus_nr; |
| 263 | if (rbus != -1 && rbus == bus) |
| 264 | break; |
| 265 | } |
| 266 | |
| 267 | return i >= 0 ? tegra_pcie.port + i : NULL; |
| 268 | } |
| 269 | |
| 270 | static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, |
| 271 | int where, int size, u32 *val) |
| 272 | { |
| 273 | struct tegra_pcie_port *pp = bus_to_port(bus->number); |
| 274 | void __iomem *addr; |
| 275 | |
| 276 | if (pp) { |
| 277 | if (devfn != 0) { |
| 278 | *val = 0xffffffff; |
| 279 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 280 | } |
| 281 | |
| 282 | addr = pp->base + (where & ~0x3); |
| 283 | } else { |
| 284 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + |
| 285 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + |
| 286 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + |
| 287 | PCIE_CONF_REG(where)); |
| 288 | } |
| 289 | |
| 290 | *val = readl(addr); |
| 291 | |
| 292 | if (size == 1) |
| 293 | *val = (*val >> (8 * (where & 3))) & 0xff; |
| 294 | else if (size == 2) |
| 295 | *val = (*val >> (8 * (where & 3))) & 0xffff; |
| 296 | |
| 297 | return PCIBIOS_SUCCESSFUL; |
| 298 | } |
| 299 | |
| 300 | static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, |
| 301 | int where, int size, u32 val) |
| 302 | { |
| 303 | struct tegra_pcie_port *pp = bus_to_port(bus->number); |
| 304 | void __iomem *addr; |
| 305 | |
| 306 | u32 mask; |
| 307 | u32 tmp; |
| 308 | |
| 309 | if (pp) { |
| 310 | if (devfn != 0) |
| 311 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 312 | |
| 313 | addr = pp->base + (where & ~0x3); |
| 314 | } else { |
| 315 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + |
| 316 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + |
| 317 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + |
| 318 | PCIE_CONF_REG(where)); |
| 319 | } |
| 320 | |
| 321 | if (size == 4) { |
| 322 | writel(val, addr); |
| 323 | return PCIBIOS_SUCCESSFUL; |
| 324 | } |
| 325 | |
| 326 | if (size == 2) |
| 327 | mask = ~(0xffff << ((where & 0x3) * 8)); |
| 328 | else if (size == 1) |
| 329 | mask = ~(0xff << ((where & 0x3) * 8)); |
| 330 | else |
| 331 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 332 | |
| 333 | tmp = readl(addr) & mask; |
| 334 | tmp |= val << ((where & 0x3) * 8); |
| 335 | writel(tmp, addr); |
| 336 | |
| 337 | return PCIBIOS_SUCCESSFUL; |
| 338 | } |
| 339 | |
| 340 | static struct pci_ops tegra_pcie_ops = { |
| 341 | .read = tegra_pcie_read_conf, |
| 342 | .write = tegra_pcie_write_conf, |
| 343 | }; |
| 344 | |
| 345 | static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev) |
| 346 | { |
| 347 | u16 reg; |
| 348 | |
| 349 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { |
| 350 | pci_read_config_word(dev, PCI_COMMAND, ®); |
| 351 | reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 352 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); |
| 353 | pci_write_config_word(dev, PCI_COMMAND, reg); |
| 354 | } |
| 355 | } |
| 356 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); |
| 357 | |
| 358 | /* Tegra PCIE root complex wrongly reports device class */ |
| 359 | static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev) |
| 360 | { |
| 361 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
| 362 | } |
| 363 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); |
| 364 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); |
| 365 | |
| 366 | /* Tegra PCIE requires relaxed ordering */ |
| 367 | static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) |
| 368 | { |
| 369 | u16 val16; |
| 370 | int pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 371 | |
| 372 | if (pos <= 0) { |
| 373 | dev_err(&dev->dev, "skipping relaxed ordering fixup\n"); |
| 374 | return; |
| 375 | } |
| 376 | |
| 377 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16); |
| 378 | val16 |= PCI_EXP_DEVCTL_RELAX_EN; |
| 379 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16); |
| 380 | } |
| 381 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); |
| 382 | |
| 383 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) |
| 384 | { |
| 385 | struct tegra_pcie_port *pp; |
| 386 | |
| 387 | if (nr >= tegra_pcie.num_ports) |
| 388 | return 0; |
| 389 | |
| 390 | pp = tegra_pcie.port + nr; |
| 391 | pp->root_bus_nr = sys->busnr; |
| 392 | |
| 393 | /* |
| 394 | * IORESOURCE_IO |
| 395 | */ |
| 396 | snprintf(pp->io_space_name, sizeof(pp->io_space_name), |
| 397 | "PCIe %d I/O", pp->index); |
| 398 | pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; |
| 399 | pp->res[0].name = pp->io_space_name; |
| 400 | if (pp->index == 0) { |
| 401 | pp->res[0].start = PCIBIOS_MIN_IO; |
| 402 | pp->res[0].end = pp->res[0].start + SZ_32K - 1; |
| 403 | } else { |
| 404 | pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; |
| 405 | pp->res[0].end = IO_SPACE_LIMIT; |
| 406 | } |
| 407 | pp->res[0].flags = IORESOURCE_IO; |
| 408 | if (request_resource(&ioport_resource, &pp->res[0])) |
| 409 | panic("Request PCIe IO resource failed\n"); |
| 410 | sys->resource[0] = &pp->res[0]; |
| 411 | |
| 412 | /* |
| 413 | * IORESOURCE_MEM |
| 414 | */ |
| 415 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), |
| 416 | "PCIe %d MEM", pp->index); |
| 417 | pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; |
| 418 | pp->res[1].name = pp->mem_space_name; |
| 419 | if (pp->index == 0) { |
| 420 | pp->res[1].start = MEM_BASE_0; |
| 421 | pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; |
| 422 | } else { |
| 423 | pp->res[1].start = MEM_BASE_1; |
| 424 | pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; |
| 425 | } |
| 426 | pp->res[1].flags = IORESOURCE_MEM; |
| 427 | if (request_resource(&iomem_resource, &pp->res[1])) |
| 428 | panic("Request PCIe Memory resource failed\n"); |
| 429 | sys->resource[1] = &pp->res[1]; |
| 430 | |
| 431 | /* |
| 432 | * IORESOURCE_MEM | IORESOURCE_PREFETCH |
| 433 | */ |
| 434 | snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), |
| 435 | "PCIe %d PREFETCH MEM", pp->index); |
| 436 | pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; |
| 437 | pp->res[2].name = pp->prefetch_space_name; |
| 438 | if (pp->index == 0) { |
| 439 | pp->res[2].start = PREFETCH_MEM_BASE_0; |
| 440 | pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; |
| 441 | } else { |
| 442 | pp->res[2].start = PREFETCH_MEM_BASE_1; |
| 443 | pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; |
| 444 | } |
| 445 | pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 446 | if (request_resource(&iomem_resource, &pp->res[2])) |
| 447 | panic("Request PCIe Prefetch Memory resource failed\n"); |
| 448 | sys->resource[2] = &pp->res[2]; |
| 449 | |
| 450 | return 1; |
| 451 | } |
| 452 | |
Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 453 | static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 454 | { |
| 455 | return INT_PCIE_INTR; |
| 456 | } |
| 457 | |
| 458 | static struct pci_bus __init *tegra_pcie_scan_bus(int nr, |
| 459 | struct pci_sys_data *sys) |
| 460 | { |
| 461 | struct tegra_pcie_port *pp; |
| 462 | |
| 463 | if (nr >= tegra_pcie.num_ports) |
| 464 | return 0; |
| 465 | |
| 466 | pp = tegra_pcie.port + nr; |
| 467 | pp->root_bus_nr = sys->busnr; |
| 468 | |
| 469 | return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); |
| 470 | } |
| 471 | |
| 472 | static struct hw_pci tegra_pcie_hw __initdata = { |
| 473 | .nr_controllers = 2, |
| 474 | .setup = tegra_pcie_setup, |
| 475 | .scan = tegra_pcie_scan_bus, |
| 476 | .swizzle = pci_std_swizzle, |
| 477 | .map_irq = tegra_pcie_map_irq, |
| 478 | }; |
| 479 | |
| 480 | |
| 481 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) |
| 482 | { |
| 483 | const char *err_msg[] = { |
| 484 | "Unknown", |
| 485 | "AXI slave error", |
| 486 | "AXI decode error", |
| 487 | "Target abort", |
| 488 | "Master abort", |
| 489 | "Invalid write", |
| 490 | "Response decoding error", |
| 491 | "AXI response decoding error", |
| 492 | "Transcation timeout", |
| 493 | }; |
| 494 | |
| 495 | u32 code, signature; |
| 496 | |
| 497 | code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK; |
| 498 | signature = afi_readl(AFI_INTR_SIGNATURE); |
| 499 | afi_writel(0, AFI_INTR_CODE); |
| 500 | |
| 501 | if (code == AFI_INTR_LEGACY) |
| 502 | return IRQ_NONE; |
| 503 | |
| 504 | if (code >= ARRAY_SIZE(err_msg)) |
| 505 | code = 0; |
| 506 | |
| 507 | /* |
| 508 | * do not pollute kernel log with master abort reports since they |
| 509 | * happen a lot during enumeration |
| 510 | */ |
| 511 | if (code == AFI_INTR_MASTER_ABORT) |
| 512 | pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature); |
| 513 | else |
| 514 | pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature); |
| 515 | |
| 516 | return IRQ_HANDLED; |
| 517 | } |
| 518 | |
| 519 | static void tegra_pcie_setup_translations(void) |
| 520 | { |
| 521 | u32 fpci_bar; |
| 522 | u32 size; |
| 523 | u32 axi_address; |
| 524 | |
| 525 | /* Bar 0: config Bar */ |
| 526 | fpci_bar = ((u32)0xfdff << 16); |
| 527 | size = PCIE_CFG_SZ; |
| 528 | axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF; |
| 529 | afi_writel(axi_address, AFI_AXI_BAR0_START); |
| 530 | afi_writel(size >> 12, AFI_AXI_BAR0_SZ); |
| 531 | afi_writel(fpci_bar, AFI_FPCI_BAR0); |
| 532 | |
| 533 | /* Bar 1: extended config Bar */ |
| 534 | fpci_bar = ((u32)0xfe1 << 20); |
| 535 | size = PCIE_EXT_CFG_SZ; |
| 536 | axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF; |
| 537 | afi_writel(axi_address, AFI_AXI_BAR1_START); |
| 538 | afi_writel(size >> 12, AFI_AXI_BAR1_SZ); |
| 539 | afi_writel(fpci_bar, AFI_FPCI_BAR1); |
| 540 | |
| 541 | /* Bar 2: downstream IO bar */ |
| 542 | fpci_bar = ((__u32)0xfdfc << 16); |
| 543 | size = MMIO_SIZE; |
| 544 | axi_address = MMIO_BASE; |
| 545 | afi_writel(axi_address, AFI_AXI_BAR2_START); |
| 546 | afi_writel(size >> 12, AFI_AXI_BAR2_SZ); |
| 547 | afi_writel(fpci_bar, AFI_FPCI_BAR2); |
| 548 | |
| 549 | /* Bar 3: prefetchable memory BAR */ |
| 550 | fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1; |
| 551 | size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1; |
| 552 | axi_address = PREFETCH_MEM_BASE_0; |
| 553 | afi_writel(axi_address, AFI_AXI_BAR3_START); |
| 554 | afi_writel(size >> 12, AFI_AXI_BAR3_SZ); |
| 555 | afi_writel(fpci_bar, AFI_FPCI_BAR3); |
| 556 | |
| 557 | /* Bar 4: non prefetchable memory BAR */ |
| 558 | fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1; |
| 559 | size = MEM_SIZE_0 + MEM_SIZE_1; |
| 560 | axi_address = MEM_BASE_0; |
| 561 | afi_writel(axi_address, AFI_AXI_BAR4_START); |
| 562 | afi_writel(size >> 12, AFI_AXI_BAR4_SZ); |
| 563 | afi_writel(fpci_bar, AFI_FPCI_BAR4); |
| 564 | |
| 565 | /* Bar 5: NULL out the remaining BAR as it is not used */ |
| 566 | fpci_bar = 0; |
| 567 | size = 0; |
| 568 | axi_address = 0; |
| 569 | afi_writel(axi_address, AFI_AXI_BAR5_START); |
| 570 | afi_writel(size >> 12, AFI_AXI_BAR5_SZ); |
| 571 | afi_writel(fpci_bar, AFI_FPCI_BAR5); |
| 572 | |
| 573 | /* map all upstream transactions as uncached */ |
| 574 | afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST); |
| 575 | afi_writel(0, AFI_CACHE_BAR0_SZ); |
| 576 | afi_writel(0, AFI_CACHE_BAR1_ST); |
| 577 | afi_writel(0, AFI_CACHE_BAR1_SZ); |
| 578 | |
| 579 | /* No MSI */ |
| 580 | afi_writel(0, AFI_MSI_FPCI_BAR_ST); |
| 581 | afi_writel(0, AFI_MSI_BAR_SZ); |
| 582 | afi_writel(0, AFI_MSI_AXI_BAR_ST); |
| 583 | afi_writel(0, AFI_MSI_BAR_SZ); |
| 584 | } |
| 585 | |
| 586 | static void tegra_pcie_enable_controller(void) |
| 587 | { |
| 588 | u32 val, reg; |
| 589 | int i; |
| 590 | |
| 591 | /* Enable slot clock and pulse the reset signals */ |
| 592 | for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { |
| 593 | val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN; |
| 594 | afi_writel(val, reg); |
| 595 | val &= ~AFI_PEX_CTRL_RST; |
| 596 | afi_writel(val, reg); |
| 597 | |
| 598 | val = afi_readl(reg) | AFI_PEX_CTRL_RST; |
| 599 | afi_writel(val, reg); |
| 600 | } |
| 601 | |
| 602 | /* Enable dual controller and both ports */ |
| 603 | val = afi_readl(AFI_PCIE_CONFIG); |
| 604 | val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | |
| 605 | AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | |
| 606 | AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK); |
| 607 | val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; |
| 608 | afi_writel(val, AFI_PCIE_CONFIG); |
| 609 | |
| 610 | val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; |
| 611 | afi_writel(val, AFI_FUSE); |
| 612 | |
| 613 | /* Initialze internal PHY, enable up to 16 PCIE lanes */ |
| 614 | pads_writel(0x0, PADS_CTL_SEL); |
| 615 | |
| 616 | /* override IDDQ to 1 on all 4 lanes */ |
| 617 | val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L; |
| 618 | pads_writel(val, PADS_CTL); |
| 619 | |
| 620 | /* |
| 621 | * set up PHY PLL inputs select PLLE output as refclock, |
| 622 | * set TX ref sel to div10 (not div5) |
| 623 | */ |
| 624 | val = pads_readl(PADS_PLL_CTL); |
| 625 | val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); |
| 626 | val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); |
| 627 | pads_writel(val, PADS_PLL_CTL); |
| 628 | |
| 629 | /* take PLL out of reset */ |
| 630 | val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM; |
| 631 | pads_writel(val, PADS_PLL_CTL); |
| 632 | |
| 633 | /* |
| 634 | * Hack, set the clock voltage to the DEFAULT provided by hw folks. |
| 635 | * This doesn't exist in the documentation |
| 636 | */ |
| 637 | pads_writel(0xfa5cfa5c, 0xc8); |
| 638 | |
| 639 | /* Wait for the PLL to lock */ |
| 640 | do { |
| 641 | val = pads_readl(PADS_PLL_CTL); |
| 642 | } while (!(val & PADS_PLL_CTL_LOCKDET)); |
| 643 | |
| 644 | /* turn off IDDQ override */ |
| 645 | val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L; |
| 646 | pads_writel(val, PADS_CTL); |
| 647 | |
| 648 | /* enable TX/RX data */ |
| 649 | val = pads_readl(PADS_CTL); |
| 650 | val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); |
| 651 | pads_writel(val, PADS_CTL); |
| 652 | |
| 653 | /* Take the PCIe interface module out of reset */ |
| 654 | tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); |
| 655 | |
| 656 | /* Finally enable PCIe */ |
| 657 | val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; |
| 658 | afi_writel(val, AFI_CONFIGURATION); |
| 659 | |
| 660 | val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | |
| 661 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | |
| 662 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR); |
| 663 | afi_writel(val, AFI_AFI_INTR_ENABLE); |
| 664 | afi_writel(0xffffffff, AFI_SM_INTR_ENABLE); |
| 665 | |
| 666 | /* FIXME: No MSI for now, only INT */ |
| 667 | afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); |
| 668 | |
| 669 | /* Disable all execptions */ |
| 670 | afi_writel(0, AFI_FPCI_ERROR_MASKS); |
| 671 | |
| 672 | return; |
| 673 | } |
| 674 | |
| 675 | static void tegra_pcie_xclk_clamp(bool clamp) |
| 676 | { |
| 677 | u32 reg; |
| 678 | |
| 679 | reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; |
| 680 | |
| 681 | if (clamp) |
| 682 | reg |= PMC_SCRATCH42_PCX_CLAMP; |
| 683 | |
| 684 | pmc_writel(reg, PMC_SCRATCH42); |
| 685 | } |
| 686 | |
Mike Rapoport | 1e40a97 | 2011-03-02 14:34:04 +0200 | [diff] [blame] | 687 | static void tegra_pcie_power_off(void) |
| 688 | { |
| 689 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); |
| 690 | tegra_periph_reset_assert(tegra_pcie.afi_clk); |
| 691 | tegra_periph_reset_assert(tegra_pcie.pex_clk); |
| 692 | |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 693 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); |
Mike Rapoport | 1e40a97 | 2011-03-02 14:34:04 +0200 | [diff] [blame] | 694 | tegra_pcie_xclk_clamp(true); |
| 695 | } |
| 696 | |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 697 | static int tegra_pcie_power_regate(void) |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 698 | { |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 699 | int err; |
| 700 | |
| 701 | tegra_pcie_power_off(); |
| 702 | |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 703 | tegra_pcie_xclk_clamp(true); |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 704 | |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 705 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 706 | tegra_periph_reset_assert(tegra_pcie.afi_clk); |
| 707 | |
| 708 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, |
| 709 | tegra_pcie.pex_clk); |
| 710 | if (err) { |
| 711 | pr_err("PCIE: powerup sequence failed: %d\n", err); |
| 712 | return err; |
| 713 | } |
| 714 | |
| 715 | tegra_periph_reset_deassert(tegra_pcie.afi_clk); |
| 716 | |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 717 | tegra_pcie_xclk_clamp(false); |
| 718 | |
| 719 | clk_enable(tegra_pcie.afi_clk); |
| 720 | clk_enable(tegra_pcie.pex_clk); |
| 721 | return clk_enable(tegra_pcie.pll_e); |
| 722 | } |
| 723 | |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 724 | static int tegra_pcie_clocks_get(void) |
| 725 | { |
| 726 | int err; |
| 727 | |
| 728 | tegra_pcie.pex_clk = clk_get(NULL, "pex"); |
| 729 | if (IS_ERR(tegra_pcie.pex_clk)) |
| 730 | return PTR_ERR(tegra_pcie.pex_clk); |
| 731 | |
| 732 | tegra_pcie.afi_clk = clk_get(NULL, "afi"); |
| 733 | if (IS_ERR(tegra_pcie.afi_clk)) { |
| 734 | err = PTR_ERR(tegra_pcie.afi_clk); |
| 735 | goto err_afi_clk; |
| 736 | } |
| 737 | |
| 738 | tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk"); |
| 739 | if (IS_ERR(tegra_pcie.pcie_xclk)) { |
| 740 | err = PTR_ERR(tegra_pcie.pcie_xclk); |
| 741 | goto err_pcie_xclk; |
| 742 | } |
| 743 | |
| 744 | tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e"); |
| 745 | if (IS_ERR(tegra_pcie.pll_e)) { |
| 746 | err = PTR_ERR(tegra_pcie.pll_e); |
| 747 | goto err_pll_e; |
| 748 | } |
| 749 | |
| 750 | return 0; |
| 751 | |
| 752 | err_pll_e: |
| 753 | clk_put(tegra_pcie.pcie_xclk); |
| 754 | err_pcie_xclk: |
| 755 | clk_put(tegra_pcie.afi_clk); |
| 756 | err_afi_clk: |
| 757 | clk_put(tegra_pcie.pex_clk); |
| 758 | |
| 759 | return err; |
| 760 | } |
| 761 | |
| 762 | static void tegra_pcie_clocks_put(void) |
| 763 | { |
| 764 | clk_put(tegra_pcie.pll_e); |
| 765 | clk_put(tegra_pcie.pcie_xclk); |
| 766 | clk_put(tegra_pcie.afi_clk); |
| 767 | clk_put(tegra_pcie.pex_clk); |
| 768 | } |
| 769 | |
| 770 | static int __init tegra_pcie_get_resources(void) |
| 771 | { |
| 772 | struct resource *res_mmio = &tegra_pcie.res_mmio; |
| 773 | int err; |
| 774 | |
| 775 | err = tegra_pcie_clocks_get(); |
| 776 | if (err) { |
| 777 | pr_err("PCIE: failed to get clocks: %d\n", err); |
| 778 | return err; |
| 779 | } |
| 780 | |
Mike Rapoport | b96cc7f | 2011-03-02 14:34:05 +0200 | [diff] [blame] | 781 | err = tegra_pcie_power_regate(); |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 782 | if (err) { |
| 783 | pr_err("PCIE: failed to power up: %d\n", err); |
| 784 | goto err_pwr_on; |
| 785 | } |
| 786 | |
| 787 | tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); |
| 788 | if (tegra_pcie.regs == NULL) { |
| 789 | pr_err("PCIE: Failed to map PCI/AFI registers\n"); |
| 790 | err = -ENOMEM; |
| 791 | goto err_map_reg; |
| 792 | } |
| 793 | |
| 794 | err = request_resource(&iomem_resource, res_mmio); |
| 795 | if (err) { |
| 796 | pr_err("PCIE: Failed to request resources: %d\n", err); |
| 797 | goto err_req_io; |
| 798 | } |
| 799 | |
| 800 | tegra_pcie_io_base = ioremap_nocache(res_mmio->start, |
| 801 | resource_size(res_mmio)); |
| 802 | if (tegra_pcie_io_base == NULL) { |
| 803 | pr_err("PCIE: Failed to map IO\n"); |
| 804 | err = -ENOMEM; |
| 805 | goto err_map_io; |
| 806 | } |
| 807 | |
| 808 | err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, |
| 809 | IRQF_SHARED, "PCIE", &tegra_pcie); |
| 810 | if (err) { |
| 811 | pr_err("PCIE: Failed to register IRQ: %d\n", err); |
| 812 | goto err_irq; |
| 813 | } |
| 814 | set_irq_flags(INT_PCIE_INTR, IRQF_VALID); |
| 815 | |
| 816 | return 0; |
| 817 | |
| 818 | err_irq: |
| 819 | iounmap(tegra_pcie_io_base); |
| 820 | err_map_io: |
| 821 | release_resource(&tegra_pcie.res_mmio); |
| 822 | err_req_io: |
| 823 | iounmap(tegra_pcie.regs); |
| 824 | err_map_reg: |
| 825 | tegra_pcie_power_off(); |
| 826 | err_pwr_on: |
| 827 | tegra_pcie_clocks_put(); |
| 828 | |
| 829 | return err; |
| 830 | } |
| 831 | |
| 832 | /* |
| 833 | * FIXME: If there are no PCIe cards attached, then calling this function |
| 834 | * can result in the increase of the bootup time as there are big timeout |
| 835 | * loops. |
| 836 | */ |
| 837 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ |
| 838 | static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, |
| 839 | u32 reset_reg) |
| 840 | { |
| 841 | u32 reg; |
| 842 | int retries = 3; |
| 843 | int timeout; |
| 844 | |
| 845 | do { |
| 846 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; |
| 847 | while (timeout) { |
| 848 | reg = readl(pp->base + RP_VEND_XP); |
| 849 | |
| 850 | if (reg & RP_VEND_XP_DL_UP) |
| 851 | break; |
| 852 | |
| 853 | mdelay(1); |
| 854 | timeout--; |
| 855 | } |
| 856 | |
| 857 | if (!timeout) { |
| 858 | pr_err("PCIE: port %d: link down, retrying\n", idx); |
| 859 | goto retry; |
| 860 | } |
| 861 | |
| 862 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; |
| 863 | while (timeout) { |
| 864 | reg = readl(pp->base + RP_LINK_CONTROL_STATUS); |
| 865 | |
| 866 | if (reg & 0x20000000) |
| 867 | return true; |
| 868 | |
| 869 | mdelay(1); |
| 870 | timeout--; |
| 871 | } |
| 872 | |
| 873 | retry: |
| 874 | /* Pulse the PEX reset */ |
| 875 | reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; |
| 876 | afi_writel(reg, reset_reg); |
| 877 | mdelay(1); |
| 878 | reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; |
| 879 | afi_writel(reg, reset_reg); |
| 880 | |
| 881 | retries--; |
| 882 | } while (retries); |
| 883 | |
| 884 | return false; |
| 885 | } |
| 886 | |
| 887 | static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) |
| 888 | { |
| 889 | struct tegra_pcie_port *pp; |
| 890 | |
| 891 | pp = tegra_pcie.port + tegra_pcie.num_ports; |
| 892 | |
| 893 | pp->index = -1; |
| 894 | pp->base = tegra_pcie.regs + offset; |
| 895 | pp->link_up = tegra_pcie_check_link(pp, index, reset_reg); |
| 896 | |
| 897 | if (!pp->link_up) { |
| 898 | pp->base = NULL; |
| 899 | printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); |
| 900 | return; |
| 901 | } |
| 902 | |
| 903 | tegra_pcie.num_ports++; |
| 904 | pp->index = index; |
| 905 | pp->root_bus_nr = -1; |
| 906 | memset(pp->res, 0, sizeof(pp->res)); |
| 907 | } |
| 908 | |
| 909 | int __init tegra_pcie_init(bool init_port0, bool init_port1) |
| 910 | { |
| 911 | int err; |
| 912 | |
| 913 | if (!(init_port0 || init_port1)) |
| 914 | return -ENODEV; |
| 915 | |
Rob Herring | c9d95fb | 2011-06-28 21:16:13 -0500 | [diff] [blame] | 916 | pcibios_min_mem = 0; |
| 917 | |
Mike Rapoport | 77ffc14 | 2010-09-27 11:26:33 +0200 | [diff] [blame] | 918 | err = tegra_pcie_get_resources(); |
| 919 | if (err) |
| 920 | return err; |
| 921 | |
| 922 | tegra_pcie_enable_controller(); |
| 923 | |
| 924 | /* setup the AFI address translations */ |
| 925 | tegra_pcie_setup_translations(); |
| 926 | |
| 927 | if (init_port0) |
| 928 | tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL); |
| 929 | |
| 930 | if (init_port1) |
| 931 | tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL); |
| 932 | |
| 933 | pci_common_init(&tegra_pcie_hw); |
| 934 | |
| 935 | return 0; |
| 936 | } |