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Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001/*
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002 * Support functions for OMAP GPIO
3 *
Tony Lindgren92105bb2005-09-07 17:20:26 +01004 * Copyright (C) 2003-2005 Nokia Corporation
Jan Engelhardt96de0e22007-10-19 23:21:04 +02005 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01006 *
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010015#include <linux/init.h>
16#include <linux/module.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010017#include <linux/interrupt.h>
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +020018#include <linux/syscore_ops.h>
Tony Lindgren92105bb2005-09-07 17:20:26 +010019#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000020#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Benoit Cousson96751fc2012-02-01 16:01:39 +010022#include <linux/device.h>
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080023#include <linux/pm_runtime.h>
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +053024#include <linux/pm.h>
Benoit Cousson384ebe12011-08-16 11:53:02 +020025#include <linux/of.h>
26#include <linux/of_device.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070027#include <linux/gpio.h>
Yegor Yefremov93700842014-04-24 08:57:39 +020028#include <linux/bitops.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070029#include <linux/platform_data/gpio-omap.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010030
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053031#define OFF_MODE 1
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +030032#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053033
Charulatha V03e128c2011-05-05 19:58:01 +053034static LIST_HEAD(omap_gpio_list);
35
Charulatha V6d62e212011-04-18 15:06:51 +000036struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
Nishanth Menonae547352011-09-09 19:08:58 +053047 u32 debounce;
48 u32 debounce_en;
Charulatha V6d62e212011-04-18 15:06:51 +000049};
50
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010051struct gpio_bank {
Charulatha V03e128c2011-05-05 19:58:01 +053052 struct list_head node;
Tony Lindgren92105bb2005-09-07 17:20:26 +010053 void __iomem *base;
Grygorii Strashko30cefea2015-09-25 12:06:02 -070054 int irq;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080055 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
Charulatha V6d62e212011-04-18 15:06:51 +000057 struct gpio_regs context;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080058 u32 saved_datain;
Kevin Hilmanb144ff62008-01-16 21:56:15 -080059 u32 level_mask;
Cory Maccarrone4318f362010-01-08 10:29:04 -080060 u32 toggle_mask;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +020061 raw_spinlock_t lock;
Grygorii Strashko450fa542015-09-25 12:28:03 -070062 raw_spinlock_t wa_lock;
David Brownell52e31342008-03-03 12:43:23 -080063 struct gpio_chip chip;
Jouni Hogander89db9482008-12-10 17:35:24 -080064 struct clk *dbck;
Charulatha V058af1e2009-11-22 10:11:25 -080065 u32 mod_usage;
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020066 u32 irq_usage;
Kevin Hilman8865b9b2009-01-27 11:15:34 -080067 u32 dbck_enable_mask;
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +053068 bool dbck_enabled;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080069 struct device *dev;
Charulatha Vd0d665a2011-08-31 00:02:21 +053070 bool is_mpuio;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080071 bool dbck_flag;
Charulatha V0cde8d02011-05-05 20:15:16 +053072 bool loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -050073 bool context_valid;
Tony Lindgren5de62b82010-12-07 16:26:58 -080074 int stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -070075 u32 width;
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053076 int context_loss_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053077 int power_mode;
78 bool workaround_enabled;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070079
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +020080 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053081 int (*get_context_loss_count)(struct device *dev);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070082
83 struct omap_gpio_reg_offs *regs;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010084};
85
Charulatha Vc8eef652011-05-02 15:21:42 +053086#define GPIO_MOD_CTRL_BIT BIT(0)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010087
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020088#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +020089#define LINE_USED(line, offset) (line & (BIT(offset)))
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020090
Tony Lindgren3d009c82015-01-16 14:50:50 -080091static void omap_gpio_unmask_irq(struct irq_data *d);
92
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +020093static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
Jon Hunterede4d7a2013-03-01 11:22:47 -060094{
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +020095 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
96 return container_of(chip, struct gpio_bank, chip);
Benoit Cousson25db7112012-02-23 21:50:10 +010097}
98
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +020099static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
100 int is_input)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100101{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100102 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100103 u32 l;
104
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700105 reg += bank->regs->direction;
Victor Kamensky661553b2013-11-16 02:01:04 +0200106 l = readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100107 if (is_input)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200108 l |= BIT(gpio);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100109 else
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200110 l &= ~(BIT(gpio));
Victor Kamensky661553b2013-11-16 02:01:04 +0200111 writel_relaxed(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530112 bank->context.oe = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100113}
114
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700115
116/* set data out value using dedicate set/clear register */
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200117static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200118 int enable)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100119{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100120 void __iomem *reg = bank->base;
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200121 u32 l = BIT(offset);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100122
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530123 if (enable) {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700124 reg += bank->regs->set_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530125 bank->context.dataout |= l;
126 } else {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700127 reg += bank->regs->clr_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530128 bank->context.dataout &= ~l;
129 }
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700130
Victor Kamensky661553b2013-11-16 02:01:04 +0200131 writel_relaxed(l, reg);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700132}
133
134/* set data out value using mask register */
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200135static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200136 int enable)
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700137{
138 void __iomem *reg = bank->base + bank->regs->dataout;
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200139 u32 gpio_bit = BIT(offset);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700140 u32 l;
141
Victor Kamensky661553b2013-11-16 02:01:04 +0200142 l = readl_relaxed(reg);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700143 if (enable)
144 l |= gpio_bit;
145 else
146 l &= ~gpio_bit;
Victor Kamensky661553b2013-11-16 02:01:04 +0200147 writel_relaxed(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530148 bank->context.dataout = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100149}
150
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200151static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100152{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700153 void __iomem *reg = bank->base + bank->regs->datain;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100154
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200155 return (readl_relaxed(reg) & (BIT(offset))) != 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100156}
157
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200158static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300159{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700160 void __iomem *reg = bank->base + bank->regs->dataout;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300161
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200162 return (readl_relaxed(reg) & (BIT(offset))) != 0;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300163}
164
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200165static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
Kevin Hilmanece95282011-07-12 08:18:15 -0700166{
Victor Kamensky661553b2013-11-16 02:01:04 +0200167 int l = readl_relaxed(base + reg);
Kevin Hilmanece95282011-07-12 08:18:15 -0700168
Benoit Cousson862ff642012-02-01 15:58:56 +0100169 if (set)
Kevin Hilmanece95282011-07-12 08:18:15 -0700170 l |= mask;
171 else
172 l &= ~mask;
173
Victor Kamensky661553b2013-11-16 02:01:04 +0200174 writel_relaxed(l, base + reg);
Kevin Hilmanece95282011-07-12 08:18:15 -0700175}
Tony Lindgren92105bb2005-09-07 17:20:26 +0100176
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200177static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530178{
179 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300180 clk_enable(bank->dbck);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530181 bank->dbck_enabled = true;
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300182
Victor Kamensky661553b2013-11-16 02:01:04 +0200183 writel_relaxed(bank->dbck_enable_mask,
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300184 bank->base + bank->regs->debounce_en);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530185 }
186}
187
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200188static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530189{
190 if (bank->dbck_enable_mask && bank->dbck_enabled) {
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300191 /*
192 * Disable debounce before cutting it's clock. If debounce is
193 * enabled but the clock is not, GPIO module seems to be unable
194 * to detect events and generate interrupts at least on OMAP3.
195 */
Victor Kamensky661553b2013-11-16 02:01:04 +0200196 writel_relaxed(0, bank->base + bank->regs->debounce_en);
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300197
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300198 clk_disable(bank->dbck);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530199 bank->dbck_enabled = false;
200 }
201}
202
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700203/**
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200204 * omap2_set_gpio_debounce - low level gpio debounce time
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700205 * @bank: the gpio bank we're acting upon
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200206 * @offset: the gpio number on this @bank
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700207 * @debounce: debounce time to use
208 *
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300209 * OMAP's debounce time is in 31us steps
210 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
211 * so we need to convert and round up to the closest unit.
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700212 */
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200213static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200214 unsigned debounce)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700215{
Kevin Hilman9942da02011-04-22 12:02:05 -0700216 void __iomem *reg;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700217 u32 val;
218 u32 l;
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300219 bool enable = !!debounce;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700220
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800221 if (!bank->dbck_flag)
222 return;
223
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300224 if (enable) {
225 debounce = DIV_ROUND_UP(debounce, 31) - 1;
226 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
227 }
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700228
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200229 l = BIT(offset);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700230
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300231 clk_enable(bank->dbck);
Kevin Hilman9942da02011-04-22 12:02:05 -0700232 reg = bank->base + bank->regs->debounce;
Victor Kamensky661553b2013-11-16 02:01:04 +0200233 writel_relaxed(debounce, reg);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700234
Kevin Hilman9942da02011-04-22 12:02:05 -0700235 reg = bank->base + bank->regs->debounce_en;
Victor Kamensky661553b2013-11-16 02:01:04 +0200236 val = readl_relaxed(reg);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700237
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300238 if (enable)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700239 val |= l;
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530240 else
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700241 val &= ~l;
Kevin Hilmanf7ec0b02010-06-09 13:53:07 +0300242 bank->dbck_enable_mask = val;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700243
Victor Kamensky661553b2013-11-16 02:01:04 +0200244 writel_relaxed(val, reg);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300245 clk_disable(bank->dbck);
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530246 /*
247 * Enable debounce clock per module.
248 * This call is mandatory because in omap_gpio_request() when
249 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
250 * runtime callbck fails to turn on dbck because dbck_enable_mask
251 * used within _gpio_dbck_enable() is still not initialized at
252 * that point. Therefore we have to enable dbck here.
253 */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200254 omap_gpio_dbck_enable(bank);
Nishanth Menonae547352011-09-09 19:08:58 +0530255 if (bank->dbck_enable_mask) {
256 bank->context.debounce = debounce;
257 bank->context.debounce_en = val;
258 }
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700259}
260
Jon Hunterc9c55d92012-10-26 14:26:04 -0500261/**
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200262 * omap_clear_gpio_debounce - clear debounce settings for a gpio
Jon Hunterc9c55d92012-10-26 14:26:04 -0500263 * @bank: the gpio bank we're acting upon
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200264 * @offset: the gpio number on this @bank
Jon Hunterc9c55d92012-10-26 14:26:04 -0500265 *
266 * If a gpio is using debounce, then clear the debounce enable bit and if
267 * this is the only gpio in this bank using debounce, then clear the debounce
268 * time too. The debounce clock will also be disabled when calling this function
269 * if this is the only gpio in the bank using debounce.
270 */
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200271static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
Jon Hunterc9c55d92012-10-26 14:26:04 -0500272{
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200273 u32 gpio_bit = BIT(offset);
Jon Hunterc9c55d92012-10-26 14:26:04 -0500274
275 if (!bank->dbck_flag)
276 return;
277
278 if (!(bank->dbck_enable_mask & gpio_bit))
279 return;
280
281 bank->dbck_enable_mask &= ~gpio_bit;
282 bank->context.debounce_en &= ~gpio_bit;
Victor Kamensky661553b2013-11-16 02:01:04 +0200283 writel_relaxed(bank->context.debounce_en,
Jon Hunterc9c55d92012-10-26 14:26:04 -0500284 bank->base + bank->regs->debounce_en);
285
286 if (!bank->dbck_enable_mask) {
287 bank->context.debounce = 0;
Victor Kamensky661553b2013-11-16 02:01:04 +0200288 writel_relaxed(bank->context.debounce, bank->base +
Jon Hunterc9c55d92012-10-26 14:26:04 -0500289 bank->regs->debounce);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300290 clk_disable(bank->dbck);
Jon Hunterc9c55d92012-10-26 14:26:04 -0500291 bank->dbck_enabled = false;
292 }
293}
294
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200295static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
Tarun Kanti DebBarma00ece7e2011-11-25 15:41:06 +0530296 unsigned trigger)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100297{
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800298 void __iomem *base = bank->base;
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200299 u32 gpio_bit = BIT(gpio);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100300
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200301 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
302 trigger & IRQ_TYPE_LEVEL_LOW);
303 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
304 trigger & IRQ_TYPE_LEVEL_HIGH);
305 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
306 trigger & IRQ_TYPE_EDGE_RISING);
307 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
308 trigger & IRQ_TYPE_EDGE_FALLING);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530309
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530310 bank->context.leveldetect0 =
Victor Kamensky661553b2013-11-16 02:01:04 +0200311 readl_relaxed(bank->base + bank->regs->leveldetect0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530312 bank->context.leveldetect1 =
Victor Kamensky661553b2013-11-16 02:01:04 +0200313 readl_relaxed(bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530314 bank->context.risingdetect =
Victor Kamensky661553b2013-11-16 02:01:04 +0200315 readl_relaxed(bank->base + bank->regs->risingdetect);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530316 bank->context.fallingdetect =
Victor Kamensky661553b2013-11-16 02:01:04 +0200317 readl_relaxed(bank->base + bank->regs->fallingdetect);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530318
319 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200320 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530321 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200322 readl_relaxed(bank->base + bank->regs->wkup_en);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530323 }
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530324
Ambresh K55b220c2011-06-15 13:40:45 -0700325 /* This part needs to be executed always for OMAP{34xx, 44xx} */
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530326 if (!bank->regs->irqctrl) {
327 /* On omap24xx proceed only when valid GPIO bit is set */
328 if (bank->non_wakeup_gpios) {
329 if (!(bank->non_wakeup_gpios & gpio_bit))
330 goto exit;
331 }
332
Chunqiu Wang699117a62009-06-24 17:13:39 +0000333 /*
334 * Log the edge gpio and manually trigger the IRQ
335 * after resume if the input level changes
336 * to avoid irq lost during PER RET/OFF mode
337 * Applies for omap2 non-wakeup gpio and all omap3 gpios
338 */
339 if (trigger & IRQ_TYPE_EDGE_BOTH)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800340 bank->enabled_non_wakeup_gpios |= gpio_bit;
341 else
342 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
343 }
Kevin Hilman5eb3bb92007-05-05 11:40:29 -0700344
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530345exit:
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530346 bank->level_mask =
Victor Kamensky661553b2013-11-16 02:01:04 +0200347 readl_relaxed(bank->base + bank->regs->leveldetect0) |
348 readl_relaxed(bank->base + bank->regs->leveldetect1);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100349}
350
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800351#ifdef CONFIG_ARCH_OMAP1
Cory Maccarrone4318f362010-01-08 10:29:04 -0800352/*
353 * This only applies to chips that can't do both rising and falling edge
354 * detection at once. For all other chips, this function is a noop.
355 */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200356static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800357{
358 void __iomem *reg = bank->base;
359 u32 l = 0;
360
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530361 if (!bank->regs->irqctrl)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800362 return;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530363
364 reg += bank->regs->irqctrl;
Cory Maccarrone4318f362010-01-08 10:29:04 -0800365
Victor Kamensky661553b2013-11-16 02:01:04 +0200366 l = readl_relaxed(reg);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800367 if ((l >> gpio) & 1)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200368 l &= ~(BIT(gpio));
Cory Maccarrone4318f362010-01-08 10:29:04 -0800369 else
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200370 l |= BIT(gpio);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800371
Victor Kamensky661553b2013-11-16 02:01:04 +0200372 writel_relaxed(l, reg);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800373}
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530374#else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200375static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800376#endif
Cory Maccarrone4318f362010-01-08 10:29:04 -0800377
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200378static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
379 unsigned trigger)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100380{
381 void __iomem *reg = bank->base;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530382 void __iomem *base = bank->base;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100383 u32 l = 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100384
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530385 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200386 omap_set_gpio_trigger(bank, gpio, trigger);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530387 } else if (bank->regs->irqctrl) {
388 reg += bank->regs->irqctrl;
389
Victor Kamensky661553b2013-11-16 02:01:04 +0200390 l = readl_relaxed(reg);
Janusz Krzysztofik29501572010-04-05 11:38:06 +0000391 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200392 bank->toggle_mask |= BIT(gpio);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100393 if (trigger & IRQ_TYPE_EDGE_RISING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200394 l |= BIT(gpio);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100395 else if (trigger & IRQ_TYPE_EDGE_FALLING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200396 l &= ~(BIT(gpio));
Tony Lindgren92105bb2005-09-07 17:20:26 +0100397 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530398 return -EINVAL;
399
Victor Kamensky661553b2013-11-16 02:01:04 +0200400 writel_relaxed(l, reg);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530401 } else if (bank->regs->edgectrl1) {
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100402 if (gpio & 0x08)
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530403 reg += bank->regs->edgectrl2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100404 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530405 reg += bank->regs->edgectrl1;
406
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100407 gpio &= 0x07;
Victor Kamensky661553b2013-11-16 02:01:04 +0200408 l = readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100409 l &= ~(3 << (gpio << 1));
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100410 if (trigger & IRQ_TYPE_EDGE_RISING)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100411 l |= 2 << (gpio << 1);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100412 if (trigger & IRQ_TYPE_EDGE_FALLING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200413 l |= BIT(gpio << 1);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530414
415 /* Enable wake-up during idle for dynamic tick */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200416 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530417 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200418 readl_relaxed(bank->base + bank->regs->wkup_en);
419 writel_relaxed(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100420 }
Tony Lindgren92105bb2005-09-07 17:20:26 +0100421 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100422}
423
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200424static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200425{
426 if (bank->regs->pinctrl) {
427 void __iomem *reg = bank->base + bank->regs->pinctrl;
428
429 /* Claim the pin for MPU */
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200430 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200431 }
432
433 if (bank->regs->ctrl && !BANK_USED(bank)) {
434 void __iomem *reg = bank->base + bank->regs->ctrl;
435 u32 ctrl;
436
Victor Kamensky661553b2013-11-16 02:01:04 +0200437 ctrl = readl_relaxed(reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200438 /* Module is enabled, clocks are not gated */
439 ctrl &= ~GPIO_MOD_CTRL_BIT;
Victor Kamensky661553b2013-11-16 02:01:04 +0200440 writel_relaxed(ctrl, reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200441 bank->context.ctrl = ctrl;
442 }
443}
444
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200445static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200446{
447 void __iomem *base = bank->base;
448
449 if (bank->regs->wkup_en &&
450 !LINE_USED(bank->mod_usage, offset) &&
451 !LINE_USED(bank->irq_usage, offset)) {
452 /* Disable wake-up during idle for dynamic tick */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200453 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200454 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200455 readl_relaxed(bank->base + bank->regs->wkup_en);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200456 }
457
458 if (bank->regs->ctrl && !BANK_USED(bank)) {
459 void __iomem *reg = bank->base + bank->regs->ctrl;
460 u32 ctrl;
461
Victor Kamensky661553b2013-11-16 02:01:04 +0200462 ctrl = readl_relaxed(reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200463 /* Module is disabled, clocks are gated */
464 ctrl |= GPIO_MOD_CTRL_BIT;
Victor Kamensky661553b2013-11-16 02:01:04 +0200465 writel_relaxed(ctrl, reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200466 bank->context.ctrl = ctrl;
467 }
468}
469
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200470static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200471{
472 void __iomem *reg = bank->base + bank->regs->direction;
473
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200474 return readl_relaxed(reg) & BIT(offset);
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200475}
476
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200477static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
Tony Lindgren3d009c82015-01-16 14:50:50 -0800478{
479 if (!LINE_USED(bank->mod_usage, offset)) {
480 omap_enable_gpio_module(bank, offset);
481 omap_set_gpio_direction(bank, offset, 1);
482 }
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200483 bank->irq_usage |= BIT(offset);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800484}
485
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200486static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100487{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200488 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100489 int retval;
David Brownella6472532008-03-03 04:33:30 -0800490 unsigned long flags;
Grygorii Strashkoea5fbe82015-03-23 14:18:29 +0200491 unsigned offset = d->hwirq;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100492
David Brownelle5c56ed2006-12-06 17:13:59 -0800493 if (type & ~IRQ_TYPE_SENSE_MASK)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100494 return -EINVAL;
David Brownelle5c56ed2006-12-06 17:13:59 -0800495
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530496 if (!bank->regs->leveldetect0 &&
497 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
Tony Lindgren92105bb2005-09-07 17:20:26 +0100498 return -EINVAL;
499
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200500 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200501 retval = omap_set_gpio_triggering(bank, offset, type);
Grygorii Strashko977bd8a2015-06-24 17:54:17 +0300502 if (retval) {
Axel Lin627c89b2015-08-05 22:37:41 +0800503 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko1562e462015-05-22 17:35:49 +0300504 goto error;
Grygorii Strashko977bd8a2015-06-24 17:54:17 +0300505 }
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200506 omap_gpio_init_irq(bank, offset);
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200507 if (!omap_gpio_is_input(bank, offset)) {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200508 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko1562e462015-05-22 17:35:49 +0300509 retval = -EINVAL;
510 goto error;
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200511 }
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200512 raw_spin_unlock_irqrestore(&bank->lock, flags);
Kevin Hilman672e3022008-01-16 21:56:16 -0800513
514 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner43ec2e42015-06-23 15:52:39 +0200515 irq_set_handler_locked(d, handle_level_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800516 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixner43ec2e42015-06-23 15:52:39 +0200517 irq_set_handler_locked(d, handle_edge_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800518
Grygorii Strashko1562e462015-05-22 17:35:49 +0300519 return 0;
520
521error:
Tony Lindgren92105bb2005-09-07 17:20:26 +0100522 return retval;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100523}
524
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200525static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100526{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100527 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100528
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700529 reg += bank->regs->irqstatus;
Victor Kamensky661553b2013-11-16 02:01:04 +0200530 writel_relaxed(gpio_mask, reg);
Hiroshi DOYUbee79302006-09-25 12:41:46 +0300531
532 /* Workaround for clearing DSP GPIO interrupts to allow retention */
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700533 if (bank->regs->irqstatus2) {
534 reg = bank->base + bank->regs->irqstatus2;
Victor Kamensky661553b2013-11-16 02:01:04 +0200535 writel_relaxed(gpio_mask, reg);
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700536 }
Roger Quadrosbedfd152009-04-23 11:10:50 -0700537
538 /* Flush posted write for the irq status to avoid spurious interrupts */
Victor Kamensky661553b2013-11-16 02:01:04 +0200539 readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100540}
541
Grygorii Strashko9943f262015-03-23 14:18:27 +0200542static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
543 unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100544{
Grygorii Strashko9943f262015-03-23 14:18:27 +0200545 omap_clear_gpio_irqbank(bank, BIT(offset));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100546}
547
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200548static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
Imre Deakea6dedd2006-06-26 16:16:00 -0700549{
550 void __iomem *reg = bank->base;
Imre Deak99c47702006-06-26 16:16:07 -0700551 u32 l;
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200552 u32 mask = (BIT(bank->width)) - 1;
Imre Deakea6dedd2006-06-26 16:16:00 -0700553
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700554 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200555 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700556 if (bank->regs->irqenable_inv)
Imre Deak99c47702006-06-26 16:16:07 -0700557 l = ~l;
558 l &= mask;
559 return l;
Imre Deakea6dedd2006-06-26 16:16:00 -0700560}
561
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200562static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100563{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100564 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100565 u32 l;
566
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700567 if (bank->regs->set_irqenable) {
568 reg += bank->regs->set_irqenable;
569 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530570 bank->context.irqenable1 |= gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700571 } else {
572 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200573 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700574 if (bank->regs->irqenable_inv)
575 l &= ~gpio_mask;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100576 else
577 l |= gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530578 bank->context.irqenable1 = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100579 }
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700580
Victor Kamensky661553b2013-11-16 02:01:04 +0200581 writel_relaxed(l, reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700582}
583
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200584static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700585{
586 void __iomem *reg = bank->base;
587 u32 l;
588
589 if (bank->regs->clr_irqenable) {
590 reg += bank->regs->clr_irqenable;
591 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530592 bank->context.irqenable1 &= ~gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700593 } else {
594 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200595 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700596 if (bank->regs->irqenable_inv)
597 l |= gpio_mask;
598 else
599 l &= ~gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530600 bank->context.irqenable1 = l;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700601 }
602
Victor Kamensky661553b2013-11-16 02:01:04 +0200603 writel_relaxed(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100604}
605
Grygorii Strashko9943f262015-03-23 14:18:27 +0200606static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
607 unsigned offset, int enable)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100608{
Tarun Kanti DebBarma8276536c2011-11-25 15:27:37 +0530609 if (enable)
Grygorii Strashko9943f262015-03-23 14:18:27 +0200610 omap_enable_gpio_irqbank(bank, BIT(offset));
Tarun Kanti DebBarma8276536c2011-11-25 15:27:37 +0530611 else
Grygorii Strashko9943f262015-03-23 14:18:27 +0200612 omap_disable_gpio_irqbank(bank, BIT(offset));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100613}
614
Tony Lindgren92105bb2005-09-07 17:20:26 +0100615/*
616 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
617 * 1510 does not seem to have a wake-up register. If JTAG is connected
618 * to the target, system will wake up always on GPIO events. While
619 * system is running all registered GPIO interrupts need to have wake-up
620 * enabled. When system is suspended, only selected GPIO interrupts need
621 * to have wake-up enabled.
622 */
Grygorii Strashko9943f262015-03-23 14:18:27 +0200623static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
624 int enable)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100625{
Grygorii Strashko9943f262015-03-23 14:18:27 +0200626 u32 gpio_bit = BIT(offset);
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700627 unsigned long flags;
David Brownella6472532008-03-03 04:33:30 -0800628
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700629 if (bank->non_wakeup_gpios & gpio_bit) {
Benoit Cousson862ff642012-02-01 15:58:56 +0100630 dev_err(bank->dev,
Grygorii Strashko9943f262015-03-23 14:18:27 +0200631 "Unable to modify wakeup on non-wakeup GPIO%d\n",
632 offset);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100633 return -EINVAL;
634 }
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700635
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200636 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700637 if (enable)
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530638 bank->context.wake_en |= gpio_bit;
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700639 else
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530640 bank->context.wake_en &= ~gpio_bit;
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700641
Victor Kamensky661553b2013-11-16 02:01:04 +0200642 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200643 raw_spin_unlock_irqrestore(&bank->lock, flags);
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700644
645 return 0;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100646}
647
648/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200649static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100650{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200651 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200652 unsigned offset = d->hwirq;
Grygorii Strashko450fa542015-09-25 12:28:03 -0700653 int ret;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100654
Grygorii Strashko450fa542015-09-25 12:28:03 -0700655 ret = omap_set_gpio_wakeup(bank, offset, enable);
656 if (!ret)
657 ret = irq_set_irq_wake(bank->irq, enable);
658
659 return ret;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100660}
661
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800662static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100663{
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800664 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
David Brownella6472532008-03-03 04:33:30 -0800665 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100666
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530667 /*
668 * If this is the first gpio_request for the bank,
669 * enable the bank module.
670 */
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200671 if (!BANK_USED(bank))
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530672 pm_runtime_get_sync(bank->dev);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100673
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200674 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashkoc3518172015-05-22 17:35:51 +0300675 omap_enable_gpio_module(bank, offset);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200676 bank->mod_usage |= BIT(offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200677 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100678
679 return 0;
680}
681
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800682static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100683{
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800684 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
David Brownella6472532008-03-03 04:33:30 -0800685 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100686
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200687 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200688 bank->mod_usage &= ~(BIT(offset));
Grygorii Strashko5f982c72015-05-22 17:35:48 +0300689 if (!LINE_USED(bank->irq_usage, offset)) {
690 omap_set_gpio_direction(bank, offset, 1);
691 omap_clear_gpio_debounce(bank, offset);
692 }
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200693 omap_disable_gpio_module(bank, offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200694 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530695
696 /*
697 * If this is the last gpio to be freed in the bank,
698 * disable the bank module.
699 */
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200700 if (!BANK_USED(bank))
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530701 pm_runtime_put(bank->dev);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100702}
703
704/*
705 * We need to unmask the GPIO bank interrupt as soon as possible to
706 * avoid missing GPIO interrupts for other lines in the bank.
707 * Then we need to mask-read-clear-unmask the triggered GPIO lines
708 * in the bank to avoid missing nested interrupts for a GPIO line.
709 * If we wait to unmask individual GPIO lines in the bank after the
710 * line's interrupt handler has been run, we may miss some nested
711 * interrupts.
712 */
Grygorii Strashko450fa542015-09-25 12:28:03 -0700713static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100714{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100715 void __iomem *isr_reg = NULL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100716 u32 isr;
Jon Hunter3513cde2013-04-04 15:16:14 -0500717 unsigned int bit;
Grygorii Strashko450fa542015-09-25 12:28:03 -0700718 struct gpio_bank *bank = gpiobank;
719 unsigned long wa_lock_flags;
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300720 unsigned long lock_flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100721
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700722 isr_reg = bank->base + bank->regs->irqstatus;
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800723 if (WARN_ON(!isr_reg))
724 goto exit;
725
Grygorii Strashko450fa542015-09-25 12:28:03 -0700726 pm_runtime_get_sync(bank->dev);
727
Laurent Navete83507b2013-03-20 13:15:57 +0100728 while (1) {
Tony Lindgren6e60e792006-04-02 17:46:23 +0100729 u32 isr_saved, level_mask = 0;
Imre Deakea6dedd2006-06-26 16:16:00 -0700730 u32 enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100731
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300732 raw_spin_lock_irqsave(&bank->lock, lock_flags);
733
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200734 enabled = omap_get_gpio_irqbank_mask(bank);
Victor Kamensky661553b2013-11-16 02:01:04 +0200735 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100736
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530737 if (bank->level_mask)
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800738 level_mask = bank->level_mask & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100739
740 /* clear edge sensitive interrupts before handler(s) are
741 called so that we don't miss any interrupt occurred while
742 executing them */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200743 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
744 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
745 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
Tony Lindgren6e60e792006-04-02 17:46:23 +0100746
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300747 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
748
Tony Lindgren92105bb2005-09-07 17:20:26 +0100749 if (!isr)
750 break;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100751
Jon Hunter3513cde2013-04-04 15:16:14 -0500752 while (isr) {
753 bit = __ffs(isr);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200754 isr &= ~(BIT(bit));
Benoit Cousson25db7112012-02-23 21:50:10 +0100755
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300756 raw_spin_lock_irqsave(&bank->lock, lock_flags);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800757 /*
758 * Some chips can't respond to both rising and falling
759 * at the same time. If this irq was requested with
760 * both flags, we need to flip the ICR data for the IRQ
761 * to respond to the IRQ for the opposite direction.
762 * This will be indicated in the bank toggle_mask.
763 */
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200764 if (bank->toggle_mask & (BIT(bit)))
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200765 omap_toggle_gpio_edge_triggering(bank, bit);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800766
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300767 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
768
Grygorii Strashko450fa542015-09-25 12:28:03 -0700769 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
770
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +0200771 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
772 bit));
Grygorii Strashko450fa542015-09-25 12:28:03 -0700773
774 raw_spin_unlock_irqrestore(&bank->wa_lock,
775 wa_lock_flags);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100776 }
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000777 }
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800778exit:
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530779 pm_runtime_put(bank->dev);
Grygorii Strashko450fa542015-09-25 12:28:03 -0700780 return IRQ_HANDLED;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100781}
782
Tony Lindgren3d009c82015-01-16 14:50:50 -0800783static unsigned int omap_gpio_irq_startup(struct irq_data *d)
784{
785 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800786 unsigned long flags;
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200787 unsigned offset = d->hwirq;
Tony Lindgren3d009c82015-01-16 14:50:50 -0800788
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200789 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300790
791 if (!LINE_USED(bank->mod_usage, offset))
792 omap_set_gpio_direction(bank, offset, 1);
793 else if (!omap_gpio_is_input(bank, offset))
794 goto err;
795 omap_enable_gpio_module(bank, offset);
796 bank->irq_usage |= BIT(offset);
797
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200798 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800799 omap_gpio_unmask_irq(d);
800
801 return 0;
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300802err:
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200803 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300804 return -EINVAL;
Tony Lindgren3d009c82015-01-16 14:50:50 -0800805}
806
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200807static void omap_gpio_irq_shutdown(struct irq_data *d)
Tony Lindgren4196dd62006-09-25 12:41:38 +0300808{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200809 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Colin Cross85ec7b92011-06-06 13:38:18 -0700810 unsigned long flags;
Grygorii Strashko9943f262015-03-23 14:18:27 +0200811 unsigned offset = d->hwirq;
Tony Lindgren4196dd62006-09-25 12:41:38 +0300812
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200813 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200814 bank->irq_usage &= ~(BIT(offset));
Grygorii Strashko6e96c1b2015-05-22 17:35:50 +0300815 omap_set_gpio_irqenable(bank, offset, 0);
816 omap_clear_gpio_irqstatus(bank, offset);
817 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
818 if (!LINE_USED(bank->mod_usage, offset))
819 omap_clear_gpio_debounce(bank, offset);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200820 omap_disable_gpio_module(bank, offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200821 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashkoaca82d12015-09-25 12:28:02 -0700822}
823
824static void omap_gpio_irq_bus_lock(struct irq_data *data)
825{
826 struct gpio_bank *bank = omap_irq_data_get_bank(data);
827
828 if (!BANK_USED(bank))
829 pm_runtime_get_sync(bank->dev);
830}
831
832static void gpio_irq_bus_sync_unlock(struct irq_data *data)
833{
834 struct gpio_bank *bank = omap_irq_data_get_bank(data);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200835
836 /*
837 * If this is the last IRQ to be freed in the bank,
838 * disable the bank module.
839 */
840 if (!BANK_USED(bank))
841 pm_runtime_put(bank->dev);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300842}
843
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200844static void omap_gpio_ack_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100845{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200846 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200847 unsigned offset = d->hwirq;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100848
Grygorii Strashko9943f262015-03-23 14:18:27 +0200849 omap_clear_gpio_irqstatus(bank, offset);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100850}
851
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200852static void omap_gpio_mask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100853{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200854 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200855 unsigned offset = d->hwirq;
Colin Cross85ec7b92011-06-06 13:38:18 -0700856 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100857
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200858 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200859 omap_set_gpio_irqenable(bank, offset, 0);
860 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200861 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100862}
863
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200864static void omap_gpio_unmask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100865{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200866 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200867 unsigned offset = d->hwirq;
Thomas Gleixner8c04a172011-03-24 12:40:15 +0100868 u32 trigger = irqd_get_trigger_type(d);
Colin Cross85ec7b92011-06-06 13:38:18 -0700869 unsigned long flags;
Kevin Hilman55b60192009-06-04 15:57:10 -0700870
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200871 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman55b60192009-06-04 15:57:10 -0700872 if (trigger)
Grygorii Strashko9943f262015-03-23 14:18:27 +0200873 omap_set_gpio_triggering(bank, offset, trigger);
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800874
875 /* For level-triggered GPIOs, the clearing must be done after
876 * the HW source is cleared, thus after the handler has run */
Grygorii Strashko9943f262015-03-23 14:18:27 +0200877 if (bank->level_mask & BIT(offset)) {
878 omap_set_gpio_irqenable(bank, offset, 0);
879 omap_clear_gpio_irqstatus(bank, offset);
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800880 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100881
Grygorii Strashko9943f262015-03-23 14:18:27 +0200882 omap_set_gpio_irqenable(bank, offset, 1);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200883 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100884}
885
David Brownelle5c56ed2006-12-06 17:13:59 -0800886/*---------------------------------------------------------------------*/
887
Magnus Damm79ee0312009-07-08 13:22:04 +0200888static int omap_mpuio_suspend_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800889{
Magnus Damm79ee0312009-07-08 13:22:04 +0200890 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800891 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800892 void __iomem *mask_reg = bank->base +
893 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800894 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800895
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200896 raw_spin_lock_irqsave(&bank->lock, flags);
Victor Kamensky661553b2013-11-16 02:01:04 +0200897 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200898 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800899
900 return 0;
901}
902
Magnus Damm79ee0312009-07-08 13:22:04 +0200903static int omap_mpuio_resume_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800904{
Magnus Damm79ee0312009-07-08 13:22:04 +0200905 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800906 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800907 void __iomem *mask_reg = bank->base +
908 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800909 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800910
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200911 raw_spin_lock_irqsave(&bank->lock, flags);
Victor Kamensky661553b2013-11-16 02:01:04 +0200912 writel_relaxed(bank->context.wake_en, mask_reg);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200913 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800914
915 return 0;
916}
917
Alexey Dobriyan47145212009-12-14 18:00:08 -0800918static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
Magnus Damm79ee0312009-07-08 13:22:04 +0200919 .suspend_noirq = omap_mpuio_suspend_noirq,
920 .resume_noirq = omap_mpuio_resume_noirq,
921};
922
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +0200923/* use platform_driver for this. */
David Brownell11a78b72006-12-06 17:14:11 -0800924static struct platform_driver omap_mpuio_driver = {
David Brownell11a78b72006-12-06 17:14:11 -0800925 .driver = {
926 .name = "mpuio",
Magnus Damm79ee0312009-07-08 13:22:04 +0200927 .pm = &omap_mpuio_dev_pm_ops,
David Brownell11a78b72006-12-06 17:14:11 -0800928 },
929};
930
931static struct platform_device omap_mpuio_device = {
932 .name = "mpuio",
933 .id = -1,
934 .dev = {
935 .driver = &omap_mpuio_driver.driver,
936 }
937 /* could list the /proc/iomem resources */
938};
939
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200940static inline void omap_mpuio_init(struct gpio_bank *bank)
David Brownell11a78b72006-12-06 17:14:11 -0800941{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800942 platform_set_drvdata(&omap_mpuio_device, bank);
David Brownellfcf126d2007-04-02 12:46:47 -0700943
David Brownell11a78b72006-12-06 17:14:11 -0800944 if (platform_driver_register(&omap_mpuio_driver) == 0)
945 (void) platform_device_register(&omap_mpuio_device);
946}
947
David Brownelle5c56ed2006-12-06 17:13:59 -0800948/*---------------------------------------------------------------------*/
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100949
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200950static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
Yegor Yefremov93700842014-04-24 08:57:39 +0200951{
952 struct gpio_bank *bank;
953 unsigned long flags;
954 void __iomem *reg;
955 int dir;
956
957 bank = container_of(chip, struct gpio_bank, chip);
958 reg = bank->base + bank->regs->direction;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200959 raw_spin_lock_irqsave(&bank->lock, flags);
Yegor Yefremov93700842014-04-24 08:57:39 +0200960 dir = !!(readl_relaxed(reg) & BIT(offset));
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200961 raw_spin_unlock_irqrestore(&bank->lock, flags);
Yegor Yefremov93700842014-04-24 08:57:39 +0200962 return dir;
963}
964
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200965static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
David Brownell52e31342008-03-03 12:43:23 -0800966{
967 struct gpio_bank *bank;
968 unsigned long flags;
969
970 bank = container_of(chip, struct gpio_bank, chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200971 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200972 omap_set_gpio_direction(bank, offset, 1);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200973 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell52e31342008-03-03 12:43:23 -0800974 return 0;
975}
976
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200977static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
David Brownell52e31342008-03-03 12:43:23 -0800978{
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300979 struct gpio_bank *bank;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300980
Charulatha Va8be8da2011-04-22 16:38:16 +0530981 bank = container_of(chip, struct gpio_bank, chip);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300982
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200983 if (omap_gpio_is_input(bank, offset))
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200984 return omap_get_gpio_datain(bank, offset);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300985 else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200986 return omap_get_gpio_dataout(bank, offset);
David Brownell52e31342008-03-03 12:43:23 -0800987}
988
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200989static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
David Brownell52e31342008-03-03 12:43:23 -0800990{
991 struct gpio_bank *bank;
992 unsigned long flags;
993
994 bank = container_of(chip, struct gpio_bank, chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200995 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700996 bank->set_dataout(bank, offset, value);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200997 omap_set_gpio_direction(bank, offset, 0);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200998 raw_spin_unlock_irqrestore(&bank->lock, flags);
Javier Martinez Canillas2f56e0a2013-10-16 02:47:30 +0200999 return 0;
David Brownell52e31342008-03-03 12:43:23 -08001000}
1001
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001002static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1003 unsigned debounce)
Felipe Balbi168ef3d2010-05-26 14:42:23 -07001004{
1005 struct gpio_bank *bank;
1006 unsigned long flags;
1007
1008 bank = container_of(chip, struct gpio_bank, chip);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001009
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001010 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001011 omap2_set_gpio_debounce(bank, offset, debounce);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001012 raw_spin_unlock_irqrestore(&bank->lock, flags);
Felipe Balbi168ef3d2010-05-26 14:42:23 -07001013
1014 return 0;
1015}
1016
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001017static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
David Brownell52e31342008-03-03 12:43:23 -08001018{
1019 struct gpio_bank *bank;
1020 unsigned long flags;
1021
1022 bank = container_of(chip, struct gpio_bank, chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001023 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001024 bank->set_dataout(bank, offset, value);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001025 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell52e31342008-03-03 12:43:23 -08001026}
1027
1028/*---------------------------------------------------------------------*/
1029
Tony Lindgren9a748052010-12-07 16:26:56 -08001030static void __init omap_gpio_show_rev(struct gpio_bank *bank)
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001031{
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001032 static bool called;
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001033 u32 rev;
1034
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001035 if (called || bank->regs->revision == USHRT_MAX)
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001036 return;
1037
Victor Kamensky661553b2013-11-16 02:01:04 +02001038 rev = readw_relaxed(bank->base + bank->regs->revision);
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001039 pr_info("OMAP GPIO hardware version %d.%d\n",
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001040 (rev >> 4) & 0x0f, rev & 0x0f);
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001041
1042 called = true;
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001043}
1044
Charulatha V03e128c2011-05-05 19:58:01 +05301045static void omap_gpio_mod_init(struct gpio_bank *bank)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001046{
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301047 void __iomem *base = bank->base;
1048 u32 l = 0xffffffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001049
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301050 if (bank->width == 16)
1051 l = 0xffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001052
Charulatha Vd0d665a2011-08-31 00:02:21 +05301053 if (bank->is_mpuio) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001054 writel_relaxed(l, bank->base + bank->regs->irqenable);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301055 return;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001056 }
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301057
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001058 omap_gpio_rmw(base, bank->regs->irqenable, l,
1059 bank->regs->irqenable_inv);
1060 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1061 !bank->regs->irqenable_inv);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301062 if (bank->regs->debounce_en)
Victor Kamensky661553b2013-11-16 02:01:04 +02001063 writel_relaxed(0, base + bank->regs->debounce_en);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301064
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301065 /* Save OE default value (0xffffffff) in the context */
Victor Kamensky661553b2013-11-16 02:01:04 +02001066 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301067 /* Initialize interface clk ungated, module enabled */
1068 if (bank->regs->ctrl)
Victor Kamensky661553b2013-11-16 02:01:04 +02001069 writel_relaxed(0, base + bank->regs->ctrl);
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001070}
1071
Nishanth Menon46824e22014-09-05 14:52:55 -05001072static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001073{
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001074 static int gpio;
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001075 int irq_base = 0;
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001076 int ret;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001077
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001078 /*
1079 * REVISIT eventually switch from OMAP-specific gpio structs
1080 * over to the generic ones
1081 */
1082 bank->chip.request = omap_gpio_request;
1083 bank->chip.free = omap_gpio_free;
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001084 bank->chip.get_direction = omap_gpio_get_direction;
1085 bank->chip.direction_input = omap_gpio_input;
1086 bank->chip.get = omap_gpio_get;
1087 bank->chip.direction_output = omap_gpio_output;
1088 bank->chip.set_debounce = omap_gpio_debounce;
1089 bank->chip.set = omap_gpio_set;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301090 if (bank->is_mpuio) {
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001091 bank->chip.label = "mpuio";
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +05301092 if (bank->regs->wkup_en)
1093 bank->chip.dev = &omap_mpuio_device.dev;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001094 bank->chip.base = OMAP_MPUIO(0);
1095 } else {
1096 bank->chip.label = "gpio";
1097 bank->chip.base = gpio;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001098 }
Kevin Hilmand5f46242011-04-21 09:23:00 -07001099 bank->chip.ngpio = bank->width;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001100
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001101 ret = gpiochip_add(&bank->chip);
1102 if (ret) {
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001103 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001104 return ret;
1105 }
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001106
Tony Lindgren46d4f7c2015-09-03 10:31:27 -07001107 if (!bank->is_mpuio)
1108 gpio += bank->width;
1109
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001110#ifdef CONFIG_ARCH_OMAP1
1111 /*
1112 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1113 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1114 */
1115 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1116 if (irq_base < 0) {
1117 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1118 return -ENODEV;
1119 }
1120#endif
1121
Tony Lindgrend2d05c62015-04-23 16:54:17 -07001122 /* MPUIO is a bit different, reading IRQ status clears it */
1123 if (bank->is_mpuio) {
1124 irqc->irq_ack = dummy_irq_chip.irq_ack;
1125 irqc->irq_mask = irq_gc_mask_set_bit;
1126 irqc->irq_unmask = irq_gc_mask_clr_bit;
1127 if (!bank->regs->wkup_en)
1128 irqc->irq_set_wake = NULL;
1129 }
1130
Nishanth Menon46824e22014-09-05 14:52:55 -05001131 ret = gpiochip_irqchip_add(&bank->chip, irqc,
Grygorii Strashko450fa542015-09-25 12:28:03 -07001132 irq_base, handle_bad_irq,
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001133 IRQ_TYPE_NONE);
1134
1135 if (ret) {
1136 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
Linus Walleijda26d5d2014-09-16 15:11:41 -07001137 gpiochip_remove(&bank->chip);
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001138 return -ENODEV;
1139 }
1140
Grygorii Strashko450fa542015-09-25 12:28:03 -07001141 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001142
Grygorii Strashko450fa542015-09-25 12:28:03 -07001143 ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,
1144 0, dev_name(bank->dev), bank);
1145 if (ret)
1146 gpiochip_remove(&bank->chip);
1147
1148 return ret;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001149}
1150
Benoit Cousson384ebe12011-08-16 11:53:02 +02001151static const struct of_device_id omap_gpio_match[];
1152
Bill Pemberton38363092012-11-19 13:22:34 -05001153static int omap_gpio_probe(struct platform_device *pdev)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001154{
Benoit Cousson862ff642012-02-01 15:58:56 +01001155 struct device *dev = &pdev->dev;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001156 struct device_node *node = dev->of_node;
1157 const struct of_device_id *match;
Uwe Kleine-Königf6817a22012-05-21 21:57:39 +02001158 const struct omap_gpio_platform_data *pdata;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001159 struct resource *res;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001160 struct gpio_bank *bank;
Nishanth Menon46824e22014-09-05 14:52:55 -05001161 struct irq_chip *irqc;
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001162 int ret;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001163
Benoit Cousson384ebe12011-08-16 11:53:02 +02001164 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1165
Jingoo Hane56aee12013-07-30 17:08:05 +09001166 pdata = match ? match->data : dev_get_platdata(dev);
Benoit Cousson384ebe12011-08-16 11:53:02 +02001167 if (!pdata)
Benoit Cousson96751fc2012-02-01 16:01:39 +01001168 return -EINVAL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001169
Tobias Klauser086d5852012-10-05 11:37:38 +02001170 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
Charulatha V03e128c2011-05-05 19:58:01 +05301171 if (!bank) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001172 dev_err(dev, "Memory alloc failed\n");
Benoit Cousson96751fc2012-02-01 16:01:39 +01001173 return -ENOMEM;
Charulatha V03e128c2011-05-05 19:58:01 +05301174 }
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001175
Nishanth Menon46824e22014-09-05 14:52:55 -05001176 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1177 if (!irqc)
1178 return -ENOMEM;
1179
Tony Lindgren3d009c82015-01-16 14:50:50 -08001180 irqc->irq_startup = omap_gpio_irq_startup,
Nishanth Menon46824e22014-09-05 14:52:55 -05001181 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1182 irqc->irq_ack = omap_gpio_ack_irq,
1183 irqc->irq_mask = omap_gpio_mask_irq,
1184 irqc->irq_unmask = omap_gpio_unmask_irq,
1185 irqc->irq_set_type = omap_gpio_irq_type,
1186 irqc->irq_set_wake = omap_gpio_wake_enable,
Grygorii Strashkoaca82d12015-09-25 12:28:02 -07001187 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1188 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
Nishanth Menon46824e22014-09-05 14:52:55 -05001189 irqc->name = dev_name(&pdev->dev);
1190
Grygorii Strashko89d18e32015-08-18 14:10:53 +03001191 bank->irq = platform_get_irq(pdev, 0);
1192 if (bank->irq <= 0) {
1193 if (!bank->irq)
1194 bank->irq = -ENXIO;
1195 if (bank->irq != -EPROBE_DEFER)
1196 dev_err(dev,
1197 "can't get irq resource ret=%d\n", bank->irq);
1198 return bank->irq;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001199 }
1200
Benoit Cousson862ff642012-02-01 15:58:56 +01001201 bank->dev = dev;
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001202 bank->chip.dev = dev;
Grygorii Strashkoc23837c2015-06-25 18:13:33 +03001203 bank->chip.owner = THIS_MODULE;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001204 bank->dbck_flag = pdata->dbck_flag;
Tony Lindgren5de62b82010-12-07 16:26:58 -08001205 bank->stride = pdata->bank_stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -07001206 bank->width = pdata->bank_width;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301207 bank->is_mpuio = pdata->is_mpuio;
Charulatha V803a2432011-05-05 17:04:12 +05301208 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001209 bank->regs = pdata->regs;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001210#ifdef CONFIG_OF_GPIO
1211 bank->chip.of_node = of_node_get(node);
1212#endif
Jon Huntera2797be2013-04-04 15:16:15 -05001213 if (node) {
1214 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1215 bank->loses_context = true;
1216 } else {
1217 bank->loses_context = pdata->loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -05001218
1219 if (bank->loses_context)
1220 bank->get_context_loss_count =
1221 pdata->get_context_loss_count;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001222 }
1223
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001224 if (bank->regs->set_dataout && bank->regs->clr_dataout)
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001225 bank->set_dataout = omap_set_gpio_dataout_reg;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001226 else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001227 bank->set_dataout = omap_set_gpio_dataout_mask;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001228
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001229 raw_spin_lock_init(&bank->lock);
Grygorii Strashko450fa542015-09-25 12:28:03 -07001230 raw_spin_lock_init(&bank->wa_lock);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001231
1232 /* Static mapping, never released */
1233 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Han717f70e2014-02-12 11:51:38 +09001234 bank->base = devm_ioremap_resource(dev, res);
1235 if (IS_ERR(bank->base)) {
Jingoo Han717f70e2014-02-12 11:51:38 +09001236 return PTR_ERR(bank->base);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001237 }
1238
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001239 if (bank->dbck_flag) {
1240 bank->dbck = devm_clk_get(bank->dev, "dbclk");
1241 if (IS_ERR(bank->dbck)) {
1242 dev_err(bank->dev,
1243 "Could not get gpio dbck. Disable debounce\n");
1244 bank->dbck_flag = false;
1245 } else {
1246 clk_prepare(bank->dbck);
1247 }
1248 }
1249
Tarun Kanti DebBarma065cd792011-11-24 01:48:52 +05301250 platform_set_drvdata(pdev, bank);
1251
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001252 pm_runtime_enable(bank->dev);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301253 pm_runtime_irq_safe(bank->dev);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001254 pm_runtime_get_sync(bank->dev);
1255
Charulatha Vd0d665a2011-08-31 00:02:21 +05301256 if (bank->is_mpuio)
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001257 omap_mpuio_init(bank);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301258
Charulatha V03e128c2011-05-05 19:58:01 +05301259 omap_gpio_mod_init(bank);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001260
Nishanth Menon46824e22014-09-05 14:52:55 -05001261 ret = omap_gpio_chip_init(bank, irqc);
Tony Lindgren5e606ab2015-08-28 11:44:49 -07001262 if (ret) {
1263 pm_runtime_put_sync(bank->dev);
1264 pm_runtime_disable(bank->dev);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001265 return ret;
Tony Lindgren5e606ab2015-08-28 11:44:49 -07001266 }
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001267
Tony Lindgren9a748052010-12-07 16:26:56 -08001268 omap_gpio_show_rev(bank);
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001269
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301270 pm_runtime_put(bank->dev);
1271
Charulatha V03e128c2011-05-05 19:58:01 +05301272 list_add_tail(&bank->node, &omap_gpio_list);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001273
Jon Hunter879fe322013-04-04 15:16:12 -05001274 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001275}
1276
Tony Lindgrencac089f2015-04-23 16:56:22 -07001277static int omap_gpio_remove(struct platform_device *pdev)
1278{
1279 struct gpio_bank *bank = platform_get_drvdata(pdev);
1280
1281 list_del(&bank->node);
1282 gpiochip_remove(&bank->chip);
1283 pm_runtime_disable(bank->dev);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001284 if (bank->dbck_flag)
1285 clk_unprepare(bank->dbck);
Tony Lindgrencac089f2015-04-23 16:56:22 -07001286
1287 return 0;
1288}
1289
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301290#ifdef CONFIG_ARCH_OMAP2PLUS
1291
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001292#if defined(CONFIG_PM)
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301293static void omap_gpio_restore_context(struct gpio_bank *bank);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001294
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301295static int omap_gpio_runtime_suspend(struct device *dev)
1296{
1297 struct platform_device *pdev = to_platform_device(dev);
1298 struct gpio_bank *bank = platform_get_drvdata(pdev);
1299 u32 l1 = 0, l2 = 0;
1300 unsigned long flags;
Kevin Hilman68942ed2012-03-05 15:10:04 -08001301 u32 wake_low, wake_hi;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301302
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001303 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001304
1305 /*
1306 * Only edges can generate a wakeup event to the PRCM.
1307 *
1308 * Therefore, ensure any wake-up capable GPIOs have
1309 * edge-detection enabled before going idle to ensure a wakeup
1310 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1311 * NDA TRM 25.5.3.1)
1312 *
1313 * The normal values will be restored upon ->runtime_resume()
1314 * by writing back the values saved in bank->context.
1315 */
1316 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1317 if (wake_low)
Victor Kamensky661553b2013-11-16 02:01:04 +02001318 writel_relaxed(wake_low | bank->context.fallingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001319 bank->base + bank->regs->fallingdetect);
1320 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1321 if (wake_hi)
Victor Kamensky661553b2013-11-16 02:01:04 +02001322 writel_relaxed(wake_hi | bank->context.risingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001323 bank->base + bank->regs->risingdetect);
1324
Kevin Hilmanb3c64bc2012-05-17 16:42:16 -07001325 if (!bank->enabled_non_wakeup_gpios)
1326 goto update_gpio_context_count;
1327
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301328 if (bank->power_mode != OFF_MODE) {
1329 bank->power_mode = 0;
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301330 goto update_gpio_context_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301331 }
1332 /*
1333 * If going to OFF, remove triggering for all
1334 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1335 * generated. See OMAP2420 Errata item 1.101.
1336 */
Victor Kamensky661553b2013-11-16 02:01:04 +02001337 bank->saved_datain = readl_relaxed(bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301338 bank->regs->datain);
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301339 l1 = bank->context.fallingdetect;
1340 l2 = bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301341
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301342 l1 &= ~bank->enabled_non_wakeup_gpios;
1343 l2 &= ~bank->enabled_non_wakeup_gpios;
1344
Victor Kamensky661553b2013-11-16 02:01:04 +02001345 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1346 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301347
1348 bank->workaround_enabled = true;
1349
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301350update_gpio_context_count:
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301351 if (bank->get_context_loss_count)
1352 bank->context_loss_count =
1353 bank->get_context_loss_count(bank->dev);
1354
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001355 omap_gpio_dbck_disable(bank);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001356 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301357
1358 return 0;
1359}
1360
Jon Hunter352a2d52013-04-15 13:06:54 -05001361static void omap_gpio_init_context(struct gpio_bank *p);
1362
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301363static int omap_gpio_runtime_resume(struct device *dev)
1364{
1365 struct platform_device *pdev = to_platform_device(dev);
1366 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301367 u32 l = 0, gen, gen0, gen1;
1368 unsigned long flags;
Jon Huntera2797be2013-04-04 15:16:15 -05001369 int c;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301370
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001371 raw_spin_lock_irqsave(&bank->lock, flags);
Jon Hunter352a2d52013-04-15 13:06:54 -05001372
1373 /*
1374 * On the first resume during the probe, the context has not
1375 * been initialised and so initialise it now. Also initialise
1376 * the context loss count.
1377 */
1378 if (bank->loses_context && !bank->context_valid) {
1379 omap_gpio_init_context(bank);
1380
1381 if (bank->get_context_loss_count)
1382 bank->context_loss_count =
1383 bank->get_context_loss_count(bank->dev);
1384 }
1385
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001386 omap_gpio_dbck_enable(bank);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001387
1388 /*
1389 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1390 * GPIOs were set to edge trigger also in order to be able to
1391 * generate a PRCM wakeup. Here we restore the
1392 * pre-runtime_suspend() values for edge triggering.
1393 */
Victor Kamensky661553b2013-11-16 02:01:04 +02001394 writel_relaxed(bank->context.fallingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001395 bank->base + bank->regs->fallingdetect);
Victor Kamensky661553b2013-11-16 02:01:04 +02001396 writel_relaxed(bank->context.risingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001397 bank->base + bank->regs->risingdetect);
1398
Jon Huntera2797be2013-04-04 15:16:15 -05001399 if (bank->loses_context) {
1400 if (!bank->get_context_loss_count) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301401 omap_gpio_restore_context(bank);
1402 } else {
Jon Huntera2797be2013-04-04 15:16:15 -05001403 c = bank->get_context_loss_count(bank->dev);
1404 if (c != bank->context_loss_count) {
1405 omap_gpio_restore_context(bank);
1406 } else {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001407 raw_spin_unlock_irqrestore(&bank->lock, flags);
Jon Huntera2797be2013-04-04 15:16:15 -05001408 return 0;
1409 }
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301410 }
1411 }
1412
Tarun Kanti DebBarma1b1287032012-04-27 19:43:38 +05301413 if (!bank->workaround_enabled) {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001414 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma1b1287032012-04-27 19:43:38 +05301415 return 0;
1416 }
1417
Victor Kamensky661553b2013-11-16 02:01:04 +02001418 l = readl_relaxed(bank->base + bank->regs->datain);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301419
1420 /*
1421 * Check if any of the non-wakeup interrupt GPIOs have changed
1422 * state. If so, generate an IRQ by software. This is
1423 * horribly racy, but it's the best we can do to work around
1424 * this silicon bug.
1425 */
1426 l ^= bank->saved_datain;
1427 l &= bank->enabled_non_wakeup_gpios;
1428
1429 /*
1430 * No need to generate IRQs for the rising edge for gpio IRQs
1431 * configured with falling edge only; and vice versa.
1432 */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301433 gen0 = l & bank->context.fallingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301434 gen0 &= bank->saved_datain;
1435
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301436 gen1 = l & bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301437 gen1 &= ~(bank->saved_datain);
1438
1439 /* FIXME: Consider GPIO IRQs with level detections properly! */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301440 gen = l & (~(bank->context.fallingdetect) &
1441 ~(bank->context.risingdetect));
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301442 /* Consider all GPIO IRQs needed to be updated */
1443 gen |= gen0 | gen1;
1444
1445 if (gen) {
1446 u32 old0, old1;
1447
Victor Kamensky661553b2013-11-16 02:01:04 +02001448 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1449 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301450
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301451 if (!bank->regs->irqstatus_raw0) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001452 writel_relaxed(old0 | gen, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301453 bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001454 writel_relaxed(old1 | gen, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301455 bank->regs->leveldetect1);
1456 }
1457
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301458 if (bank->regs->irqstatus_raw0) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001459 writel_relaxed(old0 | l, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301460 bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001461 writel_relaxed(old1 | l, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301462 bank->regs->leveldetect1);
1463 }
Victor Kamensky661553b2013-11-16 02:01:04 +02001464 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1465 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301466 }
1467
1468 bank->workaround_enabled = false;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001469 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301470
1471 return 0;
1472}
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001473#endif /* CONFIG_PM */
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301474
Tony Lindgrencac089f2015-04-23 16:56:22 -07001475#if IS_BUILTIN(CONFIG_GPIO_OMAP)
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301476void omap2_gpio_prepare_for_idle(int pwr_mode)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001477{
Charulatha V03e128c2011-05-05 19:58:01 +05301478 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001479
Charulatha V03e128c2011-05-05 19:58:01 +05301480 list_for_each_entry(bank, &omap_gpio_list, node) {
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +02001481 if (!BANK_USED(bank) || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301482 continue;
1483
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301484 bank->power_mode = pwr_mode;
1485
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301486 pm_runtime_put_sync_suspend(bank->dev);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001487 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001488}
1489
Kevin Hilman43ffcd92009-01-27 11:09:24 -08001490void omap2_gpio_resume_after_idle(void)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001491{
Charulatha V03e128c2011-05-05 19:58:01 +05301492 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001493
Charulatha V03e128c2011-05-05 19:58:01 +05301494 list_for_each_entry(bank, &omap_gpio_list, node) {
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +02001495 if (!BANK_USED(bank) || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301496 continue;
1497
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301498 pm_runtime_get_sync(bank->dev);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001499 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001500}
Tony Lindgrencac089f2015-04-23 16:56:22 -07001501#endif
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001502
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001503#if defined(CONFIG_PM)
Jon Hunter352a2d52013-04-15 13:06:54 -05001504static void omap_gpio_init_context(struct gpio_bank *p)
1505{
1506 struct omap_gpio_reg_offs *regs = p->regs;
1507 void __iomem *base = p->base;
1508
Victor Kamensky661553b2013-11-16 02:01:04 +02001509 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1510 p->context.oe = readl_relaxed(base + regs->direction);
1511 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1512 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1513 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1514 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1515 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1516 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1517 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
Jon Hunter352a2d52013-04-15 13:06:54 -05001518
1519 if (regs->set_dataout && p->regs->clr_dataout)
Victor Kamensky661553b2013-11-16 02:01:04 +02001520 p->context.dataout = readl_relaxed(base + regs->set_dataout);
Jon Hunter352a2d52013-04-15 13:06:54 -05001521 else
Victor Kamensky661553b2013-11-16 02:01:04 +02001522 p->context.dataout = readl_relaxed(base + regs->dataout);
Jon Hunter352a2d52013-04-15 13:06:54 -05001523
1524 p->context_valid = true;
1525}
1526
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301527static void omap_gpio_restore_context(struct gpio_bank *bank)
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301528{
Victor Kamensky661553b2013-11-16 02:01:04 +02001529 writel_relaxed(bank->context.wake_en,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301530 bank->base + bank->regs->wkup_en);
Victor Kamensky661553b2013-11-16 02:01:04 +02001531 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1532 writel_relaxed(bank->context.leveldetect0,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301533 bank->base + bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001534 writel_relaxed(bank->context.leveldetect1,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301535 bank->base + bank->regs->leveldetect1);
Victor Kamensky661553b2013-11-16 02:01:04 +02001536 writel_relaxed(bank->context.risingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301537 bank->base + bank->regs->risingdetect);
Victor Kamensky661553b2013-11-16 02:01:04 +02001538 writel_relaxed(bank->context.fallingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301539 bank->base + bank->regs->fallingdetect);
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301540 if (bank->regs->set_dataout && bank->regs->clr_dataout)
Victor Kamensky661553b2013-11-16 02:01:04 +02001541 writel_relaxed(bank->context.dataout,
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301542 bank->base + bank->regs->set_dataout);
1543 else
Victor Kamensky661553b2013-11-16 02:01:04 +02001544 writel_relaxed(bank->context.dataout,
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301545 bank->base + bank->regs->dataout);
Victor Kamensky661553b2013-11-16 02:01:04 +02001546 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
Nishanth Menon6d13eaa2011-08-29 18:54:50 +05301547
Nishanth Menonae547352011-09-09 19:08:58 +05301548 if (bank->dbck_enable_mask) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001549 writel_relaxed(bank->context.debounce, bank->base +
Nishanth Menonae547352011-09-09 19:08:58 +05301550 bank->regs->debounce);
Victor Kamensky661553b2013-11-16 02:01:04 +02001551 writel_relaxed(bank->context.debounce_en,
Nishanth Menonae547352011-09-09 19:08:58 +05301552 bank->base + bank->regs->debounce_en);
1553 }
Nishanth Menonba805be2011-08-29 18:41:08 +05301554
Victor Kamensky661553b2013-11-16 02:01:04 +02001555 writel_relaxed(bank->context.irqenable1,
Nishanth Menonba805be2011-08-29 18:41:08 +05301556 bank->base + bank->regs->irqenable);
Victor Kamensky661553b2013-11-16 02:01:04 +02001557 writel_relaxed(bank->context.irqenable2,
Nishanth Menonba805be2011-08-29 18:41:08 +05301558 bank->base + bank->regs->irqenable2);
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301559}
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001560#endif /* CONFIG_PM */
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301561#else
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301562#define omap_gpio_runtime_suspend NULL
1563#define omap_gpio_runtime_resume NULL
Arnd Bergmannea4a21a2013-05-31 17:59:46 +02001564static inline void omap_gpio_init_context(struct gpio_bank *p) {}
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301565#endif
1566
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301567static const struct dev_pm_ops gpio_pm_ops = {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301568 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1569 NULL)
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301570};
1571
Benoit Cousson384ebe12011-08-16 11:53:02 +02001572#if defined(CONFIG_OF)
1573static struct omap_gpio_reg_offs omap2_gpio_regs = {
1574 .revision = OMAP24XX_GPIO_REVISION,
1575 .direction = OMAP24XX_GPIO_OE,
1576 .datain = OMAP24XX_GPIO_DATAIN,
1577 .dataout = OMAP24XX_GPIO_DATAOUT,
1578 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1579 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1580 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1581 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1582 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1583 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1584 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1585 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1586 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1587 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1588 .ctrl = OMAP24XX_GPIO_CTRL,
1589 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1590 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1591 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1592 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1593 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1594};
1595
1596static struct omap_gpio_reg_offs omap4_gpio_regs = {
1597 .revision = OMAP4_GPIO_REVISION,
1598 .direction = OMAP4_GPIO_OE,
1599 .datain = OMAP4_GPIO_DATAIN,
1600 .dataout = OMAP4_GPIO_DATAOUT,
1601 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1602 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1603 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1604 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1605 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1606 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1607 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1608 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1609 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1610 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1611 .ctrl = OMAP4_GPIO_CTRL,
1612 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1613 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1614 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1615 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1616 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1617};
1618
Chen Gange9a65bb2013-02-06 18:44:32 +08001619static const struct omap_gpio_platform_data omap2_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001620 .regs = &omap2_gpio_regs,
1621 .bank_width = 32,
1622 .dbck_flag = false,
1623};
1624
Chen Gange9a65bb2013-02-06 18:44:32 +08001625static const struct omap_gpio_platform_data omap3_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001626 .regs = &omap2_gpio_regs,
1627 .bank_width = 32,
1628 .dbck_flag = true,
1629};
1630
Chen Gange9a65bb2013-02-06 18:44:32 +08001631static const struct omap_gpio_platform_data omap4_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001632 .regs = &omap4_gpio_regs,
1633 .bank_width = 32,
1634 .dbck_flag = true,
1635};
1636
1637static const struct of_device_id omap_gpio_match[] = {
1638 {
1639 .compatible = "ti,omap4-gpio",
1640 .data = &omap4_pdata,
1641 },
1642 {
1643 .compatible = "ti,omap3-gpio",
1644 .data = &omap3_pdata,
1645 },
1646 {
1647 .compatible = "ti,omap2-gpio",
1648 .data = &omap2_pdata,
1649 },
1650 { },
1651};
1652MODULE_DEVICE_TABLE(of, omap_gpio_match);
1653#endif
1654
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001655static struct platform_driver omap_gpio_driver = {
1656 .probe = omap_gpio_probe,
Tony Lindgrencac089f2015-04-23 16:56:22 -07001657 .remove = omap_gpio_remove,
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001658 .driver = {
1659 .name = "omap_gpio",
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301660 .pm = &gpio_pm_ops,
Benoit Cousson384ebe12011-08-16 11:53:02 +02001661 .of_match_table = of_match_ptr(omap_gpio_match),
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001662 },
1663};
1664
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001665/*
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001666 * gpio driver register needs to be done before
1667 * machine_init functions access gpio APIs.
1668 * Hence omap_gpio_drv_reg() is a postcore_initcall.
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001669 */
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001670static int __init omap_gpio_drv_reg(void)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001671{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001672 return platform_driver_register(&omap_gpio_driver);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001673}
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001674postcore_initcall(omap_gpio_drv_reg);
Tony Lindgrencac089f2015-04-23 16:56:22 -07001675
1676static void __exit omap_gpio_exit(void)
1677{
1678 platform_driver_unregister(&omap_gpio_driver);
1679}
1680module_exit(omap_gpio_exit);
1681
1682MODULE_DESCRIPTION("omap gpio driver");
1683MODULE_ALIAS("platform:gpio-omap");
1684MODULE_LICENSE("GPL v2");