Narender Ankam | dc32cdf | 2020-03-16 17:21:08 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SDE_HW_MDSS_H |
| 14 | #define _SDE_HW_MDSS_H |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/err.h> |
| 18 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 19 | #include "msm_drv.h" |
| 20 | |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 21 | #define SDE_DBG_NAME "sde" |
| 22 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 23 | #define SDE_NONE 0 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 24 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 25 | #ifndef SDE_CSC_MATRIX_COEFF_SIZE |
| 26 | #define SDE_CSC_MATRIX_COEFF_SIZE 9 |
| 27 | #endif |
| 28 | |
| 29 | #ifndef SDE_CSC_CLAMP_SIZE |
| 30 | #define SDE_CSC_CLAMP_SIZE 6 |
| 31 | #endif |
| 32 | |
| 33 | #ifndef SDE_CSC_BIAS_SIZE |
| 34 | #define SDE_CSC_BIAS_SIZE 3 |
| 35 | #endif |
| 36 | |
| 37 | #ifndef SDE_MAX_PLANES |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 38 | #define SDE_MAX_PLANES 4 |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 39 | #endif |
| 40 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 41 | #define PIPES_PER_STAGE 2 |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 42 | #ifndef SDE_MAX_DE_CURVES |
| 43 | #define SDE_MAX_DE_CURVES 3 |
| 44 | #endif |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 45 | |
abeykun | 2997c81 | 2016-10-04 11:34:15 -0400 | [diff] [blame] | 46 | enum sde_format_flags { |
| 47 | SDE_FORMAT_FLAG_YUV_BIT, |
| 48 | SDE_FORMAT_FLAG_DX_BIT, |
Alan Kwong | 4fc006e | 2017-01-29 18:19:34 -0800 | [diff] [blame] | 49 | SDE_FORMAT_FLAG_COMPRESSED_BIT, |
abeykun | 2997c81 | 2016-10-04 11:34:15 -0400 | [diff] [blame] | 50 | SDE_FORMAT_FLAG_BIT_MAX, |
| 51 | }; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 52 | |
abeykun | 2997c81 | 2016-10-04 11:34:15 -0400 | [diff] [blame] | 53 | #define SDE_FORMAT_FLAG_YUV BIT(SDE_FORMAT_FLAG_YUV_BIT) |
| 54 | #define SDE_FORMAT_FLAG_DX BIT(SDE_FORMAT_FLAG_DX_BIT) |
Alan Kwong | 4fc006e | 2017-01-29 18:19:34 -0800 | [diff] [blame] | 55 | #define SDE_FORMAT_FLAG_COMPRESSED BIT(SDE_FORMAT_FLAG_COMPRESSED_BIT) |
abeykun | 2997c81 | 2016-10-04 11:34:15 -0400 | [diff] [blame] | 56 | #define SDE_FORMAT_IS_YUV(X) \ |
| 57 | (test_bit(SDE_FORMAT_FLAG_YUV_BIT, (X)->flag)) |
| 58 | #define SDE_FORMAT_IS_DX(X) \ |
| 59 | (test_bit(SDE_FORMAT_FLAG_DX_BIT, (X)->flag)) |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 60 | #define SDE_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == SDE_FETCH_LINEAR) |
Alan Kwong | 4fc006e | 2017-01-29 18:19:34 -0800 | [diff] [blame] | 61 | #define SDE_FORMAT_IS_TILE(X) \ |
| 62 | (((X)->fetch_mode == SDE_FETCH_UBWC) && \ |
| 63 | !test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) |
| 64 | #define SDE_FORMAT_IS_UBWC(X) \ |
| 65 | (((X)->fetch_mode == SDE_FETCH_UBWC) && \ |
| 66 | test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 67 | |
Chirag Khurana | ed859f5 | 2019-11-20 18:18:12 +0530 | [diff] [blame] | 68 | #define TO_S15D16(_x_) ((_x_) << 7) |
| 69 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 70 | #define SDE_BLEND_FG_ALPHA_FG_CONST (0 << 0) |
| 71 | #define SDE_BLEND_FG_ALPHA_BG_CONST (1 << 0) |
| 72 | #define SDE_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) |
| 73 | #define SDE_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) |
| 74 | #define SDE_BLEND_FG_INV_ALPHA (1 << 2) |
| 75 | #define SDE_BLEND_FG_MOD_ALPHA (1 << 3) |
| 76 | #define SDE_BLEND_FG_INV_MOD_ALPHA (1 << 4) |
| 77 | #define SDE_BLEND_FG_TRANSP_EN (1 << 5) |
| 78 | #define SDE_BLEND_BG_ALPHA_FG_CONST (0 << 8) |
| 79 | #define SDE_BLEND_BG_ALPHA_BG_CONST (1 << 8) |
| 80 | #define SDE_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) |
| 81 | #define SDE_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) |
| 82 | #define SDE_BLEND_BG_INV_ALPHA (1 << 10) |
| 83 | #define SDE_BLEND_BG_MOD_ALPHA (1 << 11) |
| 84 | #define SDE_BLEND_BG_INV_MOD_ALPHA (1 << 12) |
| 85 | #define SDE_BLEND_BG_TRANSP_EN (1 << 13) |
| 86 | |
Dhaval Patel | aab9b52 | 2017-07-20 12:38:46 -0700 | [diff] [blame] | 87 | #define SDE_VSYNC0_SOURCE_GPIO 0 |
| 88 | #define SDE_VSYNC1_SOURCE_GPIO 1 |
| 89 | #define SDE_VSYNC2_SOURCE_GPIO 2 |
| 90 | #define SDE_VSYNC_SOURCE_INTF_0 3 |
| 91 | #define SDE_VSYNC_SOURCE_INTF_1 4 |
| 92 | #define SDE_VSYNC_SOURCE_INTF_2 5 |
| 93 | #define SDE_VSYNC_SOURCE_INTF_3 6 |
| 94 | #define SDE_VSYNC_SOURCE_WD_TIMER_4 11 |
| 95 | #define SDE_VSYNC_SOURCE_WD_TIMER_3 12 |
| 96 | #define SDE_VSYNC_SOURCE_WD_TIMER_2 13 |
| 97 | #define SDE_VSYNC_SOURCE_WD_TIMER_1 14 |
| 98 | #define SDE_VSYNC_SOURCE_WD_TIMER_0 15 |
| 99 | |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 100 | enum sde_hw_blk_type { |
| 101 | SDE_HW_BLK_TOP = 0, |
| 102 | SDE_HW_BLK_SSPP, |
| 103 | SDE_HW_BLK_LM, |
| 104 | SDE_HW_BLK_DSPP, |
Sravanthi Kollukuduru | acdc591 | 2017-06-22 14:53:00 +0530 | [diff] [blame] | 105 | SDE_HW_BLK_DS, |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 106 | SDE_HW_BLK_CTL, |
| 107 | SDE_HW_BLK_CDM, |
| 108 | SDE_HW_BLK_PINGPONG, |
| 109 | SDE_HW_BLK_INTF, |
| 110 | SDE_HW_BLK_WB, |
Jeykumar Sankaran | 5c2f070 | 2017-03-09 18:03:15 -0800 | [diff] [blame] | 111 | SDE_HW_BLK_DSC, |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 112 | SDE_HW_BLK_ROT, |
Lloyd Atkinson | 6b3b9dd | 2016-08-10 18:45:31 -0400 | [diff] [blame] | 113 | SDE_HW_BLK_MAX, |
| 114 | }; |
| 115 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 116 | enum sde_mdp { |
| 117 | MDP_TOP = 0x1, |
| 118 | MDP_MAX, |
| 119 | }; |
| 120 | |
| 121 | enum sde_sspp { |
| 122 | SSPP_NONE, |
| 123 | SSPP_VIG0, |
| 124 | SSPP_VIG1, |
| 125 | SSPP_VIG2, |
| 126 | SSPP_VIG3, |
| 127 | SSPP_RGB0, |
| 128 | SSPP_RGB1, |
| 129 | SSPP_RGB2, |
| 130 | SSPP_RGB3, |
| 131 | SSPP_DMA0, |
| 132 | SSPP_DMA1, |
| 133 | SSPP_DMA2, |
| 134 | SSPP_DMA3, |
| 135 | SSPP_CURSOR0, |
| 136 | SSPP_CURSOR1, |
| 137 | SSPP_MAX |
| 138 | }; |
| 139 | |
| 140 | enum sde_sspp_type { |
| 141 | SSPP_TYPE_VIG, |
| 142 | SSPP_TYPE_RGB, |
| 143 | SSPP_TYPE_DMA, |
| 144 | SSPP_TYPE_CURSOR, |
| 145 | SSPP_TYPE_MAX |
| 146 | }; |
| 147 | |
| 148 | enum sde_lm { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 149 | LM_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 150 | LM_1, |
| 151 | LM_2, |
| 152 | LM_3, |
| 153 | LM_4, |
| 154 | LM_5, |
| 155 | LM_6, |
| 156 | LM_MAX |
| 157 | }; |
| 158 | |
| 159 | enum sde_stage { |
| 160 | SDE_STAGE_BASE = 0, |
| 161 | SDE_STAGE_0, |
| 162 | SDE_STAGE_1, |
| 163 | SDE_STAGE_2, |
| 164 | SDE_STAGE_3, |
| 165 | SDE_STAGE_4, |
| 166 | SDE_STAGE_5, |
| 167 | SDE_STAGE_6, |
Veera Sundaram Sankaran | 370b991 | 2017-01-10 18:03:42 -0800 | [diff] [blame] | 168 | SDE_STAGE_7, |
| 169 | SDE_STAGE_8, |
| 170 | SDE_STAGE_9, |
| 171 | SDE_STAGE_10, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 172 | SDE_STAGE_MAX |
| 173 | }; |
| 174 | enum sde_dspp { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 175 | DSPP_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 176 | DSPP_1, |
| 177 | DSPP_2, |
| 178 | DSPP_3, |
| 179 | DSPP_MAX |
| 180 | }; |
| 181 | |
Sravanthi Kollukuduru | acdc591 | 2017-06-22 14:53:00 +0530 | [diff] [blame] | 182 | enum sde_ds { |
| 183 | DS_TOP, |
| 184 | DS_0, |
| 185 | DS_1, |
| 186 | DS_MAX |
| 187 | }; |
| 188 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 189 | enum sde_ctl { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 190 | CTL_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 191 | CTL_1, |
| 192 | CTL_2, |
| 193 | CTL_3, |
| 194 | CTL_4, |
| 195 | CTL_MAX |
| 196 | }; |
| 197 | |
| 198 | enum sde_cdm { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 199 | CDM_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 200 | CDM_1, |
| 201 | CDM_MAX |
| 202 | }; |
| 203 | |
| 204 | enum sde_pingpong { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 205 | PINGPONG_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 206 | PINGPONG_1, |
| 207 | PINGPONG_2, |
| 208 | PINGPONG_3, |
| 209 | PINGPONG_4, |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 210 | PINGPONG_S0, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 211 | PINGPONG_MAX |
| 212 | }; |
| 213 | |
Jeykumar Sankaran | 5c2f070 | 2017-03-09 18:03:15 -0800 | [diff] [blame] | 214 | enum sde_dsc { |
| 215 | DSC_NONE = 0, |
| 216 | DSC_0, |
| 217 | DSC_1, |
| 218 | DSC_2, |
| 219 | DSC_3, |
| 220 | DSC_4, |
| 221 | DSC_5, |
| 222 | DSC_MAX |
| 223 | }; |
| 224 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 225 | enum sde_intf { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 226 | INTF_0 = 1, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 227 | INTF_1, |
| 228 | INTF_2, |
| 229 | INTF_3, |
| 230 | INTF_4, |
| 231 | INTF_5, |
| 232 | INTF_6, |
| 233 | INTF_MAX |
| 234 | }; |
| 235 | |
| 236 | enum sde_intf_type { |
| 237 | INTF_NONE = 0x0, |
| 238 | INTF_DSI = 0x1, |
| 239 | INTF_HDMI = 0x3, |
| 240 | INTF_LCDC = 0x5, |
| 241 | INTF_EDP = 0x9, |
Dhaval Patel | 8bf7ff3 | 2016-07-20 18:13:24 -0700 | [diff] [blame] | 242 | INTF_DP = 0xa, |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 243 | INTF_TYPE_MAX, |
| 244 | |
| 245 | /* virtual interfaces */ |
| 246 | INTF_WB = 0x100, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | enum sde_intf_mode { |
| 250 | INTF_MODE_NONE = 0, |
| 251 | INTF_MODE_CMD, |
| 252 | INTF_MODE_VIDEO, |
| 253 | INTF_MODE_WB_BLOCK, |
| 254 | INTF_MODE_WB_LINE, |
| 255 | INTF_MODE_MAX |
| 256 | }; |
| 257 | |
| 258 | enum sde_wb { |
| 259 | WB_0 = 1, |
| 260 | WB_1, |
| 261 | WB_2, |
| 262 | WB_3, |
| 263 | WB_MAX |
| 264 | }; |
| 265 | |
| 266 | enum sde_ad { |
| 267 | AD_0 = 0x1, |
| 268 | AD_1, |
| 269 | AD_MAX |
| 270 | }; |
| 271 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 272 | enum sde_cwb { |
| 273 | CWB_0 = 0x1, |
| 274 | CWB_1, |
| 275 | CWB_2, |
| 276 | CWB_3, |
| 277 | CWB_MAX |
| 278 | }; |
| 279 | |
| 280 | enum sde_wd_timer { |
| 281 | WD_TIMER_0 = 0x1, |
| 282 | WD_TIMER_1, |
| 283 | WD_TIMER_2, |
| 284 | WD_TIMER_3, |
| 285 | WD_TIMER_4, |
| 286 | WD_TIMER_5, |
| 287 | WD_TIMER_MAX |
| 288 | }; |
| 289 | |
Alan Kwong | dfa8c08 | 2016-07-29 04:10:00 -0400 | [diff] [blame] | 290 | enum sde_vbif { |
| 291 | VBIF_0, |
| 292 | VBIF_1, |
| 293 | VBIF_MAX, |
| 294 | VBIF_RT = VBIF_0, |
| 295 | VBIF_NRT = VBIF_1 |
| 296 | }; |
| 297 | |
| 298 | enum sde_iommu_domain { |
| 299 | SDE_IOMMU_DOMAIN_UNSECURE, |
| 300 | SDE_IOMMU_DOMAIN_SECURE, |
| 301 | SDE_IOMMU_DOMAIN_MAX |
| 302 | }; |
| 303 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 304 | enum sde_rot { |
| 305 | ROT_0 = 1, |
| 306 | ROT_MAX |
| 307 | }; |
| 308 | |
Veera Sundaram Sankaran | 1e71ccb | 2017-05-24 18:48:50 -0700 | [diff] [blame] | 309 | enum sde_inline_rot { |
| 310 | INLINE_ROT_NONE, |
| 311 | INLINE_ROT0_SSPP, |
| 312 | INLINE_ROT0_WB, |
| 313 | INLINE_ROT_MAX |
| 314 | }; |
| 315 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 316 | /** |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 317 | * SDE HW,Component order color map |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 318 | */ |
| 319 | enum { |
| 320 | C0_G_Y = 0, |
| 321 | C1_B_Cb = 1, |
| 322 | C2_R_Cr = 2, |
| 323 | C3_ALPHA = 3 |
| 324 | }; |
| 325 | |
| 326 | /** |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 327 | * enum sde_plane_type - defines how the color component pixel packing |
| 328 | * @SDE_PLANE_INTERLEAVED : Color components in single plane |
| 329 | * @SDE_PLANE_PLANAR : Color component in separate planes |
| 330 | * @SDE_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 331 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 332 | enum sde_plane_type { |
| 333 | SDE_PLANE_INTERLEAVED, |
| 334 | SDE_PLANE_PLANAR, |
| 335 | SDE_PLANE_PSEUDO_PLANAR, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | /** |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 339 | * enum sde_chroma_samp_type - chroma sub-samplng type |
| 340 | * @SDE_CHROMA_RGB : No chroma subsampling |
| 341 | * @SDE_CHROMA_H2V1 : Chroma pixels are horizontally subsampled |
| 342 | * @SDE_CHROMA_H1V2 : Chroma pixels are vertically subsampled |
| 343 | * @SDE_CHROMA_420 : 420 subsampling |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 344 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 345 | enum sde_chroma_samp_type { |
| 346 | SDE_CHROMA_RGB, |
| 347 | SDE_CHROMA_H2V1, |
| 348 | SDE_CHROMA_H1V2, |
| 349 | SDE_CHROMA_420 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 350 | }; |
| 351 | |
| 352 | /** |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 353 | * sde_fetch_type - Defines How SDE HW fetches data |
| 354 | * @SDE_FETCH_LINEAR : fetch is line by line |
| 355 | * @SDE_FETCH_TILE : fetches data in Z order from a tile |
| 356 | * @SDE_FETCH_UBWC : fetch and decompress data |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 357 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 358 | enum sde_fetch_type { |
| 359 | SDE_FETCH_LINEAR, |
| 360 | SDE_FETCH_TILE, |
| 361 | SDE_FETCH_UBWC |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | /** |
| 365 | * Value of enum chosen to fit the number of bits |
| 366 | * expected by the HW programming. |
| 367 | */ |
| 368 | enum { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 369 | COLOR_ALPHA_1BIT = 0, |
| 370 | COLOR_ALPHA_4BIT = 1, |
| 371 | COLOR_4BIT = 0, |
| 372 | COLOR_5BIT = 1, /* No 5-bit Alpha */ |
| 373 | COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ |
| 374 | COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 375 | }; |
| 376 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 377 | /** |
| 378 | * enum sde_3d_blend_mode |
| 379 | * Desribes how the 3d data is blended |
| 380 | * @BLEND_3D_NONE : 3d blending not enabled |
| 381 | * @BLEND_3D_FRAME_INT : Frame interleaving |
| 382 | * @BLEND_3D_H_ROW_INT : Horizontal row interleaving |
| 383 | * @BLEND_3D_V_ROW_INT : vertical row interleaving |
| 384 | * @BLEND_3D_COL_INT : column interleaving |
| 385 | * @BLEND_3D_MAX : |
| 386 | */ |
| 387 | enum sde_3d_blend_mode { |
| 388 | BLEND_3D_NONE = 0, |
| 389 | BLEND_3D_FRAME_INT, |
| 390 | BLEND_3D_H_ROW_INT, |
| 391 | BLEND_3D_V_ROW_INT, |
| 392 | BLEND_3D_COL_INT, |
| 393 | BLEND_3D_MAX |
| 394 | }; |
| 395 | |
Chirag Khurana | ed859f5 | 2019-11-20 18:18:12 +0530 | [diff] [blame] | 396 | enum sde_csc_type { |
| 397 | SDE_CSC_RGB2YUV_601L, |
| 398 | SDE_CSC_RGB2YUV_601FR, |
Narender Ankam | dc32cdf | 2020-03-16 17:21:08 +0530 | [diff] [blame^] | 399 | SDE_CSC_RGB2YUV_709L, |
| 400 | SDE_CSC_RGB2YUV_2020L, |
| 401 | SDE_CSC_RGB2YUV_2020FR, |
Chirag Khurana | ed859f5 | 2019-11-20 18:18:12 +0530 | [diff] [blame] | 402 | SDE_MAX_CSC |
| 403 | }; |
| 404 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 405 | /** struct sde_format - defines the format configuration which |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 406 | * allows SDE HW to correctly fetch and decode the format |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 407 | * @base: base msm_format struture containing fourcc code |
| 408 | * @fetch_planes: how the color components are packed in pixel format |
| 409 | * @element: element color ordering |
| 410 | * @bits: element bit widths |
| 411 | * @chroma_sample: chroma sub-samplng type |
| 412 | * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB |
| 413 | * @unpack_tight: 0 for loose, 1 for tight |
| 414 | * @unpack_count: 0 = 1 component, 1 = 2 component |
| 415 | * @bpp: bytes per pixel |
| 416 | * @alpha_enable: whether the format has an alpha channel |
| 417 | * @num_planes: number of planes (including meta data planes) |
| 418 | * @fetch_mode: linear, tiled, or ubwc hw fetch behavior |
| 419 | * @is_yuv: is format a yuv variant |
| 420 | * @flag: usage bit flags |
| 421 | * @tile_width: format tile width |
| 422 | * @tile_height: format tile height |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 423 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 424 | struct sde_format { |
| 425 | struct msm_format base; |
| 426 | enum sde_plane_type fetch_planes; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 427 | u8 element[SDE_MAX_PLANES]; |
| 428 | u8 bits[SDE_MAX_PLANES]; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 429 | enum sde_chroma_samp_type chroma_sample; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 430 | u8 unpack_align_msb; |
| 431 | u8 unpack_tight; |
| 432 | u8 unpack_count; |
| 433 | u8 bpp; |
| 434 | u8 alpha_enable; |
| 435 | u8 num_planes; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 436 | enum sde_fetch_type fetch_mode; |
abeykun | 2997c81 | 2016-10-04 11:34:15 -0400 | [diff] [blame] | 437 | DECLARE_BITMAP(flag, SDE_FORMAT_FLAG_BIT_MAX); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 438 | u16 tile_width; |
| 439 | u16 tile_height; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 440 | }; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 441 | #define to_sde_format(x) container_of(x, struct sde_format, base) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 442 | |
| 443 | /** |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 444 | * struct sde_hw_fmt_layout - format information of the source pixel data |
| 445 | * @format: pixel format parameters |
| 446 | * @num_planes: number of planes (including meta data planes) |
| 447 | * @width: image width |
| 448 | * @height: image height |
| 449 | * @total_size: total size in bytes |
| 450 | * @plane_addr: address of each plane |
| 451 | * @plane_size: length of each plane |
| 452 | * @plane_pitch: pitch of each plane |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 453 | */ |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 454 | struct sde_hw_fmt_layout { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 455 | const struct sde_format *format; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 456 | uint32_t num_planes; |
| 457 | uint32_t width; |
| 458 | uint32_t height; |
| 459 | uint32_t total_size; |
| 460 | uint32_t plane_addr[SDE_MAX_PLANES]; |
| 461 | uint32_t plane_size[SDE_MAX_PLANES]; |
| 462 | uint32_t plane_pitch[SDE_MAX_PLANES]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 463 | }; |
| 464 | |
| 465 | struct sde_rect { |
| 466 | u16 x; |
| 467 | u16 y; |
| 468 | u16 w; |
| 469 | u16 h; |
| 470 | }; |
| 471 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 472 | struct sde_csc_cfg { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 473 | /* matrix coefficients in S15.16 format */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 474 | uint32_t csc_mv[SDE_CSC_MATRIX_COEFF_SIZE]; |
| 475 | uint32_t csc_pre_bv[SDE_CSC_BIAS_SIZE]; |
| 476 | uint32_t csc_post_bv[SDE_CSC_BIAS_SIZE]; |
| 477 | uint32_t csc_pre_lv[SDE_CSC_CLAMP_SIZE]; |
| 478 | uint32_t csc_post_lv[SDE_CSC_CLAMP_SIZE]; |
| 479 | }; |
| 480 | |
| 481 | /** |
| 482 | * struct sde_mdss_color - mdss color description |
| 483 | * color 0 : green |
| 484 | * color 1 : blue |
| 485 | * color 2 : red |
| 486 | * color 3 : alpha |
| 487 | */ |
| 488 | struct sde_mdss_color { |
| 489 | u32 color_0; |
| 490 | u32 color_1; |
| 491 | u32 color_2; |
| 492 | u32 color_3; |
| 493 | }; |
| 494 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 495 | /* |
| 496 | * Define bit masks for h/w logging. |
| 497 | */ |
| 498 | #define SDE_DBG_MASK_NONE (1 << 0) |
| 499 | #define SDE_DBG_MASK_CDM (1 << 1) |
| 500 | #define SDE_DBG_MASK_DSPP (1 << 2) |
| 501 | #define SDE_DBG_MASK_INTF (1 << 3) |
| 502 | #define SDE_DBG_MASK_LM (1 << 4) |
| 503 | #define SDE_DBG_MASK_CTL (1 << 5) |
| 504 | #define SDE_DBG_MASK_PINGPONG (1 << 6) |
| 505 | #define SDE_DBG_MASK_SSPP (1 << 7) |
| 506 | #define SDE_DBG_MASK_WB (1 << 8) |
Lloyd Atkinson | bb87b5b | 2016-06-13 18:31:15 -0400 | [diff] [blame] | 507 | #define SDE_DBG_MASK_TOP (1 << 9) |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 508 | #define SDE_DBG_MASK_VBIF (1 << 10) |
Jeykumar Sankaran | 5c2f070 | 2017-03-09 18:03:15 -0800 | [diff] [blame] | 509 | #define SDE_DBG_MASK_DSC (1 << 11) |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 510 | #define SDE_DBG_MASK_ROT (1 << 12) |
Sravanthi Kollukuduru | acdc591 | 2017-06-22 14:53:00 +0530 | [diff] [blame] | 511 | #define SDE_DBG_MASK_DS (1 << 13) |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 512 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 513 | /** |
| 514 | * struct sde_hw_cp_cfg: hardware dspp/lm feature payload. |
| 515 | * @payload: Feature specific payload. |
| 516 | * @len: Length of the payload. |
Gopikrishnaiah Anandan | 7e3e3f5 | 2016-12-22 11:13:05 -0800 | [diff] [blame] | 517 | * @ctl: control pointer associated with dspp/lm. |
Gopikrishnaiah Anandan | f5818e0 | 2017-01-30 10:46:58 -0800 | [diff] [blame] | 518 | * @last_feature: last feature that will be set. |
Gopikrishnaiah Anandan | 9ba4378 | 2017-01-31 18:23:08 -0800 | [diff] [blame] | 519 | * @num_of_mixers: number of layer mixers for the display. |
| 520 | * @mixer_info: mixer info pointer associated with lm. |
| 521 | * @displayv: height of the display. |
| 522 | * @displayh: width of the display. |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 523 | */ |
| 524 | struct sde_hw_cp_cfg { |
| 525 | void *payload; |
| 526 | u32 len; |
Gopikrishnaiah Anandan | 7e3e3f5 | 2016-12-22 11:13:05 -0800 | [diff] [blame] | 527 | void *ctl; |
Gopikrishnaiah Anandan | f5818e0 | 2017-01-30 10:46:58 -0800 | [diff] [blame] | 528 | u32 last_feature; |
Gopikrishnaiah Anandan | 9ba4378 | 2017-01-31 18:23:08 -0800 | [diff] [blame] | 529 | u32 num_of_mixers; |
| 530 | void *mixer_info; |
| 531 | u32 displayv; |
| 532 | u32 displayh; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 533 | }; |
| 534 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 535 | /** |
| 536 | * struct sde_hw_dim_layer: dim layer configs |
| 537 | * @flags: Flag to represent INCLUSIVE/EXCLUSIVE |
| 538 | * @stage: Blending stage of dim layer |
| 539 | * @color_fill: Color fill to be used for the layer |
| 540 | * @rect: Dim layer coordinates |
| 541 | */ |
| 542 | struct sde_hw_dim_layer { |
| 543 | uint32_t flags; |
| 544 | uint32_t stage; |
| 545 | struct sde_mdss_color color_fill; |
| 546 | struct sde_rect rect; |
| 547 | }; |
| 548 | |
Shashank Babu Chinta Venkata | 5d641d4 | 2017-09-29 12:16:28 -0700 | [diff] [blame] | 549 | /** |
| 550 | * struct sde_splash_lm_hw - Struct contains LM block properties |
| 551 | * @lm_id: stores the current LM ID |
| 552 | * @ctl_id: stores the current CTL ID associated with the LM. |
| 553 | * @lm_reg_value:Store the LM block register value |
| 554 | */ |
| 555 | struct sde_splash_lm_hw { |
| 556 | u8 lm_id; |
| 557 | u8 ctl_id; |
| 558 | u32 lm_reg_value; |
| 559 | }; |
| 560 | |
| 561 | /** |
| 562 | * struct ctl_top - Struct contains CTL block properties |
| 563 | * @value: Store the CTL block register value |
| 564 | * @mode_sel: stores the mode selected in the CTL block |
| 565 | * @dspp_sel: stores the dspp selected in the CTL block |
| 566 | * @pp_sel: stores the pp selected in the CTL block |
| 567 | * @intf_sel: stores the intf selected in the CTL block |
| 568 | * @lm: Pointer to store the list of LMs in the CTL block |
| 569 | * @ctl_lm_cnt: stores the active number of MDSS "LM" blocks in the CTL block |
| 570 | */ |
| 571 | struct ctl_top { |
| 572 | u32 value; |
| 573 | u8 mode_sel; |
| 574 | u8 dspp_sel; |
| 575 | u8 pp_sel; |
| 576 | u8 intf_sel; |
| 577 | struct sde_splash_lm_hw lm[LM_MAX - LM_0]; |
| 578 | u8 ctl_lm_cnt; |
| 579 | }; |
| 580 | |
| 581 | /** |
| 582 | * struct sde_splash_data - Struct contains details of continuous splash |
Chandan Uddaraju | 9bb109a | 2017-10-29 18:08:51 -0700 | [diff] [blame] | 583 | * memory region and initial pipeline configuration. |
Gopikrishnaiah Anandan | b38d329 | 2018-02-28 19:25:15 -0800 | [diff] [blame] | 584 | * @resource_handoff_pending: boolean to notify boot up resource handoff |
| 585 | * is pending. |
Chandan Uddaraju | 9bb109a | 2017-10-29 18:08:51 -0700 | [diff] [blame] | 586 | * @splash_base: Base address of continuous splash region reserved |
| 587 | * by bootloader |
| 588 | * @splash_size: Size of continuous splash region |
Shashank Babu Chinta Venkata | 5d641d4 | 2017-09-29 12:16:28 -0700 | [diff] [blame] | 589 | * @top: struct ctl_top objects |
| 590 | * @ctl_ids: stores the valid MDSS ctl block ids for the current mode |
| 591 | * @lm_ids: stores the valid MDSS layer mixer block ids for the current mode |
| 592 | * @dsc_ids: stores the valid MDSS DSC block ids for the current mode |
| 593 | * @ctl_top_cnt:stores the active number of MDSS "top" blks of the current mode |
| 594 | * @lm_cnt: stores the active number of MDSS "LM" blks for the current mode |
| 595 | * @dsc_cnt: stores the active number of MDSS "dsc" blks for the current mode |
Chandan Uddaraju | 9efbbe3 | 2017-11-09 23:57:05 -0800 | [diff] [blame] | 596 | * @cont_splash_en: Stores the cont_splash status (enabled/disbled) |
Ingrid Gallardo | 72cd163 | 2018-02-28 15:26:37 -0800 | [diff] [blame] | 597 | * @single_flush_en: Stores if the single flush is enabled. |
Shashank Babu Chinta Venkata | 5d641d4 | 2017-09-29 12:16:28 -0700 | [diff] [blame] | 598 | */ |
| 599 | struct sde_splash_data { |
Gopikrishnaiah Anandan | b38d329 | 2018-02-28 19:25:15 -0800 | [diff] [blame] | 600 | bool resource_handoff_pending; |
Chandan Uddaraju | 9bb109a | 2017-10-29 18:08:51 -0700 | [diff] [blame] | 601 | unsigned long splash_base; |
| 602 | u32 splash_size; |
Shashank Babu Chinta Venkata | 5d641d4 | 2017-09-29 12:16:28 -0700 | [diff] [blame] | 603 | struct ctl_top top[CTL_MAX - CTL_0]; |
| 604 | u8 ctl_ids[CTL_MAX - CTL_0]; |
| 605 | u8 lm_ids[LM_MAX - LM_0]; |
| 606 | u8 dsc_ids[DSC_MAX - DSC_0]; |
| 607 | u8 ctl_top_cnt; |
| 608 | u8 lm_cnt; |
| 609 | u8 dsc_cnt; |
Chandan Uddaraju | 9efbbe3 | 2017-11-09 23:57:05 -0800 | [diff] [blame] | 610 | bool cont_splash_en; |
Ingrid Gallardo | 72cd163 | 2018-02-28 15:26:37 -0800 | [diff] [blame] | 611 | bool single_flush_en; |
Shashank Babu Chinta Venkata | 5d641d4 | 2017-09-29 12:16:28 -0700 | [diff] [blame] | 612 | }; |
| 613 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 614 | #endif /* _SDE_HW_MDSS_H */ |