David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains code to reset and initialize USB host controllers. |
| 3 | * Some of it includes work-arounds for PCI hardware and BIOS quirks. |
| 4 | * It may need to run early during booting -- before USB would normally |
| 5 | * initialize -- to ensure that Linux doesn't use any legacy modes. |
| 6 | * |
| 7 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
| 8 | * (and others) |
| 9 | */ |
| 10 | |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 11 | #include <linux/types.h> |
Sarah Sharp | 51c9e6c | 2012-04-16 10:56:47 -0700 | [diff] [blame] | 12 | #include <linux/kconfig.h> |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 15 | #include <linux/delay.h> |
Paul Gortmaker | f940fcd | 2011-05-27 09:56:31 -0400 | [diff] [blame] | 16 | #include <linux/export.h> |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 17 | #include <linux/acpi.h> |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 18 | #include <linux/dmi.h> |
Adrian Bunk | 75e2df6 | 2006-03-25 18:01:53 +0100 | [diff] [blame] | 19 | #include "pci-quirks.h" |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 20 | #include "xhci-ext-caps.h" |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 21 | |
| 22 | |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 23 | #define UHCI_USBLEGSUP 0xc0 /* legacy support */ |
| 24 | #define UHCI_USBCMD 0 /* command register */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 25 | #define UHCI_USBINTR 4 /* interrupt register */ |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 26 | #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
| 27 | #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ |
| 28 | #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ |
| 29 | #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ |
| 30 | #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
| 31 | #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ |
| 32 | #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 33 | |
| 34 | #define OHCI_CONTROL 0x04 |
| 35 | #define OHCI_CMDSTATUS 0x08 |
| 36 | #define OHCI_INTRSTATUS 0x0c |
| 37 | #define OHCI_INTRENABLE 0x10 |
| 38 | #define OHCI_INTRDISABLE 0x14 |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 39 | #define OHCI_FMINTERVAL 0x34 |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 40 | #define OHCI_HCFS (3 << 6) /* hc functional state */ |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 41 | #define OHCI_HCR (1 << 0) /* host controller reset */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 42 | #define OHCI_OCR (1 << 3) /* ownership change request */ |
David Brownell | f2cb36c | 2005-09-22 22:43:30 -0700 | [diff] [blame] | 43 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 44 | #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
| 45 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ |
| 46 | |
| 47 | #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ |
| 48 | #define EHCI_USBCMD 0 /* command register */ |
| 49 | #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ |
| 50 | #define EHCI_USBSTS 4 /* status register */ |
| 51 | #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ |
| 52 | #define EHCI_USBINTR 8 /* interrupt register */ |
Alan Stern | 4fe5354 | 2007-04-05 16:06:53 -0400 | [diff] [blame] | 53 | #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 54 | #define EHCI_USBLEGSUP 0 /* legacy support register */ |
| 55 | #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ |
| 56 | #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ |
| 57 | #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ |
| 58 | #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ |
| 59 | |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 60 | /* AMD quirk use */ |
| 61 | #define AB_REG_BAR_LOW 0xe0 |
| 62 | #define AB_REG_BAR_HIGH 0xe1 |
| 63 | #define AB_REG_BAR_SB700 0xf0 |
| 64 | #define AB_INDX(addr) ((addr) + 0x00) |
| 65 | #define AB_DATA(addr) ((addr) + 0x04) |
| 66 | #define AX_INDXC 0x30 |
| 67 | #define AX_DATAC 0x34 |
| 68 | |
| 69 | #define NB_PCIE_INDX_ADDR 0xe0 |
| 70 | #define NB_PCIE_INDX_DATA 0xe4 |
| 71 | #define PCIE_P_CNTL 0x10040 |
| 72 | #define BIF_NB 0x10002 |
| 73 | #define NB_PIF0_PWRDOWN_0 0x01100012 |
| 74 | #define NB_PIF0_PWRDOWN_1 0x01100013 |
| 75 | |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 76 | #define USB_INTEL_XUSB2PR 0xD0 |
Keng-Yu Lin | a96874a | 2012-08-10 01:39:23 +0800 | [diff] [blame] | 77 | #define USB_INTEL_USB2PRM 0xD4 |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 78 | #define USB_INTEL_USB3_PSSEN 0xD8 |
Keng-Yu Lin | a96874a | 2012-08-10 01:39:23 +0800 | [diff] [blame] | 79 | #define USB_INTEL_USB3PRM 0xDC |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 80 | |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 81 | /* |
| 82 | * amd_chipset_gen values represent AMD different chipset generations |
| 83 | */ |
| 84 | enum amd_chipset_gen { |
| 85 | NOT_AMD_CHIPSET = 0, |
| 86 | AMD_CHIPSET_SB600, |
| 87 | AMD_CHIPSET_SB700, |
| 88 | AMD_CHIPSET_SB800, |
| 89 | AMD_CHIPSET_HUDSON2, |
| 90 | AMD_CHIPSET_BOLTON, |
| 91 | AMD_CHIPSET_YANGTZE, |
| 92 | AMD_CHIPSET_UNKNOWN, |
| 93 | }; |
| 94 | |
| 95 | struct amd_chipset_type { |
| 96 | enum amd_chipset_gen gen; |
| 97 | u8 rev; |
| 98 | }; |
| 99 | |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 100 | static struct amd_chipset_info { |
| 101 | struct pci_dev *nb_dev; |
| 102 | struct pci_dev *smbus_dev; |
| 103 | int nb_type; |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 104 | struct amd_chipset_type sb_type; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 105 | int isoc_reqs; |
| 106 | int probe_count; |
| 107 | int probe_result; |
| 108 | } amd_chipset; |
| 109 | |
| 110 | static DEFINE_SPINLOCK(amd_lock); |
| 111 | |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 112 | /* |
| 113 | * amd_chipset_sb_type_init - initialize amd chipset southbridge type |
| 114 | * |
| 115 | * AMD FCH/SB generation and revision is identified by SMBus controller |
| 116 | * vendor, device and revision IDs. |
| 117 | * |
| 118 | * Returns: 1 if it is an AMD chipset, 0 otherwise. |
| 119 | */ |
Fengguang Wu | 40b3dc6 | 2013-09-26 11:56:44 -0700 | [diff] [blame] | 120 | static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 121 | { |
| 122 | u8 rev = 0; |
| 123 | pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; |
| 124 | |
| 125 | pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, |
| 126 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); |
| 127 | if (pinfo->smbus_dev) { |
| 128 | rev = pinfo->smbus_dev->revision; |
| 129 | if (rev >= 0x10 && rev <= 0x1f) |
| 130 | pinfo->sb_type.gen = AMD_CHIPSET_SB600; |
| 131 | else if (rev >= 0x30 && rev <= 0x3f) |
| 132 | pinfo->sb_type.gen = AMD_CHIPSET_SB700; |
| 133 | else if (rev >= 0x40 && rev <= 0x4f) |
| 134 | pinfo->sb_type.gen = AMD_CHIPSET_SB800; |
| 135 | } else { |
| 136 | pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, |
| 137 | PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); |
| 138 | |
| 139 | if (!pinfo->smbus_dev) { |
| 140 | pinfo->sb_type.gen = NOT_AMD_CHIPSET; |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | rev = pinfo->smbus_dev->revision; |
| 145 | if (rev >= 0x11 && rev <= 0x14) |
| 146 | pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; |
| 147 | else if (rev >= 0x15 && rev <= 0x18) |
| 148 | pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; |
| 149 | else if (rev >= 0x39 && rev <= 0x3a) |
| 150 | pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; |
| 151 | } |
| 152 | |
| 153 | pinfo->sb_type.rev = rev; |
| 154 | return 1; |
| 155 | } |
| 156 | |
Manjunath Goudar | 2621d01 | 2013-05-28 18:34:50 +0530 | [diff] [blame] | 157 | void sb800_prefetch(struct device *dev, int on) |
| 158 | { |
| 159 | u16 misc; |
| 160 | struct pci_dev *pdev = to_pci_dev(dev); |
| 161 | |
| 162 | pci_read_config_word(pdev, 0x50, &misc); |
| 163 | if (on == 0) |
| 164 | pci_write_config_word(pdev, 0x50, misc & 0xfcff); |
| 165 | else |
| 166 | pci_write_config_word(pdev, 0x50, misc | 0x0300); |
| 167 | } |
| 168 | EXPORT_SYMBOL_GPL(sb800_prefetch); |
| 169 | |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 170 | int usb_amd_find_chipset_info(void) |
| 171 | { |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 172 | unsigned long flags; |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 173 | struct amd_chipset_info info; |
| 174 | int ret; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 175 | |
| 176 | spin_lock_irqsave(&amd_lock, flags); |
| 177 | |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 178 | /* probe only once */ |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 179 | if (amd_chipset.probe_count > 0) { |
| 180 | amd_chipset.probe_count++; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 181 | spin_unlock_irqrestore(&amd_lock, flags); |
| 182 | return amd_chipset.probe_result; |
| 183 | } |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 184 | memset(&info, 0, sizeof(info)); |
| 185 | spin_unlock_irqrestore(&amd_lock, flags); |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 186 | |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 187 | if (!amd_chipset_sb_type_init(&info)) { |
| 188 | ret = 0; |
| 189 | goto commit; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 190 | } |
| 191 | |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 192 | /* Below chipset generations needn't enable AMD PLL quirk */ |
| 193 | if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN || |
| 194 | info.sb_type.gen == AMD_CHIPSET_SB600 || |
| 195 | info.sb_type.gen == AMD_CHIPSET_YANGTZE || |
| 196 | (info.sb_type.gen == AMD_CHIPSET_SB700 && |
| 197 | info.sb_type.rev > 0x3b)) { |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 198 | if (info.smbus_dev) { |
| 199 | pci_dev_put(info.smbus_dev); |
| 200 | info.smbus_dev = NULL; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 201 | } |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 202 | ret = 0; |
| 203 | goto commit; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 204 | } |
| 205 | |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 206 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); |
| 207 | if (info.nb_dev) { |
| 208 | info.nb_type = 1; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 209 | } else { |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 210 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); |
| 211 | if (info.nb_dev) { |
| 212 | info.nb_type = 2; |
| 213 | } else { |
| 214 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, |
| 215 | 0x9600, NULL); |
| 216 | if (info.nb_dev) |
| 217 | info.nb_type = 3; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 218 | } |
| 219 | } |
| 220 | |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 221 | ret = info.probe_result = 1; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 222 | printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); |
| 223 | |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 224 | commit: |
| 225 | |
| 226 | spin_lock_irqsave(&amd_lock, flags); |
| 227 | if (amd_chipset.probe_count > 0) { |
| 228 | /* race - someone else was faster - drop devices */ |
| 229 | |
| 230 | /* Mark that we where here */ |
| 231 | amd_chipset.probe_count++; |
| 232 | ret = amd_chipset.probe_result; |
| 233 | |
| 234 | spin_unlock_irqrestore(&amd_lock, flags); |
| 235 | |
| 236 | if (info.nb_dev) |
| 237 | pci_dev_put(info.nb_dev); |
| 238 | if (info.smbus_dev) |
| 239 | pci_dev_put(info.smbus_dev); |
| 240 | |
| 241 | } else { |
| 242 | /* no race - commit the result */ |
| 243 | info.probe_count++; |
| 244 | amd_chipset = info; |
| 245 | spin_unlock_irqrestore(&amd_lock, flags); |
| 246 | } |
| 247 | |
| 248 | return ret; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 249 | } |
| 250 | EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); |
| 251 | |
Huang Rui | 7868943 | 2013-09-16 23:47:28 +0800 | [diff] [blame] | 252 | int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) |
| 253 | { |
| 254 | /* Make sure amd chipset type has already been initialized */ |
| 255 | usb_amd_find_chipset_info(); |
| 256 | if (amd_chipset.sb_type.gen != AMD_CHIPSET_YANGTZE) |
| 257 | return 0; |
| 258 | |
| 259 | dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); |
| 260 | return 1; |
| 261 | } |
| 262 | EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); |
| 263 | |
Huang Rui | 3ad145b | 2013-10-03 23:37:12 +0800 | [diff] [blame] | 264 | bool usb_amd_hang_symptom_quirk(void) |
| 265 | { |
| 266 | u8 rev; |
| 267 | |
| 268 | usb_amd_find_chipset_info(); |
| 269 | rev = amd_chipset.sb_type.rev; |
| 270 | /* SB600 and old version of SB700 have hang symptom bug */ |
| 271 | return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 || |
| 272 | (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && |
| 273 | rev >= 0x3a && rev <= 0x3b); |
| 274 | } |
| 275 | EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk); |
| 276 | |
Huang Rui | 02c123e | 2013-10-03 23:37:13 +0800 | [diff] [blame] | 277 | bool usb_amd_prefetch_quirk(void) |
| 278 | { |
| 279 | usb_amd_find_chipset_info(); |
| 280 | /* SB800 needs pre-fetch fix */ |
| 281 | return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800; |
| 282 | } |
| 283 | EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk); |
| 284 | |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 285 | /* |
| 286 | * The hardware normally enables the A-link power management feature, which |
| 287 | * lets the system lower the power consumption in idle states. |
| 288 | * |
| 289 | * This USB quirk prevents the link going into that lower power state |
| 290 | * during isochronous transfers. |
| 291 | * |
| 292 | * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of |
| 293 | * some AMD platforms may stutter or have breaks occasionally. |
| 294 | */ |
| 295 | static void usb_amd_quirk_pll(int disable) |
| 296 | { |
| 297 | u32 addr, addr_low, addr_high, val; |
| 298 | u32 bit = disable ? 0 : 1; |
| 299 | unsigned long flags; |
| 300 | |
| 301 | spin_lock_irqsave(&amd_lock, flags); |
| 302 | |
| 303 | if (disable) { |
| 304 | amd_chipset.isoc_reqs++; |
| 305 | if (amd_chipset.isoc_reqs > 1) { |
| 306 | spin_unlock_irqrestore(&amd_lock, flags); |
| 307 | return; |
| 308 | } |
| 309 | } else { |
| 310 | amd_chipset.isoc_reqs--; |
| 311 | if (amd_chipset.isoc_reqs > 0) { |
| 312 | spin_unlock_irqrestore(&amd_lock, flags); |
| 313 | return; |
| 314 | } |
| 315 | } |
| 316 | |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 317 | if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || |
| 318 | amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || |
| 319 | amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 320 | outb_p(AB_REG_BAR_LOW, 0xcd6); |
| 321 | addr_low = inb_p(0xcd7); |
| 322 | outb_p(AB_REG_BAR_HIGH, 0xcd6); |
| 323 | addr_high = inb_p(0xcd7); |
| 324 | addr = addr_high << 8 | addr_low; |
| 325 | |
| 326 | outl_p(0x30, AB_INDX(addr)); |
| 327 | outl_p(0x40, AB_DATA(addr)); |
| 328 | outl_p(0x34, AB_INDX(addr)); |
| 329 | val = inl_p(AB_DATA(addr)); |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 330 | } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && |
| 331 | amd_chipset.sb_type.rev <= 0x3b) { |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 332 | pci_read_config_dword(amd_chipset.smbus_dev, |
| 333 | AB_REG_BAR_SB700, &addr); |
| 334 | outl(AX_INDXC, AB_INDX(addr)); |
| 335 | outl(0x40, AB_DATA(addr)); |
| 336 | outl(AX_DATAC, AB_INDX(addr)); |
| 337 | val = inl(AB_DATA(addr)); |
| 338 | } else { |
| 339 | spin_unlock_irqrestore(&amd_lock, flags); |
| 340 | return; |
| 341 | } |
| 342 | |
| 343 | if (disable) { |
| 344 | val &= ~0x08; |
| 345 | val |= (1 << 4) | (1 << 9); |
| 346 | } else { |
| 347 | val |= 0x08; |
| 348 | val &= ~((1 << 4) | (1 << 9)); |
| 349 | } |
| 350 | outl_p(val, AB_DATA(addr)); |
| 351 | |
| 352 | if (!amd_chipset.nb_dev) { |
| 353 | spin_unlock_irqrestore(&amd_lock, flags); |
| 354 | return; |
| 355 | } |
| 356 | |
| 357 | if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { |
| 358 | addr = PCIE_P_CNTL; |
| 359 | pci_write_config_dword(amd_chipset.nb_dev, |
| 360 | NB_PCIE_INDX_ADDR, addr); |
| 361 | pci_read_config_dword(amd_chipset.nb_dev, |
| 362 | NB_PCIE_INDX_DATA, &val); |
| 363 | |
| 364 | val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); |
| 365 | val |= bit | (bit << 3) | (bit << 12); |
| 366 | val |= ((!bit) << 4) | ((!bit) << 9); |
| 367 | pci_write_config_dword(amd_chipset.nb_dev, |
| 368 | NB_PCIE_INDX_DATA, val); |
| 369 | |
| 370 | addr = BIF_NB; |
| 371 | pci_write_config_dword(amd_chipset.nb_dev, |
| 372 | NB_PCIE_INDX_ADDR, addr); |
| 373 | pci_read_config_dword(amd_chipset.nb_dev, |
| 374 | NB_PCIE_INDX_DATA, &val); |
| 375 | val &= ~(1 << 8); |
| 376 | val |= bit << 8; |
| 377 | |
| 378 | pci_write_config_dword(amd_chipset.nb_dev, |
| 379 | NB_PCIE_INDX_DATA, val); |
| 380 | } else if (amd_chipset.nb_type == 2) { |
| 381 | addr = NB_PIF0_PWRDOWN_0; |
| 382 | pci_write_config_dword(amd_chipset.nb_dev, |
| 383 | NB_PCIE_INDX_ADDR, addr); |
| 384 | pci_read_config_dword(amd_chipset.nb_dev, |
| 385 | NB_PCIE_INDX_DATA, &val); |
| 386 | if (disable) |
| 387 | val &= ~(0x3f << 7); |
| 388 | else |
| 389 | val |= 0x3f << 7; |
| 390 | |
| 391 | pci_write_config_dword(amd_chipset.nb_dev, |
| 392 | NB_PCIE_INDX_DATA, val); |
| 393 | |
| 394 | addr = NB_PIF0_PWRDOWN_1; |
| 395 | pci_write_config_dword(amd_chipset.nb_dev, |
| 396 | NB_PCIE_INDX_ADDR, addr); |
| 397 | pci_read_config_dword(amd_chipset.nb_dev, |
| 398 | NB_PCIE_INDX_DATA, &val); |
| 399 | if (disable) |
| 400 | val &= ~(0x3f << 7); |
| 401 | else |
| 402 | val |= 0x3f << 7; |
| 403 | |
| 404 | pci_write_config_dword(amd_chipset.nb_dev, |
| 405 | NB_PCIE_INDX_DATA, val); |
| 406 | } |
| 407 | |
| 408 | spin_unlock_irqrestore(&amd_lock, flags); |
| 409 | return; |
| 410 | } |
| 411 | |
| 412 | void usb_amd_quirk_pll_disable(void) |
| 413 | { |
| 414 | usb_amd_quirk_pll(1); |
| 415 | } |
| 416 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); |
| 417 | |
| 418 | void usb_amd_quirk_pll_enable(void) |
| 419 | { |
| 420 | usb_amd_quirk_pll(0); |
| 421 | } |
| 422 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); |
| 423 | |
| 424 | void usb_amd_dev_put(void) |
| 425 | { |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 426 | struct pci_dev *nb, *smbus; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 427 | unsigned long flags; |
| 428 | |
| 429 | spin_lock_irqsave(&amd_lock, flags); |
| 430 | |
| 431 | amd_chipset.probe_count--; |
| 432 | if (amd_chipset.probe_count > 0) { |
| 433 | spin_unlock_irqrestore(&amd_lock, flags); |
| 434 | return; |
| 435 | } |
| 436 | |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 437 | /* save them to pci_dev_put outside of spinlock */ |
| 438 | nb = amd_chipset.nb_dev; |
| 439 | smbus = amd_chipset.smbus_dev; |
| 440 | |
| 441 | amd_chipset.nb_dev = NULL; |
| 442 | amd_chipset.smbus_dev = NULL; |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 443 | amd_chipset.nb_type = 0; |
Huang Rui | 22b4f0c | 2013-09-16 23:47:27 +0800 | [diff] [blame] | 444 | memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 445 | amd_chipset.isoc_reqs = 0; |
| 446 | amd_chipset.probe_result = 0; |
| 447 | |
| 448 | spin_unlock_irqrestore(&amd_lock, flags); |
Joerg Roedel | 9ab7927 | 2011-04-13 08:38:16 +0200 | [diff] [blame] | 449 | |
| 450 | if (nb) |
| 451 | pci_dev_put(nb); |
| 452 | if (smbus) |
| 453 | pci_dev_put(smbus); |
Andiry Xu | ad93562 | 2011-03-01 14:57:05 +0800 | [diff] [blame] | 454 | } |
| 455 | EXPORT_SYMBOL_GPL(usb_amd_dev_put); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 456 | |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 457 | /* |
| 458 | * Make sure the controller is completely inactive, unable to |
| 459 | * generate interrupts or do DMA. |
| 460 | */ |
| 461 | void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) |
| 462 | { |
| 463 | /* Turn off PIRQ enable and SMI enable. (This also turns off the |
| 464 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. |
| 465 | */ |
| 466 | pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); |
| 467 | |
| 468 | /* Reset the HC - this will force us to get a |
| 469 | * new notification of any already connected |
| 470 | * ports due to the virtual disconnect that it |
| 471 | * implies. |
| 472 | */ |
| 473 | outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); |
| 474 | mb(); |
| 475 | udelay(5); |
| 476 | if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) |
| 477 | dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); |
| 478 | |
| 479 | /* Just to be safe, disable interrupt requests and |
| 480 | * make sure the controller is stopped. |
| 481 | */ |
| 482 | outw(0, base + UHCI_USBINTR); |
| 483 | outw(0, base + UHCI_USBCMD); |
| 484 | } |
| 485 | EXPORT_SYMBOL_GPL(uhci_reset_hc); |
| 486 | |
| 487 | /* |
| 488 | * Initialize a controller that was newly discovered or has just been |
| 489 | * resumed. In either case we can't be sure of its previous state. |
| 490 | * |
| 491 | * Returns: 1 if the controller was reset, 0 otherwise. |
| 492 | */ |
| 493 | int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) |
| 494 | { |
| 495 | u16 legsup; |
| 496 | unsigned int cmd, intr; |
| 497 | |
| 498 | /* |
| 499 | * When restarting a suspended controller, we expect all the |
| 500 | * settings to be the same as we left them: |
| 501 | * |
| 502 | * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; |
| 503 | * Controller is stopped and configured with EGSM set; |
| 504 | * No interrupts enabled except possibly Resume Detect. |
| 505 | * |
| 506 | * If any of these conditions are violated we do a complete reset. |
| 507 | */ |
| 508 | pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); |
| 509 | if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { |
| 510 | dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", |
Harvey Harrison | 441b62c | 2008-03-03 16:08:34 -0800 | [diff] [blame] | 511 | __func__, legsup); |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 512 | goto reset_needed; |
| 513 | } |
| 514 | |
| 515 | cmd = inw(base + UHCI_USBCMD); |
| 516 | if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || |
| 517 | !(cmd & UHCI_USBCMD_EGSM)) { |
| 518 | dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", |
Harvey Harrison | 441b62c | 2008-03-03 16:08:34 -0800 | [diff] [blame] | 519 | __func__, cmd); |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 520 | goto reset_needed; |
| 521 | } |
| 522 | |
| 523 | intr = inw(base + UHCI_USBINTR); |
| 524 | if (intr & (~UHCI_USBINTR_RESUME)) { |
| 525 | dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", |
Harvey Harrison | 441b62c | 2008-03-03 16:08:34 -0800 | [diff] [blame] | 526 | __func__, intr); |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 527 | goto reset_needed; |
| 528 | } |
| 529 | return 0; |
| 530 | |
| 531 | reset_needed: |
| 532 | dev_dbg(&pdev->dev, "Performing full reset\n"); |
| 533 | uhci_reset_hc(pdev, base); |
| 534 | return 1; |
| 535 | } |
| 536 | EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); |
| 537 | |
Linus Torvalds | 541ab4a | 2005-10-31 21:12:40 -0800 | [diff] [blame] | 538 | static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) |
| 539 | { |
| 540 | u16 cmd; |
| 541 | return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); |
| 542 | } |
| 543 | |
| 544 | #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) |
| 545 | #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) |
| 546 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 547 | static void quirk_usb_handoff_uhci(struct pci_dev *pdev) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 548 | { |
| 549 | unsigned long base = 0; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 550 | int i; |
| 551 | |
Linus Torvalds | 541ab4a | 2005-10-31 21:12:40 -0800 | [diff] [blame] | 552 | if (!pio_enabled(pdev)) |
| 553 | return; |
| 554 | |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 555 | for (i = 0; i < PCI_ROM_RESOURCE; i++) |
| 556 | if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { |
| 557 | base = pci_resource_start(pdev, i); |
| 558 | break; |
| 559 | } |
| 560 | |
Alan Stern | bb200f6 | 2005-10-03 16:36:29 -0400 | [diff] [blame] | 561 | if (base) |
| 562 | uhci_check_and_reset_hc(pdev, base); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 563 | } |
| 564 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 565 | static int mmio_resource_enabled(struct pci_dev *pdev, int idx) |
Linus Torvalds | 541ab4a | 2005-10-31 21:12:40 -0800 | [diff] [blame] | 566 | { |
| 567 | return pci_resource_start(pdev, idx) && mmio_enabled(pdev); |
| 568 | } |
| 569 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 570 | static void quirk_usb_handoff_ohci(struct pci_dev *pdev) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 571 | { |
| 572 | void __iomem *base; |
Alan Stern | 3df7169 | 2010-09-10 16:37:05 -0400 | [diff] [blame] | 573 | u32 control; |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 574 | u32 fminterval; |
| 575 | int cnt; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 576 | |
Linus Torvalds | 541ab4a | 2005-10-31 21:12:40 -0800 | [diff] [blame] | 577 | if (!mmio_resource_enabled(pdev, 0)) |
| 578 | return; |
| 579 | |
Arjan van de Ven | 8e8ce4b | 2008-10-20 21:46:01 -0700 | [diff] [blame] | 580 | base = pci_ioremap_bar(pdev, 0); |
| 581 | if (base == NULL) |
| 582 | return; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 583 | |
Alan Stern | 3df7169 | 2010-09-10 16:37:05 -0400 | [diff] [blame] | 584 | control = readl(base + OHCI_CONTROL); |
| 585 | |
David Brownell | f2cb36c | 2005-09-22 22:43:30 -0700 | [diff] [blame] | 586 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ |
Alan Stern | 3df7169 | 2010-09-10 16:37:05 -0400 | [diff] [blame] | 587 | #ifdef __hppa__ |
| 588 | #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) |
| 589 | #else |
| 590 | #define OHCI_CTRL_MASK OHCI_CTRL_RWC |
| 591 | |
David Brownell | f2cb36c | 2005-09-22 22:43:30 -0700 | [diff] [blame] | 592 | if (control & OHCI_CTRL_IR) { |
Kyle McMartin | c1b45f2 | 2006-06-25 18:45:29 -0400 | [diff] [blame] | 593 | int wait_time = 500; /* arbitrary; 5 seconds */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 594 | writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); |
| 595 | writel(OHCI_OCR, base + OHCI_CMDSTATUS); |
| 596 | while (wait_time > 0 && |
| 597 | readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { |
| 598 | wait_time -= 10; |
| 599 | msleep(10); |
| 600 | } |
David Brownell | f2cb36c | 2005-09-22 22:43:30 -0700 | [diff] [blame] | 601 | if (wait_time <= 0) |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 602 | dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" |
| 603 | " (BIOS bug?) %08x\n", |
David Brownell | a38408c | 2006-02-09 16:35:31 -0500 | [diff] [blame] | 604 | readl(base + OHCI_CONTROL)); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 605 | } |
David Brownell | f2cb36c | 2005-09-22 22:43:30 -0700 | [diff] [blame] | 606 | #endif |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 607 | |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 608 | /* disable interrupts */ |
| 609 | writel((u32) ~0, base + OHCI_INTRDISABLE); |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 610 | |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 611 | /* Reset the USB bus, if the controller isn't already in RESET */ |
| 612 | if (control & OHCI_HCFS) { |
| 613 | /* Go into RESET, preserving RWC (and possibly IR) */ |
| 614 | writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); |
| 615 | readl(base + OHCI_CONTROL); |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 616 | |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 617 | /* drive bus reset for at least 50 ms (7.1.7.5) */ |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 618 | msleep(50); |
Alan Stern | 6ea12a0 | 2011-07-15 17:22:15 -0400 | [diff] [blame] | 619 | } |
Alan Stern | 3df7169 | 2010-09-10 16:37:05 -0400 | [diff] [blame] | 620 | |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 621 | /* software reset of the controller, preserving HcFmInterval */ |
| 622 | fminterval = readl(base + OHCI_FMINTERVAL); |
| 623 | writel(OHCI_HCR, base + OHCI_CMDSTATUS); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 624 | |
Alan Stern | c618759 | 2011-11-17 16:41:45 -0500 | [diff] [blame] | 625 | /* reset requires max 10 us delay */ |
| 626 | for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ |
| 627 | if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) |
| 628 | break; |
| 629 | udelay(1); |
| 630 | } |
| 631 | writel(fminterval, base + OHCI_FMINTERVAL); |
| 632 | |
| 633 | /* Now the controller is safely in SUSPEND and nothing can wake it up */ |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 634 | iounmap(base); |
| 635 | } |
| 636 | |
Bill Pemberton | 2f82686 | 2012-11-19 13:25:20 -0500 | [diff] [blame] | 637 | static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { |
Anisse Astier | 03c7536 | 2011-07-05 16:38:45 +0200 | [diff] [blame] | 638 | { |
| 639 | /* Pegatron Lucid (ExoPC) */ |
| 640 | .matches = { |
| 641 | DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), |
| 642 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), |
| 643 | }, |
| 644 | }, |
Anisse Astier | 0c42a4e | 2011-07-05 16:38:46 +0200 | [diff] [blame] | 645 | { |
| 646 | /* Pegatron Lucid (Ordissimo AIRIS) */ |
| 647 | .matches = { |
| 648 | DMI_MATCH(DMI_BOARD_NAME, "M11JB"), |
Anisse Astier | c323dc0 | 2012-10-09 12:22:36 +0200 | [diff] [blame] | 649 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), |
Anisse Astier | 0c42a4e | 2011-07-05 16:38:46 +0200 | [diff] [blame] | 650 | }, |
| 651 | }, |
Anisse Astier | 8daf8b6 | 2012-10-09 12:22:37 +0200 | [diff] [blame] | 652 | { |
| 653 | /* Pegatron Lucid (Ordissimo) */ |
| 654 | .matches = { |
| 655 | DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), |
| 656 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), |
| 657 | }, |
| 658 | }, |
Anisse Astier | 03c7536 | 2011-07-05 16:38:45 +0200 | [diff] [blame] | 659 | { } |
| 660 | }; |
| 661 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 662 | static void ehci_bios_handoff(struct pci_dev *pdev, |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 663 | void __iomem *op_reg_base, |
| 664 | u32 cap, u8 offset) |
| 665 | { |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 666 | int try_handoff = 1, tried_handoff = 0; |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 667 | |
Anisse Astier | 03c7536 | 2011-07-05 16:38:45 +0200 | [diff] [blame] | 668 | /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying |
| 669 | * the handoff on its unused controller. Skip it. */ |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 670 | if (pdev->vendor == 0x8086 && pdev->device == 0x283a) { |
Anisse Astier | 03c7536 | 2011-07-05 16:38:45 +0200 | [diff] [blame] | 671 | if (dmi_check_system(ehci_dmi_nohandoff_table)) |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 672 | try_handoff = 0; |
| 673 | } |
| 674 | |
| 675 | if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 676 | dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); |
| 677 | |
| 678 | #if 0 |
| 679 | /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, |
| 680 | * but that seems dubious in general (the BIOS left it off intentionally) |
| 681 | * and is known to prevent some systems from booting. so we won't do this |
| 682 | * unless maybe we can determine when we're on a system that needs SMI forced. |
| 683 | */ |
| 684 | /* BIOS workaround (?): be sure the pre-Linux code |
| 685 | * receives the SMI |
| 686 | */ |
| 687 | pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); |
| 688 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, |
| 689 | val | EHCI_USBLEGCTLSTS_SOOE); |
| 690 | #endif |
| 691 | |
| 692 | /* some systems get upset if this semaphore is |
| 693 | * set for any other reason than forcing a BIOS |
| 694 | * handoff.. |
| 695 | */ |
| 696 | pci_write_config_byte(pdev, offset + 3, 1); |
| 697 | } |
| 698 | |
| 699 | /* if boot firmware now owns EHCI, spin till it hands it over. */ |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 700 | if (try_handoff) { |
| 701 | int msec = 1000; |
| 702 | while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { |
| 703 | tried_handoff = 1; |
| 704 | msleep(10); |
| 705 | msec -= 10; |
| 706 | pci_read_config_dword(pdev, offset, &cap); |
| 707 | } |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 708 | } |
| 709 | |
| 710 | if (cap & EHCI_USBLEGSUP_BIOS) { |
| 711 | /* well, possibly buggy BIOS... try to shut it down, |
| 712 | * and hope nothing goes too wrong |
| 713 | */ |
Andy Ross | 3610ea5 | 2011-05-11 15:52:38 -0700 | [diff] [blame] | 714 | if (try_handoff) |
| 715 | dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" |
| 716 | " (BIOS bug?) %08x\n", cap); |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 717 | pci_write_config_byte(pdev, offset + 2, 0); |
| 718 | } |
| 719 | |
| 720 | /* just in case, always disable EHCI SMIs */ |
| 721 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); |
| 722 | |
| 723 | /* If the BIOS ever owned the controller then we can't expect |
| 724 | * any power sessions to remain intact. |
| 725 | */ |
| 726 | if (tried_handoff) |
| 727 | writel(0, op_reg_base + EHCI_CONFIGFLAG); |
| 728 | } |
| 729 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 730 | static void quirk_usb_disable_ehci(struct pci_dev *pdev) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 731 | { |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 732 | void __iomem *base, *op_reg_base; |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 733 | u32 hcc_params, cap, val; |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 734 | u8 offset, cap_length; |
Alan Stern | 97ff22e | 2011-10-27 11:20:21 -0400 | [diff] [blame] | 735 | int wait_time, count = 256/4; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 736 | |
Linus Torvalds | 541ab4a | 2005-10-31 21:12:40 -0800 | [diff] [blame] | 737 | if (!mmio_resource_enabled(pdev, 0)) |
| 738 | return; |
| 739 | |
Arjan van de Ven | 8e8ce4b | 2008-10-20 21:46:01 -0700 | [diff] [blame] | 740 | base = pci_ioremap_bar(pdev, 0); |
| 741 | if (base == NULL) |
| 742 | return; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 743 | |
| 744 | cap_length = readb(base); |
| 745 | op_reg_base = base + cap_length; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 746 | |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 747 | /* EHCI 0.96 and later may have "extended capabilities" |
| 748 | * spec section 5.1 explains the bios handoff, e.g. for |
| 749 | * booting from USB disk or using a usb keyboard |
| 750 | */ |
| 751 | hcc_params = readl(base + EHCI_HCC_PARAMS); |
| 752 | offset = (hcc_params >> 8) & 0xff; |
Roel Kluin | 6e14bda | 2009-01-31 12:37:04 +0100 | [diff] [blame] | 753 | while (offset && --count) { |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 754 | pci_read_config_dword(pdev, offset, &cap); |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 755 | |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 756 | switch (cap & 0xff) { |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 757 | case 1: |
| 758 | ehci_bios_handoff(pdev, op_reg_base, cap, offset); |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 759 | break; |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 760 | case 0: /* Illegal reserved cap, set cap=0 so we exit */ |
| 761 | cap = 0; /* then fallthrough... */ |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 762 | default: |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 763 | dev_warn(&pdev->dev, "EHCI: unrecognized capability " |
Andy Ross | 5c85301 | 2011-05-11 15:15:51 -0700 | [diff] [blame] | 764 | "%02x\n", cap & 0xff); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 765 | } |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 766 | offset = (cap >> 8) & 0xff; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 767 | } |
David Brownell | 401feaf | 2006-01-24 07:15:30 -0800 | [diff] [blame] | 768 | if (!count) |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 769 | dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 770 | |
| 771 | /* |
| 772 | * halt EHCI & disable its interrupts in any case |
| 773 | */ |
| 774 | val = readl(op_reg_base + EHCI_USBSTS); |
| 775 | if ((val & EHCI_USBSTS_HALTED) == 0) { |
| 776 | val = readl(op_reg_base + EHCI_USBCMD); |
| 777 | val &= ~EHCI_USBCMD_RUN; |
| 778 | writel(val, op_reg_base + EHCI_USBCMD); |
| 779 | |
| 780 | wait_time = 2000; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 781 | do { |
| 782 | writel(0x3f, op_reg_base + EHCI_USBSTS); |
Alan Stern | 97ff22e | 2011-10-27 11:20:21 -0400 | [diff] [blame] | 783 | udelay(100); |
| 784 | wait_time -= 100; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 785 | val = readl(op_reg_base + EHCI_USBSTS); |
| 786 | if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { |
| 787 | break; |
| 788 | } |
| 789 | } while (wait_time > 0); |
| 790 | } |
| 791 | writel(0, op_reg_base + EHCI_USBINTR); |
| 792 | writel(0x3f, op_reg_base + EHCI_USBSTS); |
| 793 | |
| 794 | iounmap(base); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 795 | } |
| 796 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 797 | /* |
| 798 | * handshake - spin reading a register until handshake completes |
| 799 | * @ptr: address of hc register to be read |
| 800 | * @mask: bits to look at in result of read |
| 801 | * @done: value of those bits when handshake succeeds |
| 802 | * @wait_usec: timeout in microseconds |
| 803 | * @delay_usec: delay in microseconds to wait between polling |
| 804 | * |
| 805 | * Polls a register every delay_usec microseconds. |
| 806 | * Returns 0 when the mask bits have the value done. |
| 807 | * Returns -ETIMEDOUT if this condition is not true after |
| 808 | * wait_usec microseconds have passed. |
| 809 | */ |
| 810 | static int handshake(void __iomem *ptr, u32 mask, u32 done, |
| 811 | int wait_usec, int delay_usec) |
| 812 | { |
| 813 | u32 result; |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 814 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 815 | do { |
| 816 | result = readl(ptr); |
| 817 | result &= mask; |
| 818 | if (result == done) |
| 819 | return 0; |
| 820 | udelay(delay_usec); |
| 821 | wait_usec -= delay_usec; |
| 822 | } while (wait_usec > 0); |
| 823 | return -ETIMEDOUT; |
| 824 | } |
| 825 | |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 826 | /* |
| 827 | * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that |
| 828 | * share some number of ports. These ports can be switched between either |
| 829 | * controller. Not all of the ports under the EHCI host controller may be |
| 830 | * switchable. |
| 831 | * |
| 832 | * The ports should be switched over to xHCI before PCI probes for any device |
| 833 | * start. This avoids active devices under EHCI being disconnected during the |
| 834 | * port switchover, which could cause loss of data on USB storage devices, or |
| 835 | * failed boot when the root file system is on a USB mass storage device and is |
| 836 | * enumerated under EHCI first. |
| 837 | * |
| 838 | * We write into the xHC's PCI configuration space in some Intel-specific |
| 839 | * registers to switch the ports over. The USB 3.0 terminations and the USB |
| 840 | * 2.0 data wires are switched separately. We want to enable the SuperSpeed |
| 841 | * terminations before switching the USB 2.0 wires over, so that USB 3.0 |
| 842 | * devices connect at SuperSpeed, rather than at USB 2.0 speeds. |
| 843 | */ |
Mathias Nyman | 26b7679 | 2013-07-23 11:35:47 +0300 | [diff] [blame] | 844 | void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 845 | { |
| 846 | u32 ports_available; |
Mathias Nyman | 26b7679 | 2013-07-23 11:35:47 +0300 | [diff] [blame] | 847 | bool ehci_found = false; |
| 848 | struct pci_dev *companion = NULL; |
| 849 | |
| 850 | /* make sure an intel EHCI controller exists */ |
| 851 | for_each_pci_dev(companion) { |
| 852 | if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && |
| 853 | companion->vendor == PCI_VENDOR_ID_INTEL) { |
| 854 | ehci_found = true; |
| 855 | break; |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | if (!ehci_found) |
| 860 | return; |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 861 | |
Sarah Sharp | 51c9e6c | 2012-04-16 10:56:47 -0700 | [diff] [blame] | 862 | /* Don't switchover the ports if the user hasn't compiled the xHCI |
| 863 | * driver. Otherwise they will see "dead" USB ports that don't power |
| 864 | * the devices. |
| 865 | */ |
| 866 | if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { |
| 867 | dev_warn(&xhci_pdev->dev, |
| 868 | "CONFIG_USB_XHCI_HCD is turned off, " |
| 869 | "defaulting to EHCI.\n"); |
| 870 | dev_warn(&xhci_pdev->dev, |
| 871 | "USB 3.0 devices will work at USB 2.0 speeds.\n"); |
David Moore | 58b2939 | 2013-01-23 22:19:49 -0800 | [diff] [blame] | 872 | usb_disable_xhci_ports(xhci_pdev); |
Sarah Sharp | 51c9e6c | 2012-04-16 10:56:47 -0700 | [diff] [blame] | 873 | return; |
| 874 | } |
| 875 | |
Keng-Yu Lin | a96874a | 2012-08-10 01:39:23 +0800 | [diff] [blame] | 876 | /* Read USB3PRM, the USB 3.0 Port Routing Mask Register |
| 877 | * Indicate the ports that can be changed from OS. |
| 878 | */ |
| 879 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, |
| 880 | &ports_available); |
| 881 | |
| 882 | dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", |
| 883 | ports_available); |
| 884 | |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 885 | /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable |
Keng-Yu Lin | a96874a | 2012-08-10 01:39:23 +0800 | [diff] [blame] | 886 | * Register, to turn on SuperSpeed terminations for the |
| 887 | * switchable ports. |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 888 | */ |
| 889 | pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, |
Xenia Ragiadakou | e459933 | 2013-09-20 19:45:53 +0300 | [diff] [blame] | 890 | ports_available); |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 891 | |
| 892 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, |
| 893 | &ports_available); |
| 894 | dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled " |
| 895 | "under xHCI: 0x%x\n", ports_available); |
| 896 | |
Keng-Yu Lin | a96874a | 2012-08-10 01:39:23 +0800 | [diff] [blame] | 897 | /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register |
| 898 | * Indicate the USB 2.0 ports to be controlled by the xHCI host. |
| 899 | */ |
| 900 | |
| 901 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, |
| 902 | &ports_available); |
| 903 | |
| 904 | dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", |
| 905 | ports_available); |
| 906 | |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 907 | /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to |
| 908 | * switch the USB 2.0 power and data lines over to the xHCI |
| 909 | * host. |
| 910 | */ |
| 911 | pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, |
Xenia Ragiadakou | e459933 | 2013-09-20 19:45:53 +0300 | [diff] [blame] | 912 | ports_available); |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 913 | |
| 914 | pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, |
| 915 | &ports_available); |
| 916 | dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over " |
| 917 | "to xHCI: 0x%x\n", ports_available); |
| 918 | } |
Mathias Nyman | 26b7679 | 2013-07-23 11:35:47 +0300 | [diff] [blame] | 919 | EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); |
Sarah Sharp | 69e848c | 2011-02-22 09:57:15 -0800 | [diff] [blame] | 920 | |
Sarah Sharp | e95829f | 2012-07-23 18:59:30 +0300 | [diff] [blame] | 921 | void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) |
| 922 | { |
| 923 | pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); |
| 924 | pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); |
| 925 | } |
| 926 | EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); |
| 927 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 928 | /** |
| 929 | * PCI Quirks for xHCI. |
| 930 | * |
| 931 | * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. |
| 932 | * It signals to the BIOS that the OS wants control of the host controller, |
| 933 | * and then waits 5 seconds for the BIOS to hand over control. |
| 934 | * If we timeout, assume the BIOS is broken and take control anyway. |
| 935 | */ |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 936 | static void quirk_usb_handoff_xhci(struct pci_dev *pdev) |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 937 | { |
| 938 | void __iomem *base; |
| 939 | int ext_cap_offset; |
| 940 | void __iomem *op_reg_base; |
| 941 | u32 val; |
| 942 | int timeout; |
Matthew Garrett | e955a1c | 2012-08-14 16:44:49 -0400 | [diff] [blame] | 943 | int len = pci_resource_len(pdev, 0); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 944 | |
| 945 | if (!mmio_resource_enabled(pdev, 0)) |
| 946 | return; |
| 947 | |
Matthew Garrett | e955a1c | 2012-08-14 16:44:49 -0400 | [diff] [blame] | 948 | base = ioremap_nocache(pci_resource_start(pdev, 0), len); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 949 | if (base == NULL) |
| 950 | return; |
| 951 | |
| 952 | /* |
| 953 | * Find the Legacy Support Capability register - |
| 954 | * this is optional for xHCI host controllers. |
| 955 | */ |
| 956 | ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET); |
| 957 | do { |
Matthew Garrett | e955a1c | 2012-08-14 16:44:49 -0400 | [diff] [blame] | 958 | if ((ext_cap_offset + sizeof(val)) > len) { |
| 959 | /* We're reading garbage from the controller */ |
| 960 | dev_warn(&pdev->dev, |
| 961 | "xHCI controller failing to respond"); |
| 962 | return; |
| 963 | } |
| 964 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 965 | if (!ext_cap_offset) |
| 966 | /* We've reached the end of the extended capabilities */ |
| 967 | goto hc_init; |
Matthew Garrett | e955a1c | 2012-08-14 16:44:49 -0400 | [diff] [blame] | 968 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 969 | val = readl(base + ext_cap_offset); |
| 970 | if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY) |
| 971 | break; |
| 972 | ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset); |
| 973 | } while (1); |
| 974 | |
| 975 | /* If the BIOS owns the HC, signal that the OS wants it, and wait */ |
| 976 | if (val & XHCI_HC_BIOS_OWNED) { |
JiSheng Zhang | 6768458 | 2011-07-16 11:04:19 +0800 | [diff] [blame] | 977 | writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 978 | |
| 979 | /* Wait for 5 seconds with 10 microsecond polling interval */ |
| 980 | timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, |
| 981 | 0, 5000, 10); |
| 982 | |
| 983 | /* Assume a buggy BIOS and take HC ownership anyway */ |
| 984 | if (timeout) { |
| 985 | dev_warn(&pdev->dev, "xHCI BIOS handoff failed" |
| 986 | " (BIOS bug ?) %08x\n", val); |
| 987 | writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); |
| 988 | } |
| 989 | } |
| 990 | |
Alex He | 95018a5 | 2012-03-30 10:21:38 +0800 | [diff] [blame] | 991 | val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); |
| 992 | /* Mask off (turn off) any enabled SMIs */ |
| 993 | val &= XHCI_LEGACY_DISABLE_SMI; |
| 994 | /* Mask all SMI events bits, RW1C */ |
| 995 | val |= XHCI_LEGACY_SMI_EVENTS; |
| 996 | /* Disable any BIOS SMIs and clear all SMI events*/ |
| 997 | writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 998 | |
Manoj Iyer | 29d2145 | 2012-08-22 11:53:18 -0500 | [diff] [blame] | 999 | hc_init: |
Mathias Nyman | 26b7679 | 2013-07-23 11:35:47 +0300 | [diff] [blame] | 1000 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) |
| 1001 | usb_enable_intel_xhci_ports(pdev); |
Manoj Iyer | 29d2145 | 2012-08-22 11:53:18 -0500 | [diff] [blame] | 1002 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1003 | op_reg_base = base + XHCI_HC_LENGTH(readl(base)); |
| 1004 | |
| 1005 | /* Wait for the host controller to be ready before writing any |
| 1006 | * operational or runtime registers. Wait 5 seconds and no more. |
| 1007 | */ |
| 1008 | timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, |
| 1009 | 5000, 10); |
| 1010 | /* Assume a buggy HC and start HC initialization anyway */ |
| 1011 | if (timeout) { |
| 1012 | val = readl(op_reg_base + XHCI_STS_OFFSET); |
| 1013 | dev_warn(&pdev->dev, |
| 1014 | "xHCI HW not ready after 5 sec (HC bug?) " |
| 1015 | "status = 0x%x\n", val); |
| 1016 | } |
| 1017 | |
| 1018 | /* Send the halt and disable interrupts command */ |
| 1019 | val = readl(op_reg_base + XHCI_CMD_OFFSET); |
| 1020 | val &= ~(XHCI_CMD_RUN | XHCI_IRQS); |
| 1021 | writel(val, op_reg_base + XHCI_CMD_OFFSET); |
| 1022 | |
| 1023 | /* Wait for the HC to halt - poll every 125 usec (one microframe). */ |
| 1024 | timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, |
| 1025 | XHCI_MAX_HALT_USEC, 125); |
| 1026 | if (timeout) { |
| 1027 | val = readl(op_reg_base + XHCI_STS_OFFSET); |
| 1028 | dev_warn(&pdev->dev, |
| 1029 | "xHCI HW did not halt within %d usec " |
| 1030 | "status = 0x%x\n", XHCI_MAX_HALT_USEC, val); |
| 1031 | } |
| 1032 | |
| 1033 | iounmap(base); |
| 1034 | } |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1035 | |
Bill Pemberton | 41ac7b3 | 2012-11-19 13:21:48 -0500 | [diff] [blame] | 1036 | static void quirk_usb_early_handoff(struct pci_dev *pdev) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1037 | { |
Jayachandran C | e4436a7 | 2012-01-27 20:27:32 +0530 | [diff] [blame] | 1038 | /* Skip Netlogic mips SoC's internal PCI USB controller. |
| 1039 | * This device does not need/support EHCI/OHCI handoff |
| 1040 | */ |
| 1041 | if (pdev->vendor == 0x184e) /* vendor Netlogic */ |
| 1042 | return; |
Sarah Sharp | cab928e | 2012-02-07 15:11:46 -0800 | [diff] [blame] | 1043 | if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && |
| 1044 | pdev->class != PCI_CLASS_SERIAL_USB_OHCI && |
| 1045 | pdev->class != PCI_CLASS_SERIAL_USB_EHCI && |
| 1046 | pdev->class != PCI_CLASS_SERIAL_USB_XHCI) |
| 1047 | return; |
Jayachandran C | e4436a7 | 2012-01-27 20:27:32 +0530 | [diff] [blame] | 1048 | |
Sarah Sharp | cab928e | 2012-02-07 15:11:46 -0800 | [diff] [blame] | 1049 | if (pci_enable_device(pdev) < 0) { |
| 1050 | dev_warn(&pdev->dev, "Can't enable PCI device, " |
| 1051 | "BIOS handoff failed.\n"); |
| 1052 | return; |
| 1053 | } |
Alan Stern | 478a3ba | 2005-10-19 12:52:02 -0400 | [diff] [blame] | 1054 | if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1055 | quirk_usb_handoff_uhci(pdev); |
Alan Stern | 478a3ba | 2005-10-19 12:52:02 -0400 | [diff] [blame] | 1056 | else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1057 | quirk_usb_handoff_ohci(pdev); |
Alan Stern | 478a3ba | 2005-10-19 12:52:02 -0400 | [diff] [blame] | 1058 | else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1059 | quirk_usb_disable_ehci(pdev); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1060 | else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) |
| 1061 | quirk_usb_handoff_xhci(pdev); |
Sarah Sharp | cab928e | 2012-02-07 15:11:46 -0800 | [diff] [blame] | 1062 | pci_disable_device(pdev); |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 1063 | } |
Yinghai Lu | 8474ecd | 2012-02-23 23:46:59 -0800 | [diff] [blame] | 1064 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
| 1065 | PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); |