Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 24 | /** |
| 25 | * DOC: Frame Buffer Compression (FBC) |
| 26 | * |
| 27 | * FBC tries to save memory bandwidth (and so power consumption) by |
| 28 | * compressing the amount of memory used by the display. It is total |
| 29 | * transparent to user space and completely handled in the kernel. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 30 | * |
| 31 | * The benefits of FBC are mostly visible with solid backgrounds and |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 32 | * variation-less patterns. It comes from keeping the memory footprint small |
| 33 | * and having fewer memory pages opened and accessed for refreshing the display. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 34 | * |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
| 36 | * offset on proper registers. The hardware takes care of all |
| 37 | * compress/decompress. However there are many known cases where we have to |
| 38 | * forcibly disable it to allow proper screen updates. |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 39 | */ |
| 40 | |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 41 | #include "intel_drv.h" |
| 42 | #include "i915_drv.h" |
| 43 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 44 | static void i8xx_fbc_disable(struct drm_device *dev) |
| 45 | { |
| 46 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 47 | u32 fbc_ctl; |
| 48 | |
| 49 | dev_priv->fbc.enabled = false; |
| 50 | |
| 51 | /* Disable compression */ |
| 52 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 53 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 54 | return; |
| 55 | |
| 56 | fbc_ctl &= ~FBC_CTL_EN; |
| 57 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 58 | |
| 59 | /* Wait for compressing bit to clear */ |
| 60 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 61 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 62 | return; |
| 63 | } |
| 64 | |
| 65 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 66 | } |
| 67 | |
| 68 | static void i8xx_fbc_enable(struct drm_crtc *crtc) |
| 69 | { |
| 70 | struct drm_device *dev = crtc->dev; |
| 71 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 72 | struct drm_framebuffer *fb = crtc->primary->fb; |
| 73 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 74 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 75 | int cfb_pitch; |
| 76 | int i; |
| 77 | u32 fbc_ctl; |
| 78 | |
| 79 | dev_priv->fbc.enabled = true; |
| 80 | |
Jani Nikula | 60ee5cd | 2015-02-05 12:04:27 +0200 | [diff] [blame] | 81 | /* Note: fbc.threshold == 1 for i8xx */ |
| 82 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 83 | if (fb->pitches[0] < cfb_pitch) |
| 84 | cfb_pitch = fb->pitches[0]; |
| 85 | |
| 86 | /* FBC_CTL wants 32B or 64B units */ |
| 87 | if (IS_GEN2(dev)) |
| 88 | cfb_pitch = (cfb_pitch / 32) - 1; |
| 89 | else |
| 90 | cfb_pitch = (cfb_pitch / 64) - 1; |
| 91 | |
| 92 | /* Clear old tags */ |
| 93 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 94 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 95 | |
| 96 | if (IS_GEN4(dev)) { |
| 97 | u32 fbc_ctl2; |
| 98 | |
| 99 | /* Set it up... */ |
| 100 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
| 101 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
| 102 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 103 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 104 | } |
| 105 | |
| 106 | /* enable it... */ |
| 107 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 108 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; |
| 109 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; |
| 110 | if (IS_I945GM(dev)) |
| 111 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 112 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 113 | fbc_ctl |= obj->fence_reg; |
| 114 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 115 | |
| 116 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
| 117 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
| 118 | } |
| 119 | |
| 120 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
| 121 | { |
| 122 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 123 | |
| 124 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 125 | } |
| 126 | |
| 127 | static void g4x_fbc_enable(struct drm_crtc *crtc) |
| 128 | { |
| 129 | struct drm_device *dev = crtc->dev; |
| 130 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 131 | struct drm_framebuffer *fb = crtc->primary->fb; |
| 132 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 134 | u32 dpfc_ctl; |
| 135 | |
| 136 | dev_priv->fbc.enabled = true; |
| 137 | |
| 138 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
| 139 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 140 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 141 | else |
| 142 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 143 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
| 144 | |
| 145 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 146 | |
| 147 | /* enable it... */ |
| 148 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 149 | |
| 150 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
| 151 | } |
| 152 | |
| 153 | static void g4x_fbc_disable(struct drm_device *dev) |
| 154 | { |
| 155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 156 | u32 dpfc_ctl; |
| 157 | |
| 158 | dev_priv->fbc.enabled = false; |
| 159 | |
| 160 | /* Disable compression */ |
| 161 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 162 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 163 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 165 | |
| 166 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | static bool g4x_fbc_enabled(struct drm_device *dev) |
| 171 | { |
| 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 173 | |
| 174 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 175 | } |
| 176 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 177 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 178 | { |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 179 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
| 180 | POSTING_READ(MSG_FBC_REND_STATE); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void ilk_fbc_enable(struct drm_crtc *crtc) |
| 184 | { |
| 185 | struct drm_device *dev = crtc->dev; |
| 186 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 187 | struct drm_framebuffer *fb = crtc->primary->fb; |
| 188 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 190 | u32 dpfc_ctl; |
| 191 | |
| 192 | dev_priv->fbc.enabled = true; |
| 193 | |
| 194 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
| 195 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 196 | dev_priv->fbc.threshold++; |
| 197 | |
| 198 | switch (dev_priv->fbc.threshold) { |
| 199 | case 4: |
| 200 | case 3: |
| 201 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 202 | break; |
| 203 | case 2: |
| 204 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 205 | break; |
| 206 | case 1: |
| 207 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 208 | break; |
| 209 | } |
| 210 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
| 211 | if (IS_GEN5(dev)) |
| 212 | dpfc_ctl |= obj->fence_reg; |
| 213 | |
| 214 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
| 215 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
| 216 | /* enable it... */ |
| 217 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 218 | |
| 219 | if (IS_GEN6(dev)) { |
| 220 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 221 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 222 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 223 | } |
| 224 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 225 | intel_fbc_nuke(dev_priv); |
| 226 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 227 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
| 228 | } |
| 229 | |
| 230 | static void ilk_fbc_disable(struct drm_device *dev) |
| 231 | { |
| 232 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 233 | u32 dpfc_ctl; |
| 234 | |
| 235 | dev_priv->fbc.enabled = false; |
| 236 | |
| 237 | /* Disable compression */ |
| 238 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 239 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 240 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 241 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 242 | |
| 243 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | static bool ilk_fbc_enabled(struct drm_device *dev) |
| 248 | { |
| 249 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 250 | |
| 251 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 252 | } |
| 253 | |
| 254 | static void gen7_fbc_enable(struct drm_crtc *crtc) |
| 255 | { |
| 256 | struct drm_device *dev = crtc->dev; |
| 257 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 258 | struct drm_framebuffer *fb = crtc->primary->fb; |
| 259 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 261 | u32 dpfc_ctl; |
| 262 | |
| 263 | dev_priv->fbc.enabled = true; |
| 264 | |
Paulo Zanoni | d8514d6 | 2015-06-12 14:36:21 -0300 | [diff] [blame] | 265 | dpfc_ctl = 0; |
| 266 | if (IS_IVYBRIDGE(dev)) |
| 267 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
| 268 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 269 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 270 | dev_priv->fbc.threshold++; |
| 271 | |
| 272 | switch (dev_priv->fbc.threshold) { |
| 273 | case 4: |
| 274 | case 3: |
| 275 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 276 | break; |
| 277 | case 2: |
| 278 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 279 | break; |
| 280 | case 1: |
| 281 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 282 | break; |
| 283 | } |
| 284 | |
| 285 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
| 286 | |
| 287 | if (dev_priv->fbc.false_color) |
| 288 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; |
| 289 | |
| 290 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 291 | |
| 292 | if (IS_IVYBRIDGE(dev)) { |
| 293 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
| 294 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 295 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 296 | ILK_FBCQ_DIS); |
| 297 | } else { |
| 298 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
| 299 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
| 300 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | |
| 301 | HSW_FBCQ_DIS); |
| 302 | } |
| 303 | |
| 304 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 305 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 306 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 307 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 308 | intel_fbc_nuke(dev_priv); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 309 | |
| 310 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
| 311 | } |
| 312 | |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 313 | /** |
| 314 | * intel_fbc_enabled - Is FBC enabled? |
| 315 | * @dev: the drm_device |
| 316 | * |
| 317 | * This function is used to verify the current state of FBC. |
| 318 | * FIXME: This should be tracked in the plane config eventually |
| 319 | * instead of queried at runtime for most callers. |
| 320 | */ |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 321 | bool intel_fbc_enabled(struct drm_device *dev) |
| 322 | { |
| 323 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 324 | |
| 325 | return dev_priv->fbc.enabled; |
| 326 | } |
| 327 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 328 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 329 | { |
| 330 | struct intel_fbc_work *work = |
| 331 | container_of(to_delayed_work(__work), |
| 332 | struct intel_fbc_work, work); |
| 333 | struct drm_device *dev = work->crtc->dev; |
| 334 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 335 | |
| 336 | mutex_lock(&dev->struct_mutex); |
| 337 | if (work == dev_priv->fbc.fbc_work) { |
| 338 | /* Double check that we haven't switched fb without cancelling |
| 339 | * the prior work. |
| 340 | */ |
| 341 | if (work->crtc->primary->fb == work->fb) { |
| 342 | dev_priv->display.enable_fbc(work->crtc); |
| 343 | |
Paulo Zanoni | e35fef2 | 2015-02-09 14:46:29 -0200 | [diff] [blame] | 344 | dev_priv->fbc.crtc = to_intel_crtc(work->crtc); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 345 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
| 346 | dev_priv->fbc.y = work->crtc->y; |
| 347 | } |
| 348 | |
| 349 | dev_priv->fbc.fbc_work = NULL; |
| 350 | } |
| 351 | mutex_unlock(&dev->struct_mutex); |
| 352 | |
| 353 | kfree(work); |
| 354 | } |
| 355 | |
| 356 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) |
| 357 | { |
| 358 | if (dev_priv->fbc.fbc_work == NULL) |
| 359 | return; |
| 360 | |
| 361 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 362 | |
| 363 | /* Synchronisation is provided by struct_mutex and checking of |
| 364 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
| 365 | * entirely asynchronously. |
| 366 | */ |
| 367 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
| 368 | /* tasklet was killed before being run, clean up */ |
| 369 | kfree(dev_priv->fbc.fbc_work); |
| 370 | |
| 371 | /* Mark the work as no longer wanted so that if it does |
| 372 | * wake-up (because the work was already running and waiting |
| 373 | * for our mutex), it will discover that is no longer |
| 374 | * necessary to run. |
| 375 | */ |
| 376 | dev_priv->fbc.fbc_work = NULL; |
| 377 | } |
| 378 | |
| 379 | static void intel_fbc_enable(struct drm_crtc *crtc) |
| 380 | { |
| 381 | struct intel_fbc_work *work; |
| 382 | struct drm_device *dev = crtc->dev; |
| 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 384 | |
| 385 | if (!dev_priv->display.enable_fbc) |
| 386 | return; |
| 387 | |
| 388 | intel_fbc_cancel_work(dev_priv); |
| 389 | |
| 390 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
| 391 | if (work == NULL) { |
| 392 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
| 393 | dev_priv->display.enable_fbc(crtc); |
| 394 | return; |
| 395 | } |
| 396 | |
| 397 | work->crtc = crtc; |
| 398 | work->fb = crtc->primary->fb; |
| 399 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 400 | |
| 401 | dev_priv->fbc.fbc_work = work; |
| 402 | |
| 403 | /* Delay the actual enabling to let pageflipping cease and the |
| 404 | * display to settle before starting the compression. Note that |
| 405 | * this delay also serves a second purpose: it allows for a |
| 406 | * vblank to pass after disabling the FBC before we attempt |
| 407 | * to modify the control registers. |
| 408 | * |
| 409 | * A more complicated solution would involve tracking vblanks |
| 410 | * following the termination of the page-flipping sequence |
| 411 | * and indeed performing the enable as a co-routine and not |
| 412 | * waiting synchronously upon the vblank. |
| 413 | * |
| 414 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
| 415 | */ |
| 416 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
| 417 | } |
| 418 | |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 419 | /** |
| 420 | * intel_fbc_disable - disable FBC |
| 421 | * @dev: the drm_device |
| 422 | * |
| 423 | * This function disables FBC. |
| 424 | */ |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 425 | void intel_fbc_disable(struct drm_device *dev) |
| 426 | { |
| 427 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 428 | |
| 429 | intel_fbc_cancel_work(dev_priv); |
| 430 | |
| 431 | if (!dev_priv->display.disable_fbc) |
| 432 | return; |
| 433 | |
| 434 | dev_priv->display.disable_fbc(dev); |
Paulo Zanoni | e35fef2 | 2015-02-09 14:46:29 -0200 | [diff] [blame] | 435 | dev_priv->fbc.crtc = NULL; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 436 | } |
| 437 | |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 438 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
| 439 | { |
| 440 | switch (reason) { |
| 441 | case FBC_OK: |
| 442 | return "FBC enabled but currently disabled in hardware"; |
| 443 | case FBC_UNSUPPORTED: |
| 444 | return "unsupported by this chipset"; |
| 445 | case FBC_NO_OUTPUT: |
| 446 | return "no output"; |
| 447 | case FBC_STOLEN_TOO_SMALL: |
| 448 | return "not enough stolen memory"; |
| 449 | case FBC_UNSUPPORTED_MODE: |
| 450 | return "mode incompatible with compression"; |
| 451 | case FBC_MODE_TOO_LARGE: |
| 452 | return "mode too large for compression"; |
| 453 | case FBC_BAD_PLANE: |
| 454 | return "FBC unsupported on plane"; |
| 455 | case FBC_NOT_TILED: |
| 456 | return "framebuffer not tiled or fenced"; |
| 457 | case FBC_MULTIPLE_PIPES: |
| 458 | return "more than one pipe active"; |
| 459 | case FBC_MODULE_PARAM: |
| 460 | return "disabled per module param"; |
| 461 | case FBC_CHIP_DEFAULT: |
| 462 | return "disabled per chip default"; |
| 463 | case FBC_ROTATION: |
| 464 | return "rotation unsupported"; |
| 465 | default: |
| 466 | MISSING_CASE(reason); |
| 467 | return "unknown reason"; |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 472 | enum no_fbc_reason reason) |
| 473 | { |
| 474 | if (dev_priv->fbc.no_fbc_reason == reason) |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 475 | return; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 476 | |
| 477 | dev_priv->fbc.no_fbc_reason = reason; |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 478 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 479 | } |
| 480 | |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 481 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
| 482 | { |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 483 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
Paulo Zanoni | 68b9214 | 2015-02-13 17:23:42 -0200 | [diff] [blame] | 484 | enum pipe pipe; |
Paulo Zanoni | e489e38 | 2015-02-13 17:23:43 -0200 | [diff] [blame] | 485 | bool pipe_a_only = false, one_pipe_only = false; |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 486 | |
Paulo Zanoni | 68b9214 | 2015-02-13 17:23:42 -0200 | [diff] [blame] | 487 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
| 488 | pipe_a_only = true; |
Paulo Zanoni | e489e38 | 2015-02-13 17:23:43 -0200 | [diff] [blame] | 489 | else if (INTEL_INFO(dev_priv)->gen <= 4) |
| 490 | one_pipe_only = true; |
Paulo Zanoni | 68b9214 | 2015-02-13 17:23:42 -0200 | [diff] [blame] | 491 | |
| 492 | for_each_pipe(dev_priv, pipe) { |
| 493 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 494 | |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 495 | if (intel_crtc_active(tmp_crtc) && |
Maarten Lankhorst | b70709a | 2015-04-21 17:12:53 +0300 | [diff] [blame] | 496 | to_intel_plane_state(tmp_crtc->primary->state)->visible) { |
Paulo Zanoni | e489e38 | 2015-02-13 17:23:43 -0200 | [diff] [blame] | 497 | if (one_pipe_only && crtc) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 498 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 499 | return NULL; |
| 500 | } |
| 501 | crtc = tmp_crtc; |
| 502 | } |
Paulo Zanoni | 68b9214 | 2015-02-13 17:23:42 -0200 | [diff] [blame] | 503 | |
| 504 | if (pipe_a_only) |
| 505 | break; |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | if (!crtc || crtc->primary->fb == NULL) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 509 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 510 | return NULL; |
| 511 | } |
| 512 | |
| 513 | return crtc; |
| 514 | } |
| 515 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 516 | /** |
| 517 | * intel_fbc_update - enable/disable FBC as needed |
| 518 | * @dev: the drm_device |
| 519 | * |
| 520 | * Set up the framebuffer compression hardware at mode set time. We |
| 521 | * enable it if possible: |
| 522 | * - plane A only (on pre-965) |
| 523 | * - no pixel mulitply/line duplication |
| 524 | * - no alpha buffer discard |
| 525 | * - no dual wide |
| 526 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
| 527 | * |
| 528 | * We can't assume that any compression will take place (worst case), |
| 529 | * so the compressed buffer has to be the same size as the uncompressed |
| 530 | * one. It also must reside (along with the line length buffer) in |
| 531 | * stolen memory. |
| 532 | * |
| 533 | * We need to enable/disable FBC on a global basis. |
| 534 | */ |
| 535 | void intel_fbc_update(struct drm_device *dev) |
| 536 | { |
| 537 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 538 | struct drm_crtc *crtc = NULL; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 539 | struct intel_crtc *intel_crtc; |
| 540 | struct drm_framebuffer *fb; |
| 541 | struct drm_i915_gem_object *obj; |
| 542 | const struct drm_display_mode *adjusted_mode; |
| 543 | unsigned int max_width, max_height; |
| 544 | |
Paulo Zanoni | 104618b | 2015-02-09 14:46:28 -0200 | [diff] [blame] | 545 | if (!HAS_FBC(dev)) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 546 | return; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 547 | |
Yu Zhang | bd49234 | 2015-02-10 19:05:50 +0800 | [diff] [blame] | 548 | /* disable framebuffer compression in vGPU */ |
| 549 | if (intel_vgpu_active(dev)) |
| 550 | i915.enable_fbc = 0; |
| 551 | |
Paulo Zanoni | 7cc6574 | 2015-02-09 14:46:27 -0200 | [diff] [blame] | 552 | if (i915.enable_fbc < 0) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 553 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
Paulo Zanoni | 7cc6574 | 2015-02-09 14:46:27 -0200 | [diff] [blame] | 554 | goto out_disable; |
| 555 | } |
| 556 | |
Rodrigo Vivi | ab585de | 2015-03-24 12:40:09 -0700 | [diff] [blame] | 557 | if (!i915.enable_fbc) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 558 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
Paulo Zanoni | 7cc6574 | 2015-02-09 14:46:27 -0200 | [diff] [blame] | 559 | goto out_disable; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | /* |
| 563 | * If FBC is already on, we just have to verify that we can |
| 564 | * keep it that way... |
| 565 | * Need to disable if: |
| 566 | * - more than one pipe is active |
| 567 | * - changing FBC params (stride, fence, mode) |
| 568 | * - new fb is too large to fit in compressed buffer |
| 569 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 570 | */ |
Paulo Zanoni | 9510675 | 2015-02-13 17:23:41 -0200 | [diff] [blame] | 571 | crtc = intel_fbc_find_crtc(dev_priv); |
| 572 | if (!crtc) |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 573 | goto out_disable; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 574 | |
| 575 | intel_crtc = to_intel_crtc(crtc); |
| 576 | fb = crtc->primary->fb; |
| 577 | obj = intel_fb_obj(fb); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 578 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 579 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 580 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 581 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 582 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 583 | goto out_disable; |
| 584 | } |
| 585 | |
| 586 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { |
| 587 | max_width = 4096; |
| 588 | max_height = 4096; |
| 589 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
| 590 | max_width = 4096; |
| 591 | max_height = 2048; |
| 592 | } else { |
| 593 | max_width = 2048; |
| 594 | max_height = 1536; |
| 595 | } |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 596 | if (intel_crtc->config->pipe_src_w > max_width || |
| 597 | intel_crtc->config->pipe_src_h > max_height) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 598 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 599 | goto out_disable; |
| 600 | } |
| 601 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
| 602 | intel_crtc->plane != PLANE_A) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 603 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 604 | goto out_disable; |
| 605 | } |
| 606 | |
| 607 | /* The use of a CPU fence is mandatory in order to detect writes |
| 608 | * by the CPU to the scanout and trigger updates to the FBC. |
| 609 | */ |
| 610 | if (obj->tiling_mode != I915_TILING_X || |
| 611 | obj->fence_reg == I915_FENCE_REG_NONE) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 612 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 613 | goto out_disable; |
| 614 | } |
| 615 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 616 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 617 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 618 | goto out_disable; |
| 619 | } |
| 620 | |
| 621 | /* If the kernel debugger is active, always disable compression */ |
| 622 | if (in_dbg_master()) |
| 623 | goto out_disable; |
| 624 | |
| 625 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, |
| 626 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 627 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 628 | goto out_disable; |
| 629 | } |
| 630 | |
| 631 | /* If the scanout has not changed, don't modify the FBC settings. |
| 632 | * Note that we make the fundamental assumption that the fb->obj |
| 633 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 634 | * without first being decoupled from the scanout and FBC disabled. |
| 635 | */ |
Paulo Zanoni | e35fef2 | 2015-02-09 14:46:29 -0200 | [diff] [blame] | 636 | if (dev_priv->fbc.crtc == intel_crtc && |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 637 | dev_priv->fbc.fb_id == fb->base.id && |
| 638 | dev_priv->fbc.y == crtc->y) |
| 639 | return; |
| 640 | |
| 641 | if (intel_fbc_enabled(dev)) { |
| 642 | /* We update FBC along two paths, after changing fb/crtc |
| 643 | * configuration (modeswitching) and after page-flipping |
| 644 | * finishes. For the latter, we know that not only did |
| 645 | * we disable the FBC at the start of the page-flip |
| 646 | * sequence, but also more than one vblank has passed. |
| 647 | * |
| 648 | * For the former case of modeswitching, it is possible |
| 649 | * to switch between two FBC valid configurations |
| 650 | * instantaneously so we do need to disable the FBC |
| 651 | * before we can modify its control registers. We also |
| 652 | * have to wait for the next vblank for that to take |
| 653 | * effect. However, since we delay enabling FBC we can |
| 654 | * assume that a vblank has passed since disabling and |
| 655 | * that we can safely alter the registers in the deferred |
| 656 | * callback. |
| 657 | * |
| 658 | * In the scenario that we go from a valid to invalid |
| 659 | * and then back to valid FBC configuration we have |
| 660 | * no strict enforcement that a vblank occurred since |
| 661 | * disabling the FBC. However, along all current pipe |
| 662 | * disabling paths we do need to wait for a vblank at |
| 663 | * some point. And we wait before enabling FBC anyway. |
| 664 | */ |
| 665 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 666 | intel_fbc_disable(dev); |
| 667 | } |
| 668 | |
| 669 | intel_fbc_enable(crtc); |
| 670 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
| 671 | return; |
| 672 | |
| 673 | out_disable: |
| 674 | /* Multiple disables should be harmless */ |
| 675 | if (intel_fbc_enabled(dev)) { |
| 676 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
| 677 | intel_fbc_disable(dev); |
| 678 | } |
| 679 | i915_gem_stolen_cleanup_compression(dev); |
| 680 | } |
| 681 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 682 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
| 683 | unsigned int frontbuffer_bits, |
| 684 | enum fb_op_origin origin) |
| 685 | { |
| 686 | struct drm_device *dev = dev_priv->dev; |
| 687 | unsigned int fbc_bits; |
| 688 | |
| 689 | if (origin == ORIGIN_GTT) |
| 690 | return; |
| 691 | |
| 692 | if (dev_priv->fbc.enabled) |
| 693 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
| 694 | else if (dev_priv->fbc.fbc_work) |
| 695 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( |
| 696 | to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe); |
| 697 | else |
| 698 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; |
| 699 | |
| 700 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); |
| 701 | |
| 702 | if (dev_priv->fbc.busy_bits) |
| 703 | intel_fbc_disable(dev); |
| 704 | } |
| 705 | |
| 706 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
| 707 | unsigned int frontbuffer_bits) |
| 708 | { |
| 709 | struct drm_device *dev = dev_priv->dev; |
| 710 | |
| 711 | if (!dev_priv->fbc.busy_bits) |
| 712 | return; |
| 713 | |
| 714 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; |
| 715 | |
| 716 | if (!dev_priv->fbc.busy_bits) |
| 717 | intel_fbc_update(dev); |
| 718 | } |
| 719 | |
Rodrigo Vivi | 94b83957 | 2014-12-08 06:46:31 -0800 | [diff] [blame] | 720 | /** |
| 721 | * intel_fbc_init - Initialize FBC |
| 722 | * @dev_priv: the i915 device |
| 723 | * |
| 724 | * This function might be called during PM init process. |
| 725 | */ |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 726 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
| 727 | { |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 728 | enum pipe pipe; |
| 729 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 730 | if (!HAS_FBC(dev_priv)) { |
| 731 | dev_priv->fbc.enabled = false; |
Paulo Zanoni | 104618b | 2015-02-09 14:46:28 -0200 | [diff] [blame] | 732 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 733 | return; |
| 734 | } |
| 735 | |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 736 | for_each_pipe(dev_priv, pipe) { |
| 737 | dev_priv->fbc.possible_framebuffer_bits |= |
| 738 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
| 739 | |
| 740 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
| 741 | break; |
| 742 | } |
| 743 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 744 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
| 745 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; |
| 746 | dev_priv->display.enable_fbc = gen7_fbc_enable; |
| 747 | dev_priv->display.disable_fbc = ilk_fbc_disable; |
| 748 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
| 749 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; |
| 750 | dev_priv->display.enable_fbc = ilk_fbc_enable; |
| 751 | dev_priv->display.disable_fbc = ilk_fbc_disable; |
| 752 | } else if (IS_GM45(dev_priv)) { |
| 753 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 754 | dev_priv->display.enable_fbc = g4x_fbc_enable; |
| 755 | dev_priv->display.disable_fbc = g4x_fbc_disable; |
| 756 | } else { |
| 757 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 758 | dev_priv->display.enable_fbc = i8xx_fbc_enable; |
| 759 | dev_priv->display.disable_fbc = i8xx_fbc_disable; |
| 760 | |
| 761 | /* This value was pulled out of someone's hat */ |
| 762 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
| 763 | } |
| 764 | |
| 765 | dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); |
| 766 | } |