Pratap Nirujogi | 1e3bf30 | 2018-03-06 12:37:53 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | &soc { |
| 15 | qcom,msm-cam@1b00000 { |
| 16 | compatible = "qcom,msm-cam"; |
| 17 | reg = <0x1b00000 0x40000>; |
| 18 | reg-names = "msm-cam"; |
| 19 | status = "ok"; |
| 20 | bus-vectors = "suspend", "svs", "nominal", "turbo"; |
| 21 | qcom,bus-votes = <0 160000000 320000000 320000000>; |
| 22 | }; |
| 23 | |
| 24 | qcom,csiphy@1b34000 { |
| 25 | status = "ok"; |
| 26 | cell-index = <0>; |
Mounika Reddy Tangirala | e55561b | 2018-12-12 15:55:55 +0530 | [diff] [blame] | 27 | compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; |
Pratap Nirujogi | 1e3bf30 | 2018-03-06 12:37:53 +0530 | [diff] [blame] | 28 | reg = <0x1b34000 0x1000>, |
| 29 | <0x1b00030 0x4>; |
| 30 | reg-names = "csiphy", "csiphy_clk_mux"; |
| 31 | interrupts = <0 78 0>; |
| 32 | interrupt-names = "csiphy"; |
| 33 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 34 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 35 | <&clock_gcc clk_csi0phytimer_clk_src>, |
| 36 | <&clock_gcc clk_gcc_camss_csi0phytimer_clk>, |
| 37 | <&clock_gcc clk_camss_top_ahb_clk_src>, |
| 38 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 39 | clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", |
| 40 | "csiphy_timer_src_clk", "csiphy_timer_clk", |
| 41 | "camss_ahb_src", "camss_ahb_clk"; |
| 42 | qcom,clock-rates = <0 61540000 200000000 0 0 0>; |
| 43 | }; |
| 44 | |
| 45 | qcom,csiphy@1b35000 { |
| 46 | status = "ok"; |
| 47 | cell-index = <1>; |
Mounika Reddy Tangirala | e55561b | 2018-12-12 15:55:55 +0530 | [diff] [blame] | 48 | compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; |
Pratap Nirujogi | 1e3bf30 | 2018-03-06 12:37:53 +0530 | [diff] [blame] | 49 | reg = <0x1b35000 0x1000>, |
| 50 | <0x1b00038 0x4>; |
| 51 | reg-names = "csiphy", "csiphy_clk_mux"; |
| 52 | interrupts = <0 79 0>; |
| 53 | interrupt-names = "csiphy"; |
| 54 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 55 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 56 | <&clock_gcc clk_csi1phytimer_clk_src>, |
| 57 | <&clock_gcc clk_gcc_camss_csi1phytimer_clk>, |
| 58 | <&clock_gcc clk_camss_top_ahb_clk_src>, |
| 59 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 60 | clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", |
| 61 | "csiphy_timer_src_clk", "csiphy_timer_clk", |
| 62 | "camss_ahb_src", "camss_ahb_clk"; |
| 63 | qcom,clock-rates = <0 61540000 200000000 0 0 0>; |
| 64 | }; |
| 65 | |
| 66 | qcom,csid@1b30000 { |
| 67 | status = "ok"; |
| 68 | cell-index = <0>; |
| 69 | compatible = "qcom,csid-v3.4.2", "qcom,csid"; |
| 70 | reg = <0x1b30000 0x400>; |
| 71 | reg-names = "csid"; |
| 72 | interrupts = <0 51 0>; |
| 73 | interrupt-names = "csid"; |
| 74 | qcom,csi-vdd-voltage = <1200000>; |
| 75 | qcom,mipi-csi-vdd-supply = <&pm8937_l2>; |
| 76 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 77 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 78 | <&clock_gcc clk_gcc_camss_csi0_ahb_clk>, |
| 79 | <&clock_gcc clk_csi0_clk_src>, |
| 80 | <&clock_gcc clk_gcc_camss_csi0phy_clk>, |
| 81 | <&clock_gcc clk_gcc_camss_csi0_clk>, |
| 82 | <&clock_gcc clk_gcc_camss_csi0pix_clk>, |
| 83 | <&clock_gcc clk_gcc_camss_csi0rdi_clk>, |
| 84 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 85 | clock-names = "camss_top_ahb_clk", |
| 86 | "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", |
| 87 | "csi0_phy_clk", |
| 88 | "csi_clk", "csi_pix_clk", |
| 89 | "csi_rdi_clk", "camss_ahb_clk"; |
| 90 | qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; |
| 91 | }; |
| 92 | |
| 93 | qcom,csid@1b30400 { |
| 94 | status = "ok"; |
| 95 | cell-index = <1>; |
| 96 | compatible = "qcom,csid-v3.4.2", "qcom,csid"; |
| 97 | reg = <0x1b30400 0x400>; |
| 98 | reg-names = "csid"; |
| 99 | interrupts = <0 52 0>; |
| 100 | interrupt-names = "csid"; |
| 101 | qcom,csi-vdd-voltage = <1200000>; |
| 102 | qcom,mipi-csi-vdd-supply = <&pm8937_l2>; |
| 103 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 104 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 105 | <&clock_gcc clk_gcc_camss_csi1_ahb_clk>, |
| 106 | <&clock_gcc clk_csi1_clk_src>, |
| 107 | <&clock_gcc clk_gcc_camss_csi1phy_clk>, |
| 108 | <&clock_gcc clk_gcc_camss_csi1_clk>, |
| 109 | <&clock_gcc clk_gcc_camss_csi1pix_clk>, |
| 110 | <&clock_gcc clk_gcc_camss_csi1rdi_clk>, |
| 111 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 112 | clock-names = "camss_top_ahb_clk", |
| 113 | "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", |
| 114 | "csi1_phy_clk", |
| 115 | "csi_clk", "csi_pix_clk", |
| 116 | "csi_rdi_clk", "camss_ahb_clk"; |
| 117 | qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; |
| 118 | }; |
| 119 | |
| 120 | qcom,csid@1b30800 { |
| 121 | status = "ok"; |
| 122 | cell-index = <2>; |
| 123 | compatible = "qcom,csid-v3.4.2", "qcom,csid"; |
| 124 | reg = <0x1b30800 0x400>; |
| 125 | reg-names = "csid"; |
| 126 | interrupts = <0 153 0>; |
| 127 | interrupt-names = "csid"; |
| 128 | qcom,csi-vdd-voltage = <1200000>; |
| 129 | qcom,mipi-csi-vdd-supply = <&pm8937_l2>; |
| 130 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 131 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 132 | <&clock_gcc clk_gcc_camss_csi2_ahb_clk>, |
| 133 | <&clock_gcc clk_csi2_clk_src>, |
| 134 | <&clock_gcc clk_gcc_camss_csi2phy_clk>, |
| 135 | <&clock_gcc clk_gcc_camss_csi2_clk>, |
| 136 | <&clock_gcc clk_gcc_camss_csi2pix_clk>, |
| 137 | <&clock_gcc clk_gcc_camss_csi2rdi_clk>, |
| 138 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 139 | clock-names = "camss_top_ahb_clk", |
| 140 | "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", |
| 141 | "csi2_phy_clk", |
| 142 | "csi_clk", "csi_pix_clk", |
| 143 | "csi_rdi_clk", "camss_ahb_clk"; |
| 144 | qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; |
| 145 | }; |
| 146 | |
| 147 | qcom,ispif@1b31000 { |
| 148 | cell-index = <0>; |
| 149 | compatible = "qcom,ispif-v3.0", "qcom,ispif"; |
| 150 | reg = <0x1b31000 0x500>, |
| 151 | <0x1b00020 0x10>; |
| 152 | reg-names = "ispif", "csi_clk_mux"; |
| 153 | interrupts = <0 55 0>; |
| 154 | interrupt-names = "ispif"; |
| 155 | qcom,num-isps = <0x2>; |
| 156 | vfe0-vdd-supply = <&gdsc_vfe>; |
| 157 | vfe1-vdd-supply = <&gdsc_vfe1>; |
| 158 | qcom,vdd-names = "vfe0-vdd", "vfe1-vdd"; |
| 159 | clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 160 | <&clock_gcc clk_gcc_camss_ahb_clk>, |
| 161 | <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 162 | <&clock_gcc clk_camss_top_ahb_clk_src>, |
| 163 | <&clock_gcc clk_csi0_clk_src>, |
| 164 | <&clock_gcc clk_gcc_camss_csi0_clk>, |
| 165 | <&clock_gcc clk_gcc_camss_csi0rdi_clk>, |
| 166 | <&clock_gcc clk_gcc_camss_csi0pix_clk>, |
| 167 | <&clock_gcc clk_csi1_clk_src>, |
| 168 | <&clock_gcc clk_gcc_camss_csi1_clk>, |
| 169 | <&clock_gcc clk_gcc_camss_csi1rdi_clk>, |
| 170 | <&clock_gcc clk_gcc_camss_csi1pix_clk>, |
| 171 | <&clock_gcc clk_csi2_clk_src>, |
| 172 | <&clock_gcc clk_gcc_camss_csi2_clk>, |
| 173 | <&clock_gcc clk_gcc_camss_csi2rdi_clk>, |
| 174 | <&clock_gcc clk_gcc_camss_csi2pix_clk>, |
| 175 | <&clock_gcc clk_vfe0_clk_src>, |
| 176 | <&clock_gcc clk_gcc_camss_vfe0_clk>, |
| 177 | <&clock_gcc clk_gcc_camss_csi_vfe0_clk>, |
| 178 | <&clock_gcc clk_vfe1_clk_src>, |
| 179 | <&clock_gcc clk_gcc_camss_vfe1_clk>, |
| 180 | <&clock_gcc clk_gcc_camss_csi_vfe1_clk>; |
| 181 | clock-names = "ispif_ahb_clk", |
| 182 | "camss_ahb_clk", "camss_top_ahb_clk", |
| 183 | "camss_ahb_src", |
| 184 | "csi0_src_clk", "csi0_clk", |
| 185 | "csi0_rdi_clk", "csi0_pix_clk", |
| 186 | "csi1_src_clk", "csi1_clk", |
| 187 | "csi1_rdi_clk", "csi1_pix_clk", |
| 188 | "csi2_src_clk", "csi2_clk", |
| 189 | "csi2_rdi_clk", "csi2_pix_clk", |
| 190 | "vfe0_clk_src", "camss_vfe_vfe0_clk", |
| 191 | "camss_csi_vfe0_clk", "vfe1_clk_src", |
| 192 | "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; |
| 193 | qcom,clock-rates = <61540000 0 0 0 |
| 194 | 200000000 0 0 0 |
| 195 | 200000000 0 0 0 |
| 196 | 200000000 0 0 0 |
| 197 | 0 0 0 |
| 198 | 0 0 0>; |
| 199 | qcom,clock-cntl-support; |
| 200 | qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE", |
| 201 | "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", |
| 202 | "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", |
| 203 | "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", |
| 204 | "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", |
| 205 | "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", |
| 206 | "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", |
| 207 | "NO_SET_RATE"; |
| 208 | }; |
| 209 | |
| 210 | vfe0: qcom,vfe0@1b10000 { |
| 211 | cell-index = <0>; |
| 212 | compatible = "qcom,vfe40"; |
| 213 | reg = <0x1b10000 0x1000>, |
| 214 | <0x1b40000 0x200>; |
| 215 | reg-names = "vfe", "vfe_vbif"; |
| 216 | interrupts = <0 57 0>; |
| 217 | interrupt-names = "vfe"; |
| 218 | vdd-supply = <&gdsc_vfe>; |
| 219 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 220 | <&clock_gcc clk_gcc_camss_ahb_clk>, |
| 221 | <&clock_gcc clk_vfe0_clk_src>, |
| 222 | <&clock_gcc clk_gcc_camss_vfe0_clk>, |
| 223 | <&clock_gcc clk_gcc_camss_csi_vfe0_clk>, |
| 224 | <&clock_gcc clk_gcc_camss_vfe_ahb_clk>, |
| 225 | <&clock_gcc clk_gcc_camss_vfe_axi_clk>, |
| 226 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>; |
| 227 | clock-names = "camss_top_ahb_clk", "camss_ahb_clk", |
| 228 | "vfe_clk_src", "camss_vfe_vfe_clk", |
| 229 | "camss_csi_vfe_clk", "iface_clk", |
| 230 | "bus_clk", "iface_ahb_clk"; |
| 231 | qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; |
| 232 | qos-entries = <8>; |
| 233 | qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 |
| 234 | 0x2dc 0x2e0>; |
| 235 | qos-settings = <0xaa55aa55 |
| 236 | 0xaa55aa55 0xaa55aa55 |
| 237 | 0xaa55aa55 0xaa55aa55 |
| 238 | 0xaa55aa55 0xaa55aa55 |
| 239 | 0xaa55aa55>; |
| 240 | vbif-entries = <1>; |
| 241 | vbif-regs = <0x124>; |
| 242 | vbif-settings = <0x3>; |
| 243 | ds-entries = <17>; |
| 244 | ds-regs = <0x988 0x98c 0x990 0x994 0x998 |
| 245 | 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 |
| 246 | 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; |
| 247 | ds-settings = <0xcccc1111 |
| 248 | 0xcccc1111 0xcccc1111 |
| 249 | 0xcccc1111 0xcccc1111 |
| 250 | 0xcccc1111 0xcccc1111 |
| 251 | 0xcccc1111 0xcccc1111 |
| 252 | 0xcccc1111 0xcccc1111 |
| 253 | 0xcccc1111 0xcccc1111 |
| 254 | 0xcccc1111 0xcccc1111 |
| 255 | 0xcccc1111 0x00000110>; |
| 256 | max-clk-nominal = <400000000>; |
| 257 | max-clk-turbo = <432000000>; |
| 258 | }; |
| 259 | |
| 260 | vfe1: qcom,vfe1@1b14000 { |
| 261 | cell-index = <1>; |
| 262 | compatible = "qcom,vfe40"; |
| 263 | reg = <0x1b14000 0x1000>, |
| 264 | <0x1ba0000 0x200>; |
| 265 | reg-names = "vfe", "vfe_vbif"; |
| 266 | interrupts = <0 29 0>; |
| 267 | interrupt-names = "vfe"; |
| 268 | vdd-supply = <&gdsc_vfe1>; |
| 269 | clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 270 | <&clock_gcc clk_gcc_camss_ahb_clk>, |
| 271 | <&clock_gcc clk_vfe1_clk_src>, |
| 272 | <&clock_gcc clk_gcc_camss_vfe1_clk>, |
| 273 | <&clock_gcc clk_gcc_camss_csi_vfe1_clk>, |
| 274 | <&clock_gcc clk_gcc_camss_vfe1_ahb_clk>, |
| 275 | <&clock_gcc clk_gcc_camss_vfe1_axi_clk>, |
| 276 | <&clock_gcc clk_gcc_camss_ispif_ahb_clk>; |
| 277 | clock-names = "camss_top_ahb_clk" , "camss_ahb_clk", |
| 278 | "vfe_clk_src", "camss_vfe_vfe_clk", |
| 279 | "camss_csi_vfe_clk", "iface_clk", |
| 280 | "bus_clk", "iface_ahb_clk"; |
| 281 | qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; |
| 282 | qos-entries = <8>; |
| 283 | qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 |
| 284 | 0x2dc 0x2e0>; |
| 285 | qos-settings = <0xaa55aa55 |
| 286 | 0xaa55aa55 0xaa55aa55 |
| 287 | 0xaa55aa55 0xaa55aa55 |
| 288 | 0xaa55aa55 0xaa55aa55 |
| 289 | 0xaa55aa55>; |
| 290 | vbif-entries = <1>; |
| 291 | vbif-regs = <0x124>; |
| 292 | vbif-settings = <0x3>; |
| 293 | ds-entries = <17>; |
| 294 | ds-regs = <0x988 0x98c 0x990 0x994 0x998 |
| 295 | 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 |
| 296 | 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; |
| 297 | ds-settings = <0xcccc1111 |
| 298 | 0xcccc1111 0xcccc1111 |
| 299 | 0xcccc1111 0xcccc1111 |
| 300 | 0xcccc1111 0xcccc1111 |
| 301 | 0xcccc1111 0xcccc1111 |
| 302 | 0xcccc1111 0xcccc1111 |
| 303 | 0xcccc1111 0xcccc1111 |
| 304 | 0xcccc1111 0xcccc1111 |
| 305 | 0xcccc1111 0x00000110>; |
| 306 | max-clk-nominal = <400000000>; |
| 307 | max-clk-turbo = <432000000>; |
| 308 | }; |
| 309 | |
| 310 | qcom,vfe { |
| 311 | compatible = "qcom,vfe"; |
| 312 | num_child = <2>; |
| 313 | }; |
| 314 | |
| 315 | qcom,cam_smmu { |
| 316 | status = "ok"; |
| 317 | compatible = "qcom,msm-cam-smmu"; |
| 318 | msm_cam_smmu_cb1: msm_cam_smmu_cb1 { |
| 319 | compatible = "qcom,msm-cam-smmu-cb"; |
| 320 | iommus = <&apps_iommu 0x400 0x00>, |
| 321 | <&apps_iommu 0x2400 0x00>; |
| 322 | label = "vfe"; |
| 323 | qcom,scratch-buf-support; |
| 324 | }; |
| 325 | |
| 326 | msm_cam_smmu_cb2: msm_cam_smmu_cb2 { |
| 327 | compatible = "qcom,msm-cam-smmu-cb"; |
| 328 | label = "vfe_secure"; |
| 329 | qcom,secure-context; |
| 330 | }; |
| 331 | |
| 332 | msm_cam_smmu_cb3: msm_cam_smmu_cb3 { |
| 333 | compatible = "qcom,msm-cam-smmu-cb"; |
| 334 | iommus = <&apps_iommu 0x1c00 0x00>; |
| 335 | label = "cpp"; |
| 336 | }; |
| 337 | |
| 338 | msm_cam_smmu_cb4: msm_cam_smmu_cb4 { |
| 339 | compatible = "qcom,msm-cam-smmu-cb"; |
| 340 | iommus = <&apps_iommu 0x1800 0x00>; |
| 341 | label = "jpeg_enc0"; |
| 342 | }; |
| 343 | }; |
| 344 | |
| 345 | qcom,jpeg@1b1c000 { |
| 346 | status = "ok"; |
| 347 | cell-index = <0>; |
| 348 | compatible = "qcom,jpeg"; |
| 349 | reg = <0x1b1c000 0x400>, |
| 350 | <0x1b60000 0xc30>; |
| 351 | reg-names = "jpeg_hw", "jpeg_vbif"; |
| 352 | interrupts = <0 59 0>; |
| 353 | interrupt-names = "jpeg"; |
| 354 | vdd-supply = <&gdsc_jpeg>; |
| 355 | qcom,vdd-names = "vdd"; |
| 356 | clock-names = "core_clk", "iface_clk", "bus_clk0", |
| 357 | "camss_top_ahb_clk", "camss_ahb_clk"; |
| 358 | clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>, |
| 359 | <&clock_gcc clk_gcc_camss_jpeg_ahb_clk>, |
| 360 | <&clock_gcc clk_gcc_camss_jpeg_axi_clk>, |
| 361 | <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 362 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 363 | qcom,clock-rates = <266670000 0 0 0 0>; |
| 364 | qcom,qos-reg-settings = <0x28 0x0000555e>, |
| 365 | <0xc8 0x00005555>; |
| 366 | qcom,vbif-reg-settings = <0xc0 0x10101000>, |
| 367 | <0xb0 0x10100010>; |
| 368 | qcom,msm-bus,name = "msm_camera_jpeg0"; |
| 369 | qcom,msm-bus,num-cases = <2>; |
| 370 | qcom,msm-bus,num-paths = <1>; |
| 371 | qcom,msm-bus,vectors-KBps = <62 512 0 0>, |
| 372 | <62 512 800000 800000>; |
| 373 | }; |
| 374 | |
| 375 | qcom,irqrouter@1b00000 { |
| 376 | status = "ok"; |
| 377 | cell-index = <0>; |
| 378 | compatible = "qcom,irqrouter"; |
| 379 | reg = <0x1b00000 0x100>; |
| 380 | reg-names = "irqrouter"; |
| 381 | }; |
| 382 | |
| 383 | qcom,cpp@1b04000 { |
| 384 | status = "ok"; |
| 385 | cell-index = <0>; |
| 386 | compatible = "qcom,cpp"; |
| 387 | reg = <0x1b04000 0x100>, |
| 388 | <0x1b80000 0x200>, |
| 389 | <0x1b18000 0x018>, |
| 390 | <0x1858078 0x4>; |
| 391 | reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; |
| 392 | interrupts = <0 49 0>; |
| 393 | interrupt-names = "cpp"; |
| 394 | vdd-supply = <&gdsc_cpp>; |
| 395 | qcom,vdd-names = "vdd"; |
| 396 | clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 397 | <&clock_gcc clk_cpp_clk_src>, |
| 398 | <&clock_gcc clk_gcc_camss_top_ahb_clk>, |
| 399 | <&clock_gcc clk_gcc_camss_cpp_ahb_clk>, |
| 400 | <&clock_gcc clk_gcc_camss_cpp_axi_clk>, |
| 401 | <&clock_gcc clk_gcc_camss_cpp_clk>, |
| 402 | <&clock_gcc clk_gcc_camss_micro_ahb_clk>, |
| 403 | <&clock_gcc clk_gcc_camss_ahb_clk>; |
| 404 | clock-names = "ispif_ahb_clk", "cpp_core_clk", |
| 405 | "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk", |
| 406 | "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk", |
| 407 | "micro_iface_clk", "camss_ahb_clk"; |
| 408 | qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>; |
| 409 | qcom,min-clock-rate = <133000000>; |
| 410 | resets = <&clock_gcc GCC_CAMSS_MICRO_BCR>; |
| 411 | reset-names = "micro_iface_reset"; |
| 412 | qcom,bus-master = <1>; |
| 413 | qcom,msm-bus,name = "msm_camera_cpp"; |
| 414 | qcom,msm-bus,num-cases = <2>; |
| 415 | qcom,msm-bus,num-paths = <1>; |
| 416 | qcom,msm-bus,vectors-KBps = |
| 417 | <106 512 0 0>, |
| 418 | <106 512 0 0>; |
| 419 | qcom,msm-bus-vector-dyn-vote; |
| 420 | qcom,micro-reset; |
| 421 | qcom,cpp-fw-payload-info { |
| 422 | qcom,stripe-base = <156>; |
| 423 | qcom,plane-base = <141>; |
| 424 | qcom,stripe-size = <27>; |
| 425 | qcom,plane-size = <5>; |
| 426 | qcom,fe-ptr-off = <5>; |
| 427 | qcom,we-ptr-off = <11>; |
| 428 | }; |
| 429 | }; |
| 430 | |
| 431 | cci: qcom,cci@1b0c000 { |
| 432 | status = "ok"; |
| 433 | cell-index = <0>; |
| 434 | compatible = "qcom,cci"; |
| 435 | reg = <0x1b0c000 0x4000>; |
| 436 | #address-cells = <1>; |
| 437 | #size-cells = <0>; |
| 438 | reg-names = "cci"; |
| 439 | interrupts = <0 50 0>; |
| 440 | interrupt-names = "cci"; |
| 441 | clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>, |
| 442 | <&clock_gcc clk_cci_clk_src>, |
| 443 | <&clock_gcc clk_gcc_camss_cci_ahb_clk>, |
| 444 | <&clock_gcc clk_gcc_camss_cci_clk>, |
| 445 | <&clock_gcc clk_gcc_camss_ahb_clk>, |
| 446 | <&clock_gcc clk_gcc_camss_top_ahb_clk>; |
| 447 | clock-names = "ispif_ahb_clk", "cci_src_clk", |
| 448 | "cci_ahb_clk", "camss_cci_clk", |
| 449 | "camss_ahb_clk", "camss_top_ahb_clk"; |
| 450 | qcom,clock-rates = <61540000 19200000 0 0 0 0>, |
| 451 | <61540000 37500000 0 0 0 0>; |
| 452 | pinctrl-names = "cci_default", "cci_suspend"; |
| 453 | pinctrl-0 = <&cci0_active &cci1_active>; |
| 454 | pinctrl-1 = <&cci0_suspend &cci1_suspend>; |
| 455 | gpios = <&tlmm 29 0>, |
| 456 | <&tlmm 30 0>, |
| 457 | <&tlmm 31 0>, |
| 458 | <&tlmm 32 0>; |
| 459 | qcom,gpio-tbl-num = <0 1 2 3>; |
| 460 | qcom,gpio-tbl-flags = <1 1 1 1>; |
| 461 | qcom,gpio-tbl-label = "CCI_I2C_DATA0", |
| 462 | "CCI_I2C_CLK0", |
| 463 | "CCI_I2C_DATA1", |
| 464 | "CCI_I2C_CLK1"; |
| 465 | i2c_freq_100Khz: qcom,i2c_standard_mode { |
| 466 | status = "disabled"; |
| 467 | }; |
| 468 | i2c_freq_400Khz: qcom,i2c_fast_mode { |
| 469 | status = "disabled"; |
| 470 | }; |
| 471 | i2c_freq_custom: qcom,i2c_custom_mode { |
| 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
| 475 | i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { |
| 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
| 479 | }; |
| 480 | }; |
| 481 | |
| 482 | &i2c_freq_100Khz { |
| 483 | qcom,hw-thigh = <78>; |
| 484 | qcom,hw-tlow = <114>; |
| 485 | qcom,hw-tsu-sto = <28>; |
| 486 | qcom,hw-tsu-sta = <28>; |
| 487 | qcom,hw-thd-dat = <10>; |
| 488 | qcom,hw-thd-sta = <77>; |
| 489 | qcom,hw-tbuf = <118>; |
| 490 | qcom,hw-scl-stretch-en = <0>; |
| 491 | qcom,hw-trdhld = <6>; |
| 492 | qcom,hw-tsp = <1>; |
| 493 | }; |
| 494 | |
| 495 | &i2c_freq_400Khz { |
| 496 | qcom,hw-thigh = <20>; |
| 497 | qcom,hw-tlow = <28>; |
| 498 | qcom,hw-tsu-sto = <21>; |
| 499 | qcom,hw-tsu-sta = <21>; |
| 500 | qcom,hw-thd-dat = <13>; |
| 501 | qcom,hw-thd-sta = <18>; |
| 502 | qcom,hw-tbuf = <32>; |
| 503 | qcom,hw-scl-stretch-en = <0>; |
| 504 | qcom,hw-trdhld = <6>; |
| 505 | qcom,hw-tsp = <3>; |
| 506 | status = "ok"; |
| 507 | }; |
| 508 | |
| 509 | &i2c_freq_custom { |
| 510 | qcom,hw-thigh = <15>; |
| 511 | qcom,hw-tlow = <28>; |
| 512 | qcom,hw-tsu-sto = <21>; |
| 513 | qcom,hw-tsu-sta = <21>; |
| 514 | qcom,hw-thd-dat = <13>; |
| 515 | qcom,hw-thd-sta = <18>; |
| 516 | qcom,hw-tbuf = <25>; |
| 517 | qcom,hw-scl-stretch-en = <1>; |
| 518 | qcom,hw-trdhld = <6>; |
| 519 | qcom,hw-tsp = <3>; |
| 520 | status = "ok"; |
| 521 | }; |
| 522 | |
| 523 | &i2c_freq_1Mhz { |
| 524 | qcom,hw-thigh = <16>; |
| 525 | qcom,hw-tlow = <22>; |
| 526 | qcom,hw-tsu-sto = <17>; |
| 527 | qcom,hw-tsu-sta = <18>; |
| 528 | qcom,hw-thd-dat = <16>; |
| 529 | qcom,hw-thd-sta = <15>; |
| 530 | qcom,hw-tbuf = <19>; |
| 531 | qcom,hw-scl-stretch-en = <1>; |
| 532 | qcom,hw-trdhld = <3>; |
| 533 | qcom,hw-tsp = <3>; |
| 534 | qcom,cci-clk-src = <37500000>; |
| 535 | status = "ok"; |
| 536 | }; |