| Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. |
| 3 | * |
| 4 | * Module: __INC_HAL8192SPHYREG_H |
| 5 | * |
| 6 | * |
| 7 | * Note: 1. Define PMAC/BB register map |
| 8 | * 2. Define RF register map |
| 9 | * 3. PMAC/BB register bit mask. |
| 10 | * 4. RF reg bit mask. |
| 11 | * 5. Other BB/RF relative definition. |
| 12 | * |
| 13 | * |
| 14 | * Export: Constants, macro, functions(API), global variables(None). |
| 15 | * |
| 16 | * Abbrev: |
| 17 | * |
| 18 | * History: |
| 19 | * Data Who Remark |
| 20 | * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. |
| 21 | * 2. Reorganize code architecture. |
| 22 | * 09/25/2008 MH 1. Add RL6052 register definition |
| 23 | * |
| 24 | *****************************************************************************/ |
| 25 | #ifndef __INC_HAL8192SPHYREG_H |
| 26 | #define __INC_HAL8192SPHYREG_H |
| 27 | |
| 28 | |
| 29 | /*--------------------------Define Parameters-------------------------------*/ |
| 30 | |
| 31 | //============================================================ |
| 32 | // 8192S Regsiter offset definition |
| 33 | //============================================================ |
| 34 | |
| 35 | // |
| 36 | // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF |
| 37 | // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF |
| 38 | // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 |
| 39 | // 3. RF register 0x00-2E |
| 40 | // 4. Bit Mask for BB/RF register |
| Adam Buchbinder | 6070d81 | 2009-12-04 15:47:01 -0500 | [diff] [blame] | 41 | // 5. Other definition for BB/RF R/W |
| Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 42 | // |
| 43 | |
| 44 | |
| 45 | // |
| 46 | // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF |
| 47 | // 1. Page1(0x100) |
| 48 | // |
| 49 | #define rPMAC_Reset 0x100 |
| 50 | #define rPMAC_TxStart 0x104 |
| 51 | #define rPMAC_TxLegacySIG 0x108 |
| 52 | #define rPMAC_TxHTSIG1 0x10c |
| 53 | #define rPMAC_TxHTSIG2 0x110 |
| 54 | #define rPMAC_PHYDebug 0x114 |
| 55 | #define rPMAC_TxPacketNum 0x118 |
| 56 | #define rPMAC_TxIdle 0x11c |
| 57 | #define rPMAC_TxMACHeader0 0x120 |
| 58 | #define rPMAC_TxMACHeader1 0x124 |
| 59 | #define rPMAC_TxMACHeader2 0x128 |
| 60 | #define rPMAC_TxMACHeader3 0x12c |
| 61 | #define rPMAC_TxMACHeader4 0x130 |
| 62 | #define rPMAC_TxMACHeader5 0x134 |
| 63 | #define rPMAC_TxDataType 0x138 |
| 64 | #define rPMAC_TxRandomSeed 0x13c |
| 65 | #define rPMAC_CCKPLCPPreamble 0x140 |
| 66 | #define rPMAC_CCKPLCPHeader 0x144 |
| 67 | #define rPMAC_CCKCRC16 0x148 |
| 68 | #define rPMAC_OFDMRxCRC32OK 0x170 |
| 69 | #define rPMAC_OFDMRxCRC32Er 0x174 |
| 70 | #define rPMAC_OFDMRxParityEr 0x178 |
| 71 | #define rPMAC_OFDMRxCRC8Er 0x17c |
| 72 | #define rPMAC_CCKCRxRC16Er 0x180 |
| 73 | #define rPMAC_CCKCRxRC32Er 0x184 |
| 74 | #define rPMAC_CCKCRxRC32OK 0x188 |
| 75 | #define rPMAC_TxStatus 0x18c |
| 76 | |
| 77 | // |
| 78 | // 2. Page2(0x200) |
| 79 | // |
| 80 | // The following two definition are only used for USB interface. |
| 81 | #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. |
| 82 | #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. |
| 83 | |
| 84 | // |
| 85 | // 3. Page8(0x800) |
| 86 | // |
| 87 | #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? |
| 88 | |
| 89 | #define rFPGA0_TxInfo 0x804 // Status report?? |
| 90 | #define rFPGA0_PSDFunction 0x808 |
| 91 | |
| 92 | #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? |
| 93 | |
| 94 | #define rFPGA0_RFTiming1 0x810 // Useless now |
| 95 | #define rFPGA0_RFTiming2 0x814 |
| 96 | //#define rFPGA0_XC_RFTiming 0x818 |
| 97 | //#define rFPGA0_XD_RFTiming 0x81c |
| 98 | |
| 99 | #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register |
| 100 | #define rFPGA0_XA_HSSIParameter2 0x824 |
| 101 | #define rFPGA0_XB_HSSIParameter1 0x828 |
| 102 | #define rFPGA0_XB_HSSIParameter2 0x82c |
| 103 | #define rFPGA0_XC_HSSIParameter1 0x830 |
| 104 | #define rFPGA0_XC_HSSIParameter2 0x834 |
| 105 | #define rFPGA0_XD_HSSIParameter1 0x838 |
| 106 | #define rFPGA0_XD_HSSIParameter2 0x83c |
| 107 | #define rFPGA0_XA_LSSIParameter 0x840 |
| 108 | #define rFPGA0_XB_LSSIParameter 0x844 |
| 109 | #define rFPGA0_XC_LSSIParameter 0x848 |
| 110 | #define rFPGA0_XD_LSSIParameter 0x84c |
| 111 | |
| 112 | #define rFPGA0_RFWakeUpParameter 0x850 // Useless now |
| 113 | #define rFPGA0_RFSleepUpParameter 0x854 |
| 114 | |
| 115 | #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch |
| 116 | #define rFPGA0_XCD_SwitchControl 0x85c |
| 117 | |
| 118 | #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch |
| 119 | #define rFPGA0_XB_RFInterfaceOE 0x864 |
| 120 | #define rFPGA0_XC_RFInterfaceOE 0x868 |
| 121 | #define rFPGA0_XD_RFInterfaceOE 0x86c |
| 122 | |
| 123 | #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control |
| 124 | #define rFPGA0_XCD_RFInterfaceSW 0x874 |
| 125 | |
| 126 | #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter |
| 127 | #define rFPGA0_XCD_RFParameter 0x87c |
| 128 | |
| 129 | #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? |
| 130 | #define rFPGA0_AnalogParameter2 0x884 |
| 131 | #define rFPGA0_AnalogParameter3 0x888 // Useless now |
| 132 | #define rFPGA0_AnalogParameter4 0x88c |
| 133 | |
| 134 | #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback |
| 135 | #define rFPGA0_XB_LSSIReadBack 0x8a4 |
| 136 | #define rFPGA0_XC_LSSIReadBack 0x8a8 |
| 137 | #define rFPGA0_XD_LSSIReadBack 0x8ac |
| 138 | |
| 139 | #define rFPGA0_PSDReport 0x8b4 // Useless now |
| 140 | #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback |
| 141 | #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback |
| 142 | #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value |
| 143 | #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now |
| 144 | |
| 145 | // |
| 146 | // 4. Page9(0x900) |
| 147 | // |
| 148 | #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? |
| 149 | |
| 150 | #define rFPGA1_TxBlock 0x904 // Useless now |
| 151 | #define rFPGA1_DebugSelect 0x908 // Useless now |
| 152 | #define rFPGA1_TxInfo 0x90c // Useless now // Status report?? |
| 153 | |
| 154 | // |
| 155 | // 5. PageA(0xA00) |
| 156 | // |
| 157 | // Set Control channel to upper or lower. These settings are required only for 40MHz |
| 158 | #define rCCK0_System 0xa00 |
| 159 | |
| 160 | #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI |
| 161 | #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain |
| 162 | |
| 163 | #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series |
| 164 | #define rCCK0_RxAGC2 0xa10 //AGC & DAGC |
| 165 | |
| 166 | #define rCCK0_RxHP 0xa14 |
| 167 | |
| 168 | #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold |
| 169 | #define rCCK0_DSPParameter2 0xa1c //SQ threshold |
| 170 | |
| 171 | #define rCCK0_TxFilter1 0xa20 |
| 172 | #define rCCK0_TxFilter2 0xa24 |
| 173 | #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 |
| 174 | #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report |
| 175 | #define rCCK0_TRSSIReport 0xa50 |
| 176 | #define rCCK0_RxReport 0xa54 //0xa57 |
| 177 | #define rCCK0_FACounterLower 0xa5c //0xa5b |
| 178 | #define rCCK0_FACounterUpper 0xa58 //0xa5c |
| 179 | |
| 180 | // |
| 181 | // 6. PageC(0xC00) |
| 182 | // |
| 183 | #define rOFDM0_LSTF 0xc00 |
| 184 | |
| 185 | #define rOFDM0_TRxPathEnable 0xc04 |
| 186 | #define rOFDM0_TRMuxPar 0xc08 |
| 187 | #define rOFDM0_TRSWIsolation 0xc0c |
| 188 | |
| 189 | #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter |
| 190 | #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix |
| 191 | #define rOFDM0_XBRxAFE 0xc18 |
| 192 | #define rOFDM0_XBRxIQImbalance 0xc1c |
| 193 | #define rOFDM0_XCRxAFE 0xc20 |
| 194 | #define rOFDM0_XCRxIQImbalance 0xc24 |
| 195 | #define rOFDM0_XDRxAFE 0xc28 |
| 196 | #define rOFDM0_XDRxIQImbalance 0xc2c |
| 197 | |
| 198 | #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain |
| 199 | #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. |
| 200 | #define rOFDM0_RxDetector3 0xc38 //Frame Sync. |
| 201 | #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI |
| 202 | |
| 203 | #define rOFDM0_RxDSP 0xc40 //Rx Sync Path |
| 204 | #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC |
| 205 | #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold |
| 206 | #define rOFDM0_ECCAThreshold 0xc4c // energy CCA |
| 207 | |
| 208 | #define rOFDM0_XAAGCCore1 0xc50 // DIG |
| 209 | #define rOFDM0_XAAGCCore2 0xc54 |
| 210 | #define rOFDM0_XBAGCCore1 0xc58 |
| 211 | #define rOFDM0_XBAGCCore2 0xc5c |
| 212 | #define rOFDM0_XCAGCCore1 0xc60 |
| 213 | #define rOFDM0_XCAGCCore2 0xc64 |
| 214 | #define rOFDM0_XDAGCCore1 0xc68 |
| 215 | #define rOFDM0_XDAGCCore2 0xc6c |
| 216 | |
| 217 | #define rOFDM0_AGCParameter1 0xc70 |
| 218 | #define rOFDM0_AGCParameter2 0xc74 |
| 219 | #define rOFDM0_AGCRSSITable 0xc78 |
| 220 | #define rOFDM0_HTSTFAGC 0xc7c |
| 221 | |
| 222 | #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG |
| 223 | #define rOFDM0_XATxAFE 0xc84 |
| 224 | #define rOFDM0_XBTxIQImbalance 0xc88 |
| 225 | #define rOFDM0_XBTxAFE 0xc8c |
| 226 | #define rOFDM0_XCTxIQImbalance 0xc90 |
| 227 | #define rOFDM0_XCTxAFE 0xc94 |
| 228 | #define rOFDM0_XDTxIQImbalance 0xc98 |
| 229 | #define rOFDM0_XDTxAFE 0xc9c |
| 230 | |
| 231 | #define rOFDM0_RxHPParameter 0xce0 |
| 232 | #define rOFDM0_TxPseudoNoiseWgt 0xce4 |
| 233 | #define rOFDM0_FrameSync 0xcf0 |
| 234 | #define rOFDM0_DFSReport 0xcf4 |
| 235 | #define rOFDM0_TxCoeff1 0xca4 |
| 236 | #define rOFDM0_TxCoeff2 0xca8 |
| 237 | #define rOFDM0_TxCoeff3 0xcac |
| 238 | #define rOFDM0_TxCoeff4 0xcb0 |
| 239 | #define rOFDM0_TxCoeff5 0xcb4 |
| 240 | #define rOFDM0_TxCoeff6 0xcb8 |
| 241 | |
| 242 | |
| 243 | // |
| 244 | // 7. PageD(0xD00) |
| 245 | // |
| 246 | #define rOFDM1_LSTF 0xd00 |
| 247 | #define rOFDM1_TRxPathEnable 0xd04 |
| 248 | #define rOFDM1_CFO 0xd08 // No setting now |
| 249 | #define rOFDM1_CSI1 0xd10 |
| 250 | #define rOFDM1_SBD 0xd14 |
| 251 | #define rOFDM1_CSI2 0xd18 |
| 252 | #define rOFDM1_CFOTracking 0xd2c |
| 253 | #define rOFDM1_TRxMesaure1 0xd34 |
| 254 | #define rOFDM1_IntfDet 0xd3c |
| 255 | #define rOFDM1_PseudoNoiseStateAB 0xd50 |
| 256 | #define rOFDM1_PseudoNoiseStateCD 0xd54 |
| 257 | #define rOFDM1_RxPseudoNoiseWgt 0xd58 |
| 258 | |
| 259 | #define rOFDM_PHYCounter1 0xda0 //cca, parity fail |
| 260 | #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail |
| 261 | #define rOFDM_PHYCounter3 0xda8 //MCS not support |
| 262 | #define rOFDM_ShortCFOAB 0xdac // No setting now |
| 263 | #define rOFDM_ShortCFOCD 0xdb0 |
| 264 | #define rOFDM_LongCFOAB 0xdb4 |
| 265 | #define rOFDM_LongCFOCD 0xdb8 |
| 266 | #define rOFDM_TailCFOAB 0xdbc |
| 267 | #define rOFDM_TailCFOCD 0xdc0 |
| 268 | #define rOFDM_PWMeasure1 0xdc4 |
| 269 | #define rOFDM_PWMeasure2 0xdc8 |
| 270 | #define rOFDM_BWReport 0xdcc |
| 271 | #define rOFDM_AGCReport 0xdd0 |
| 272 | #define rOFDM_RxSNR 0xdd4 |
| 273 | #define rOFDM_RxEVMCSI 0xdd8 |
| 274 | #define rOFDM_SIGReport 0xddc |
| 275 | |
| 276 | |
| 277 | // |
| 278 | // 8. PageE(0xE00) |
| 279 | // |
| 280 | #define rTxAGC_Rate18_06 0xe00 |
| 281 | #define rTxAGC_Rate54_24 0xe04 |
| 282 | #define rTxAGC_CCK_Mcs32 0xe08 |
| 283 | #define rTxAGC_Mcs03_Mcs00 0xe10 |
| 284 | #define rTxAGC_Mcs07_Mcs04 0xe14 |
| 285 | #define rTxAGC_Mcs11_Mcs08 0xe18 |
| 286 | #define rTxAGC_Mcs15_Mcs12 0xe1c |
| 287 | |
| 288 | // |
| 289 | // 7. RF Register 0x00-0x2E (RF 8256) |
| 290 | // RF-0222D 0x00-3F |
| 291 | // |
| 292 | //Zebra1 |
| 293 | #define rZebra1_HSSIEnable 0x0 // Useless now |
| 294 | #define rZebra1_TRxEnable1 0x1 |
| 295 | #define rZebra1_TRxEnable2 0x2 |
| 296 | #define rZebra1_AGC 0x4 |
| 297 | #define rZebra1_ChargePump 0x5 |
| 298 | //#if (RTL92SE_FPGA_VERIFY == 1) |
| 299 | #define rZebra1_Channel 0x7 // RF channel switch |
| 300 | //#else |
| 301 | |
| 302 | //#endif |
| 303 | #define rZebra1_TxGain 0x8 // Useless now |
| 304 | #define rZebra1_TxLPF 0x9 |
| 305 | #define rZebra1_RxLPF 0xb |
| 306 | #define rZebra1_RxHPFCorner 0xc |
| 307 | |
| 308 | //Zebra4 |
| 309 | #define rGlobalCtrl 0 // Useless now |
| 310 | #define rRTL8256_TxLPF 19 |
| 311 | #define rRTL8256_RxLPF 11 |
| 312 | |
| 313 | //RTL8258 |
| 314 | #define rRTL8258_TxLPF 0x11 // Useless now |
| 315 | #define rRTL8258_RxLPF 0x13 |
| 316 | #define rRTL8258_RSSILPF 0xa |
| 317 | |
| 318 | // |
| 319 | // RL6052 Register definition |
| 320 | // |
| 321 | #define RF_AC 0x00 // |
| 322 | |
| 323 | #define RF_IQADJ_G1 0x01 // |
| 324 | #define RF_IQADJ_G2 0x02 // |
| 325 | #define RF_POW_TRSW 0x05 // |
| 326 | |
| 327 | #define RF_GAIN_RX 0x06 // |
| 328 | #define RF_GAIN_TX 0x07 // |
| 329 | |
| 330 | #define RF_TXM_IDAC 0x08 // |
| 331 | #define RF_BS_IQGEN 0x0F // |
| 332 | |
| 333 | #define RF_MODE1 0x10 // |
| 334 | #define RF_MODE2 0x11 // |
| 335 | |
| 336 | #define RF_RX_AGC_HP 0x12 // |
| 337 | #define RF_TX_AGC 0x13 // |
| 338 | #define RF_BIAS 0x14 // |
| 339 | #define RF_IPA 0x15 // |
| 340 | #define RF_POW_ABILITY 0x17 // |
| 341 | #define RF_MODE_AG 0x18 // |
| 342 | #define rRfChannel 0x18 // RF channel and BW switch |
| 343 | #define RF_CHNLBW 0x18 // RF channel and BW switch |
| 344 | #define RF_TOP 0x19 // |
| 345 | |
| 346 | #define RF_RX_G1 0x1A // |
| 347 | #define RF_RX_G2 0x1B // |
| 348 | |
| 349 | #define RF_RX_BB2 0x1C // |
| 350 | #define RF_RX_BB1 0x1D // |
| 351 | |
| 352 | #define RF_RCK1 0x1E // |
| 353 | #define RF_RCK2 0x1F // |
| 354 | |
| 355 | #define RF_TX_G1 0x20 // |
| 356 | #define RF_TX_G2 0x21 // |
| 357 | #define RF_TX_G3 0x22 // |
| 358 | |
| 359 | #define RF_TX_BB1 0x23 // |
| 360 | |
| 361 | #define RF_T_METER 0x24 // |
| 362 | |
| 363 | #define RF_SYN_G1 0x25 // RF TX Power control |
| 364 | #define RF_SYN_G2 0x26 // RF TX Power control |
| 365 | #define RF_SYN_G3 0x27 // RF TX Power control |
| 366 | #define RF_SYN_G4 0x28 // RF TX Power control |
| 367 | #define RF_SYN_G5 0x29 // RF TX Power control |
| 368 | #define RF_SYN_G6 0x2A // RF TX Power control |
| 369 | #define RF_SYN_G7 0x2B // RF TX Power control |
| 370 | #define RF_SYN_G8 0x2C // RF TX Power control |
| 371 | |
| 372 | #define RF_RCK_OS 0x30 // RF TX PA control |
| 373 | |
| 374 | #define RF_TXPA_G1 0x31 // RF TX PA control |
| 375 | #define RF_TXPA_G2 0x32 // RF TX PA control |
| 376 | #define RF_TXPA_G3 0x33 // RF TX PA control |
| 377 | |
| 378 | // |
| 379 | //Bit Mask |
| 380 | // |
| 381 | // 1. Page1(0x100) |
| 382 | #define bBBResetB 0x100 // Useless now? |
| 383 | #define bGlobalResetB 0x200 |
| 384 | #define bOFDMTxStart 0x4 |
| 385 | #define bCCKTxStart 0x8 |
| 386 | #define bCRC32Debug 0x100 |
| 387 | #define bPMACLoopback 0x10 |
| 388 | #define bTxLSIG 0xffffff |
| 389 | #define bOFDMTxRate 0xf |
| 390 | #define bOFDMTxReserved 0x10 |
| 391 | #define bOFDMTxLength 0x1ffe0 |
| 392 | #define bOFDMTxParity 0x20000 |
| 393 | #define bTxHTSIG1 0xffffff |
| 394 | #define bTxHTMCSRate 0x7f |
| 395 | #define bTxHTBW 0x80 |
| 396 | #define bTxHTLength 0xffff00 |
| 397 | #define bTxHTSIG2 0xffffff |
| 398 | #define bTxHTSmoothing 0x1 |
| 399 | #define bTxHTSounding 0x2 |
| 400 | #define bTxHTReserved 0x4 |
| 401 | #define bTxHTAggreation 0x8 |
| 402 | #define bTxHTSTBC 0x30 |
| 403 | #define bTxHTAdvanceCoding 0x40 |
| 404 | #define bTxHTShortGI 0x80 |
| 405 | #define bTxHTNumberHT_LTF 0x300 |
| 406 | #define bTxHTCRC8 0x3fc00 |
| 407 | #define bCounterReset 0x10000 |
| 408 | #define bNumOfOFDMTx 0xffff |
| 409 | #define bNumOfCCKTx 0xffff0000 |
| 410 | #define bTxIdleInterval 0xffff |
| 411 | #define bOFDMService 0xffff0000 |
| 412 | #define bTxMACHeader 0xffffffff |
| 413 | #define bTxDataInit 0xff |
| 414 | #define bTxHTMode 0x100 |
| 415 | #define bTxDataType 0x30000 |
| 416 | #define bTxRandomSeed 0xffffffff |
| 417 | #define bCCKTxPreamble 0x1 |
| 418 | #define bCCKTxSFD 0xffff0000 |
| 419 | #define bCCKTxSIG 0xff |
| 420 | #define bCCKTxService 0xff00 |
| 421 | #define bCCKLengthExt 0x8000 |
| 422 | #define bCCKTxLength 0xffff0000 |
| 423 | #define bCCKTxCRC16 0xffff |
| 424 | #define bCCKTxStatus 0x1 |
| 425 | #define bOFDMTxStatus 0x2 |
| 426 | |
| 427 | #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) |
| 428 | |
| 429 | // 2. Page8(0x800) |
| 430 | #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD |
| 431 | #define bJapanMode 0x2 |
| 432 | #define bCCKTxSC 0x30 |
| 433 | #define bCCKEn 0x1000000 |
| 434 | #define bOFDMEn 0x2000000 |
| 435 | |
| 436 | #define bOFDMRxADCPhase 0x10000 // Useless now |
| 437 | #define bOFDMTxDACPhase 0x40000 |
| 438 | #define bXATxAGC 0x3f |
| 439 | |
| 440 | #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage |
| 441 | #define bXCTxAGC 0xf000 |
| 442 | #define bXDTxAGC 0xf0000 |
| 443 | |
| 444 | #define bPAStart 0xf0000000 // Useless now |
| 445 | #define bTRStart 0x00f00000 |
| 446 | #define bRFStart 0x0000f000 |
| 447 | #define bBBStart 0x000000f0 |
| 448 | #define bBBCCKStart 0x0000000f |
| 449 | #define bPAEnd 0xf //Reg0x814 |
| 450 | #define bTREnd 0x0f000000 |
| 451 | #define bRFEnd 0x000f0000 |
| 452 | #define bCCAMask 0x000000f0 //T2R |
| 453 | #define bR2RCCAMask 0x00000f00 |
| 454 | #define bHSSI_R2TDelay 0xf8000000 |
| 455 | #define bHSSI_T2RDelay 0xf80000 |
| André Goddard Rosa | bbc9a99 | 2009-11-14 13:09:06 -0200 | [diff] [blame] | 456 | #define bContTxHSSI 0x400 //channel gain at continue Tx |
| Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 457 | #define bIGFromCCK 0x200 |
| 458 | #define bAGCAddress 0x3f |
| 459 | #define bRxHPTx 0x7000 |
| 460 | #define bRxHPT2R 0x38000 |
| 461 | #define bRxHPCCKIni 0xc0000 |
| 462 | #define bAGCTxCode 0xc00000 |
| 463 | #define bAGCRxCode 0x300000 |
| 464 | |
| 465 | #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 |
| 466 | #define b3WireAddressLength 0x400 |
| 467 | |
| 468 | #define b3WireRFPowerDown 0x1 // Useless now |
| 469 | //#define bHWSISelect 0x8 |
| 470 | #define b5GPAPEPolarity 0x40000000 |
| 471 | #define b2GPAPEPolarity 0x80000000 |
| 472 | #define bRFSW_TxDefaultAnt 0x3 |
| 473 | #define bRFSW_TxOptionAnt 0x30 |
| 474 | #define bRFSW_RxDefaultAnt 0x300 |
| 475 | #define bRFSW_RxOptionAnt 0x3000 |
| 476 | #define bRFSI_3WireData 0x1 |
| 477 | #define bRFSI_3WireClock 0x2 |
| 478 | #define bRFSI_3WireLoad 0x4 |
| 479 | #define bRFSI_3WireRW 0x8 |
| 480 | #define bRFSI_3Wire 0xf |
| 481 | |
| 482 | #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW |
| 483 | |
| 484 | #define bRFSI_TRSW 0x20 // Useless now |
| 485 | #define bRFSI_TRSWB 0x40 |
| 486 | #define bRFSI_ANTSW 0x100 |
| 487 | #define bRFSI_ANTSWB 0x200 |
| 488 | #define bRFSI_PAPE 0x400 |
| 489 | #define bRFSI_PAPE5G 0x800 |
| 490 | #define bBandSelect 0x1 |
| 491 | #define bHTSIG2_GI 0x80 |
| 492 | #define bHTSIG2_Smoothing 0x01 |
| 493 | #define bHTSIG2_Sounding 0x02 |
| 494 | #define bHTSIG2_Aggreaton 0x08 |
| 495 | #define bHTSIG2_STBC 0x30 |
| 496 | #define bHTSIG2_AdvCoding 0x40 |
| 497 | #define bHTSIG2_NumOfHTLTF 0x300 |
| 498 | #define bHTSIG2_CRC8 0x3fc |
| 499 | #define bHTSIG1_MCS 0x7f |
| 500 | #define bHTSIG1_BandWidth 0x80 |
| 501 | #define bHTSIG1_HTLength 0xffff |
| 502 | #define bLSIG_Rate 0xf |
| 503 | #define bLSIG_Reserved 0x10 |
| 504 | #define bLSIG_Length 0x1fffe |
| 505 | #define bLSIG_Parity 0x20 |
| 506 | #define bCCKRxPhase 0x4 |
| 507 | #define bLSSIReadAddress 0x7f800000 // T65 RF |
| 508 | #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal |
| 509 | #define bLSSIReadBackData 0xfffff // T65 RF |
| 510 | #define bLSSIReadOKFlag 0x1000 // Useless now |
| 511 | #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz |
| 512 | #define bRegulator0Standby 0x1 |
| 513 | #define bRegulatorPLLStandby 0x2 |
| 514 | #define bRegulator1Standby 0x4 |
| 515 | #define bPLLPowerUp 0x8 |
| 516 | #define bDPLLPowerUp 0x10 |
| 517 | #define bDA10PowerUp 0x20 |
| 518 | #define bAD7PowerUp 0x200 |
| 519 | #define bDA6PowerUp 0x2000 |
| 520 | #define bXtalPowerUp 0x4000 |
| 521 | #define b40MDClkPowerUP 0x8000 |
| 522 | #define bDA6DebugMode 0x20000 |
| 523 | #define bDA6Swing 0x380000 |
| 524 | |
| 525 | #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ |
| 526 | |
| 527 | #define b80MClkDelay 0x18000000 // Useless |
| 528 | #define bAFEWatchDogEnable 0x20000000 |
| 529 | |
| 530 | #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap |
| 531 | #define bXtalCap23 0x3 |
| 532 | #define bXtalCap92x 0x0f000000 |
| 533 | #define bXtalCap 0x0f000000 |
| 534 | |
| 535 | #define bIntDifClkEnable 0x400 // Useless |
| 536 | #define bExtSigClkEnable 0x800 |
| 537 | #define bBandgapMbiasPowerUp 0x10000 |
| 538 | #define bAD11SHGain 0xc0000 |
| 539 | #define bAD11InputRange 0x700000 |
| 540 | #define bAD11OPCurrent 0x3800000 |
| 541 | #define bIPathLoopback 0x4000000 |
| 542 | #define bQPathLoopback 0x8000000 |
| 543 | #define bAFELoopback 0x10000000 |
| 544 | #define bDA10Swing 0x7e0 |
| 545 | #define bDA10Reverse 0x800 |
| 546 | #define bDAClkSource 0x1000 |
| 547 | #define bAD7InputRange 0x6000 |
| 548 | #define bAD7Gain 0x38000 |
| 549 | #define bAD7OutputCMMode 0x40000 |
| 550 | #define bAD7InputCMMode 0x380000 |
| 551 | #define bAD7Current 0xc00000 |
| 552 | #define bRegulatorAdjust 0x7000000 |
| 553 | #define bAD11PowerUpAtTx 0x1 |
| 554 | #define bDA10PSAtTx 0x10 |
| 555 | #define bAD11PowerUpAtRx 0x100 |
| 556 | #define bDA10PSAtRx 0x1000 |
| 557 | #define bCCKRxAGCFormat 0x200 |
| 558 | #define bPSDFFTSamplepPoint 0xc000 |
| 559 | #define bPSDAverageNum 0x3000 |
| 560 | #define bIQPathControl 0xc00 |
| 561 | #define bPSDFreq 0x3ff |
| 562 | #define bPSDAntennaPath 0x30 |
| 563 | #define bPSDIQSwitch 0x40 |
| 564 | #define bPSDRxTrigger 0x400000 |
| 565 | #define bPSDTxTrigger 0x80000000 |
| 566 | #define bPSDSineToneScale 0x7f000000 |
| 567 | #define bPSDReport 0xffff |
| 568 | |
| 569 | // 3. Page9(0x900) |
| 570 | #define bOFDMTxSC 0x30000000 // Useless |
| 571 | #define bCCKTxOn 0x1 |
| 572 | #define bOFDMTxOn 0x2 |
| 573 | #define bDebugPage 0xfff //reset debug page and also HWord, LWord |
| 574 | #define bDebugItem 0xff //reset debug page and LWord |
| 575 | #define bAntL 0x10 |
| 576 | #define bAntNonHT 0x100 |
| 577 | #define bAntHT1 0x1000 |
| 578 | #define bAntHT2 0x10000 |
| 579 | #define bAntHT1S1 0x100000 |
| 580 | #define bAntNonHTS1 0x1000000 |
| 581 | |
| 582 | // 4. PageA(0xA00) |
| 583 | #define bCCKBBMode 0x3 // Useless |
| 584 | #define bCCKTxPowerSaving 0x80 |
| 585 | #define bCCKRxPowerSaving 0x40 |
| 586 | |
| 587 | #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch |
| 588 | |
| 589 | #define bCCKScramble 0x8 // Useless |
| 590 | #define bCCKAntDiversity 0x8000 |
| 591 | #define bCCKCarrierRecovery 0x4000 |
| 592 | #define bCCKTxRate 0x3000 |
| 593 | #define bCCKDCCancel 0x0800 |
| 594 | #define bCCKISICancel 0x0400 |
| 595 | #define bCCKMatchFilter 0x0200 |
| 596 | #define bCCKEqualizer 0x0100 |
| 597 | #define bCCKPreambleDetect 0x800000 |
| 598 | #define bCCKFastFalseCCA 0x400000 |
| 599 | #define bCCKChEstStart 0x300000 |
| 600 | #define bCCKCCACount 0x080000 |
| 601 | #define bCCKcs_lim 0x070000 |
| 602 | #define bCCKBistMode 0x80000000 |
| 603 | #define bCCKCCAMask 0x40000000 |
| 604 | #define bCCKTxDACPhase 0x4 |
| 605 | #define bCCKRxADCPhase 0x20000000 //r_rx_clk |
| 606 | #define bCCKr_cp_mode0 0x0100 |
| 607 | #define bCCKTxDCOffset 0xf0 |
| 608 | #define bCCKRxDCOffset 0xf |
| 609 | #define bCCKCCAMode 0xc000 |
| 610 | #define bCCKFalseCS_lim 0x3f00 |
| 611 | #define bCCKCS_ratio 0xc00000 |
| 612 | #define bCCKCorgBit_sel 0x300000 |
| 613 | #define bCCKPD_lim 0x0f0000 |
| 614 | #define bCCKNewCCA 0x80000000 |
| 615 | #define bCCKRxHPofIG 0x8000 |
| 616 | #define bCCKRxIG 0x7f00 |
| 617 | #define bCCKLNAPolarity 0x800000 |
| 618 | #define bCCKRx1stGain 0x7f0000 |
| 619 | #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity |
| 620 | #define bCCKRxAGCSatLevel 0x1f000000 |
| 621 | #define bCCKRxAGCSatCount 0xe0 |
| 622 | #define bCCKRxRFSettle 0x1f //AGCsamp_dly |
| 623 | #define bCCKFixedRxAGC 0x8000 |
| 624 | //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 |
| 625 | #define bCCKAntennaPolarity 0x2000 |
| 626 | #define bCCKTxFilterType 0x0c00 |
| 627 | #define bCCKRxAGCReportType 0x0300 |
| 628 | #define bCCKRxDAGCEn 0x80000000 |
| 629 | #define bCCKRxDAGCPeriod 0x20000000 |
| 630 | #define bCCKRxDAGCSatLevel 0x1f000000 |
| 631 | #define bCCKTimingRecovery 0x800000 |
| 632 | #define bCCKTxC0 0x3f0000 |
| 633 | #define bCCKTxC1 0x3f000000 |
| 634 | #define bCCKTxC2 0x3f |
| 635 | #define bCCKTxC3 0x3f00 |
| 636 | #define bCCKTxC4 0x3f0000 |
| 637 | #define bCCKTxC5 0x3f000000 |
| 638 | #define bCCKTxC6 0x3f |
| 639 | #define bCCKTxC7 0x3f00 |
| 640 | #define bCCKDebugPort 0xff0000 |
| 641 | #define bCCKDACDebug 0x0f000000 |
| 642 | #define bCCKFalseAlarmEnable 0x8000 |
| 643 | #define bCCKFalseAlarmRead 0x4000 |
| 644 | #define bCCKTRSSI 0x7f |
| 645 | #define bCCKRxAGCReport 0xfe |
| 646 | #define bCCKRxReport_AntSel 0x80000000 |
| 647 | #define bCCKRxReport_MFOff 0x40000000 |
| 648 | #define bCCKRxRxReport_SQLoss 0x20000000 |
| 649 | #define bCCKRxReport_Pktloss 0x10000000 |
| 650 | #define bCCKRxReport_Lockedbit 0x08000000 |
| 651 | #define bCCKRxReport_RateError 0x04000000 |
| 652 | #define bCCKRxReport_RxRate 0x03000000 |
| 653 | #define bCCKRxFACounterLower 0xff |
| 654 | #define bCCKRxFACounterUpper 0xff000000 |
| 655 | #define bCCKRxHPAGCStart 0xe000 |
| 656 | #define bCCKRxHPAGCFinal 0x1c00 |
| 657 | #define bCCKRxFalseAlarmEnable 0x8000 |
| 658 | #define bCCKFACounterFreeze 0x4000 |
| 659 | #define bCCKTxPathSel 0x10000000 |
| 660 | #define bCCKDefaultRxPath 0xc000000 |
| 661 | #define bCCKOptionRxPath 0x3000000 |
| 662 | |
| 663 | // 5. PageC(0xC00) |
| 664 | #define bNumOfSTF 0x3 // Useless |
| 665 | #define bShift_L 0xc0 |
| 666 | #define bGI_TH 0xc |
| 667 | #define bRxPathA 0x1 |
| 668 | #define bRxPathB 0x2 |
| 669 | #define bRxPathC 0x4 |
| 670 | #define bRxPathD 0x8 |
| 671 | #define bTxPathA 0x1 |
| 672 | #define bTxPathB 0x2 |
| 673 | #define bTxPathC 0x4 |
| 674 | #define bTxPathD 0x8 |
| 675 | #define bTRSSIFreq 0x200 |
| 676 | #define bADCBackoff 0x3000 |
| 677 | #define bDFIRBackoff 0xc000 |
| 678 | #define bTRSSILatchPhase 0x10000 |
| 679 | #define bRxIDCOffset 0xff |
| 680 | #define bRxQDCOffset 0xff00 |
| 681 | #define bRxDFIRMode 0x1800000 |
| 682 | #define bRxDCNFType 0xe000000 |
| 683 | #define bRXIQImb_A 0x3ff |
| 684 | #define bRXIQImb_B 0xfc00 |
| 685 | #define bRXIQImb_C 0x3f0000 |
| 686 | #define bRXIQImb_D 0xffc00000 |
| 687 | #define bDC_dc_Notch 0x60000 |
| 688 | #define bRxNBINotch 0x1f000000 |
| 689 | #define bPD_TH 0xf |
| 690 | #define bPD_TH_Opt2 0xc000 |
| 691 | #define bPWED_TH 0x700 |
| 692 | #define bIfMF_Win_L 0x800 |
| 693 | #define bPD_Option 0x1000 |
| 694 | #define bMF_Win_L 0xe000 |
| 695 | #define bBW_Search_L 0x30000 |
| 696 | #define bwin_enh_L 0xc0000 |
| 697 | #define bBW_TH 0x700000 |
| 698 | #define bED_TH2 0x3800000 |
| 699 | #define bBW_option 0x4000000 |
| 700 | #define bRatio_TH 0x18000000 |
| 701 | #define bWindow_L 0xe0000000 |
| 702 | #define bSBD_Option 0x1 |
| 703 | #define bFrame_TH 0x1c |
| 704 | #define bFS_Option 0x60 |
| 705 | #define bDC_Slope_check 0x80 |
| 706 | #define bFGuard_Counter_DC_L 0xe00 |
| 707 | #define bFrame_Weight_Short 0x7000 |
| 708 | #define bSub_Tune 0xe00000 |
| 709 | #define bFrame_DC_Length 0xe000000 |
| 710 | #define bSBD_start_offset 0x30000000 |
| 711 | #define bFrame_TH_2 0x7 |
| 712 | #define bFrame_GI2_TH 0x38 |
| 713 | #define bGI2_Sync_en 0x40 |
| 714 | #define bSarch_Short_Early 0x300 |
| 715 | #define bSarch_Short_Late 0xc00 |
| 716 | #define bSarch_GI2_Late 0x70000 |
| 717 | #define bCFOAntSum 0x1 |
| 718 | #define bCFOAcc 0x2 |
| 719 | #define bCFOStartOffset 0xc |
| 720 | #define bCFOLookBack 0x70 |
| 721 | #define bCFOSumWeight 0x80 |
| 722 | #define bDAGCEnable 0x10000 |
| 723 | #define bTXIQImb_A 0x3ff |
| 724 | #define bTXIQImb_B 0xfc00 |
| 725 | #define bTXIQImb_C 0x3f0000 |
| 726 | #define bTXIQImb_D 0xffc00000 |
| 727 | #define bTxIDCOffset 0xff |
| 728 | #define bTxQDCOffset 0xff00 |
| 729 | #define bTxDFIRMode 0x10000 |
| 730 | #define bTxPesudoNoiseOn 0x4000000 |
| 731 | #define bTxPesudoNoise_A 0xff |
| 732 | #define bTxPesudoNoise_B 0xff00 |
| 733 | #define bTxPesudoNoise_C 0xff0000 |
| 734 | #define bTxPesudoNoise_D 0xff000000 |
| 735 | #define bCCADropOption 0x20000 |
| 736 | #define bCCADropThres 0xfff00000 |
| 737 | #define bEDCCA_H 0xf |
| 738 | #define bEDCCA_L 0xf0 |
| 739 | #define bLambda_ED 0x300 |
| 740 | #define bRxInitialGain 0x7f |
| 741 | #define bRxAntDivEn 0x80 |
| 742 | #define bRxAGCAddressForLNA 0x7f00 |
| 743 | #define bRxHighPowerFlow 0x8000 |
| 744 | #define bRxAGCFreezeThres 0xc0000 |
| 745 | #define bRxFreezeStep_AGC1 0x300000 |
| 746 | #define bRxFreezeStep_AGC2 0xc00000 |
| 747 | #define bRxFreezeStep_AGC3 0x3000000 |
| 748 | #define bRxFreezeStep_AGC0 0xc000000 |
| 749 | #define bRxRssi_Cmp_En 0x10000000 |
| 750 | #define bRxQuickAGCEn 0x20000000 |
| 751 | #define bRxAGCFreezeThresMode 0x40000000 |
| 752 | #define bRxOverFlowCheckType 0x80000000 |
| 753 | #define bRxAGCShift 0x7f |
| 754 | #define bTRSW_Tri_Only 0x80 |
| 755 | #define bPowerThres 0x300 |
| 756 | #define bRxAGCEn 0x1 |
| 757 | #define bRxAGCTogetherEn 0x2 |
| 758 | #define bRxAGCMin 0x4 |
| 759 | #define bRxHP_Ini 0x7 |
| 760 | #define bRxHP_TRLNA 0x70 |
| 761 | #define bRxHP_RSSI 0x700 |
| 762 | #define bRxHP_BBP1 0x7000 |
| 763 | #define bRxHP_BBP2 0x70000 |
| 764 | #define bRxHP_BBP3 0x700000 |
| 765 | #define bRSSI_H 0x7f0000 //the threshold for high power |
| 766 | #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity |
| 767 | #define bRxSettle_TRSW 0x7 |
| 768 | #define bRxSettle_LNA 0x38 |
| 769 | #define bRxSettle_RSSI 0x1c0 |
| 770 | #define bRxSettle_BBP 0xe00 |
| 771 | #define bRxSettle_RxHP 0x7000 |
| 772 | #define bRxSettle_AntSW_RSSI 0x38000 |
| 773 | #define bRxSettle_AntSW 0xc0000 |
| 774 | #define bRxProcessTime_DAGC 0x300000 |
| 775 | #define bRxSettle_HSSI 0x400000 |
| 776 | #define bRxProcessTime_BBPPW 0x800000 |
| 777 | #define bRxAntennaPowerShift 0x3000000 |
| 778 | #define bRSSITableSelect 0xc000000 |
| 779 | #define bRxHP_Final 0x7000000 |
| 780 | #define bRxHTSettle_BBP 0x7 |
| 781 | #define bRxHTSettle_HSSI 0x8 |
| 782 | #define bRxHTSettle_RxHP 0x70 |
| 783 | #define bRxHTSettle_BBPPW 0x80 |
| 784 | #define bRxHTSettle_Idle 0x300 |
| 785 | #define bRxHTSettle_Reserved 0x1c00 |
| 786 | #define bRxHTRxHPEn 0x8000 |
| 787 | #define bRxHTAGCFreezeThres 0x30000 |
| 788 | #define bRxHTAGCTogetherEn 0x40000 |
| 789 | #define bRxHTAGCMin 0x80000 |
| 790 | #define bRxHTAGCEn 0x100000 |
| 791 | #define bRxHTDAGCEn 0x200000 |
| 792 | #define bRxHTRxHP_BBP 0x1c00000 |
| 793 | #define bRxHTRxHP_Final 0xe0000000 |
| 794 | #define bRxPWRatioTH 0x3 |
| 795 | #define bRxPWRatioEn 0x4 |
| 796 | #define bRxMFHold 0x3800 |
| 797 | #define bRxPD_Delay_TH1 0x38 |
| 798 | #define bRxPD_Delay_TH2 0x1c0 |
| 799 | #define bRxPD_DC_COUNT_MAX 0x600 |
| 800 | //#define bRxMF_Hold 0x3800 |
| 801 | #define bRxPD_Delay_TH 0x8000 |
| 802 | #define bRxProcess_Delay 0xf0000 |
| 803 | #define bRxSearchrange_GI2_Early 0x700000 |
| 804 | #define bRxFrame_Guard_Counter_L 0x3800000 |
| 805 | #define bRxSGI_Guard_L 0xc000000 |
| 806 | #define bRxSGI_Search_L 0x30000000 |
| 807 | #define bRxSGI_TH 0xc0000000 |
| 808 | #define bDFSCnt0 0xff |
| 809 | #define bDFSCnt1 0xff00 |
| 810 | #define bDFSFlag 0xf0000 |
| 811 | #define bMFWeightSum 0x300000 |
| 812 | #define bMinIdxTH 0x7f000000 |
| 813 | #define bDAFormat 0x40000 |
| 814 | #define bTxChEmuEnable 0x01000000 |
| 815 | #define bTRSWIsolation_A 0x7f |
| 816 | #define bTRSWIsolation_B 0x7f00 |
| 817 | #define bTRSWIsolation_C 0x7f0000 |
| 818 | #define bTRSWIsolation_D 0x7f000000 |
| 819 | #define bExtLNAGain 0x7c00 |
| 820 | |
| 821 | // 6. PageE(0xE00) |
| 822 | #define bSTBCEn 0x4 // Useless |
| 823 | #define bAntennaMapping 0x10 |
| 824 | #define bNss 0x20 |
| 825 | #define bCFOAntSumD 0x200 |
| 826 | #define bPHYCounterReset 0x8000000 |
| 827 | #define bCFOReportGet 0x4000000 |
| 828 | #define bOFDMContinueTx 0x10000000 |
| 829 | #define bOFDMSingleCarrier 0x20000000 |
| 830 | #define bOFDMSingleTone 0x40000000 |
| 831 | //#define bRxPath1 0x01 |
| 832 | //#define bRxPath2 0x02 |
| 833 | //#define bRxPath3 0x04 |
| 834 | //#define bRxPath4 0x08 |
| 835 | //#define bTxPath1 0x10 |
| 836 | //#define bTxPath2 0x20 |
| 837 | #define bHTDetect 0x100 |
| 838 | #define bCFOEn 0x10000 |
| 839 | #define bCFOValue 0xfff00000 |
| 840 | #define bSigTone_Re 0x3f |
| 841 | #define bSigTone_Im 0x7f00 |
| 842 | #define bCounter_CCA 0xffff |
| 843 | #define bCounter_ParityFail 0xffff0000 |
| 844 | #define bCounter_RateIllegal 0xffff |
| 845 | #define bCounter_CRC8Fail 0xffff0000 |
| 846 | #define bCounter_MCSNoSupport 0xffff |
| 847 | #define bCounter_FastSync 0xffff |
| 848 | #define bShortCFO 0xfff |
| 849 | #define bShortCFOTLength 12 //total |
| 850 | #define bShortCFOFLength 11 //fraction |
| 851 | #define bLongCFO 0x7ff |
| 852 | #define bLongCFOTLength 11 |
| 853 | #define bLongCFOFLength 11 |
| 854 | #define bTailCFO 0x1fff |
| 855 | #define bTailCFOTLength 13 |
| 856 | #define bTailCFOFLength 12 |
| 857 | #define bmax_en_pwdB 0xffff |
| 858 | #define bCC_power_dB 0xffff0000 |
| 859 | #define bnoise_pwdB 0xffff |
| 860 | #define bPowerMeasTLength 10 |
| 861 | #define bPowerMeasFLength 3 |
| 862 | #define bRx_HT_BW 0x1 |
| 863 | #define bRxSC 0x6 |
| 864 | #define bRx_HT 0x8 |
| 865 | #define bNB_intf_det_on 0x1 |
| 866 | #define bIntf_win_len_cfg 0x30 |
| 867 | #define bNB_Intf_TH_cfg 0x1c0 |
| 868 | #define bRFGain 0x3f |
| 869 | #define bTableSel 0x40 |
| 870 | #define bTRSW 0x80 |
| 871 | #define bRxSNR_A 0xff |
| 872 | #define bRxSNR_B 0xff00 |
| 873 | #define bRxSNR_C 0xff0000 |
| 874 | #define bRxSNR_D 0xff000000 |
| 875 | #define bSNREVMTLength 8 |
| 876 | #define bSNREVMFLength 1 |
| 877 | #define bCSI1st 0xff |
| 878 | #define bCSI2nd 0xff00 |
| 879 | #define bRxEVM1st 0xff0000 |
| 880 | #define bRxEVM2nd 0xff000000 |
| 881 | #define bSIGEVM 0xff |
| 882 | #define bPWDB 0xff00 |
| 883 | #define bSGIEN 0x10000 |
| 884 | |
| 885 | #define bSFactorQAM1 0xf // Useless |
| 886 | #define bSFactorQAM2 0xf0 |
| 887 | #define bSFactorQAM3 0xf00 |
| 888 | #define bSFactorQAM4 0xf000 |
| 889 | #define bSFactorQAM5 0xf0000 |
| 890 | #define bSFactorQAM6 0xf0000 |
| 891 | #define bSFactorQAM7 0xf00000 |
| 892 | #define bSFactorQAM8 0xf000000 |
| 893 | #define bSFactorQAM9 0xf0000000 |
| 894 | #define bCSIScheme 0x100000 |
| 895 | |
| 896 | #define bNoiseLvlTopSet 0x3 // Useless |
| 897 | #define bChSmooth 0x4 |
| 898 | #define bChSmoothCfg1 0x38 |
| 899 | #define bChSmoothCfg2 0x1c0 |
| 900 | #define bChSmoothCfg3 0xe00 |
| 901 | #define bChSmoothCfg4 0x7000 |
| 902 | #define bMRCMode 0x800000 |
| 903 | #define bTHEVMCfg 0x7000000 |
| 904 | |
| 905 | #define bLoopFitType 0x1 // Useless |
| 906 | #define bUpdCFO 0x40 |
| 907 | #define bUpdCFOOffData 0x80 |
| 908 | #define bAdvUpdCFO 0x100 |
| 909 | #define bAdvTimeCtrl 0x800 |
| 910 | #define bUpdClko 0x1000 |
| 911 | #define bFC 0x6000 |
| 912 | #define bTrackingMode 0x8000 |
| 913 | #define bPhCmpEnable 0x10000 |
| 914 | #define bUpdClkoLTF 0x20000 |
| 915 | #define bComChCFO 0x40000 |
| 916 | #define bCSIEstiMode 0x80000 |
| 917 | #define bAdvUpdEqz 0x100000 |
| 918 | #define bUChCfg 0x7000000 |
| 919 | #define bUpdEqz 0x8000000 |
| 920 | |
| 921 | #define bTxAGCRate18_06 0x7f7f7f7f // Useless |
| 922 | #define bTxAGCRate54_24 0x7f7f7f7f |
| 923 | #define bTxAGCRateMCS32 0x7f |
| 924 | #define bTxAGCRateCCK 0x7f00 |
| 925 | #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f |
| 926 | #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f |
| 927 | #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f |
| 928 | #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f |
| 929 | |
| 930 | //Rx Pseduo noise |
| 931 | #define bRxPesudoNoiseOn 0x20000000 // Useless |
| 932 | #define bRxPesudoNoise_A 0xff |
| 933 | #define bRxPesudoNoise_B 0xff00 |
| 934 | #define bRxPesudoNoise_C 0xff0000 |
| 935 | #define bRxPesudoNoise_D 0xff000000 |
| 936 | #define bPesudoNoiseState_A 0xffff |
| 937 | #define bPesudoNoiseState_B 0xffff0000 |
| 938 | #define bPesudoNoiseState_C 0xffff |
| 939 | #define bPesudoNoiseState_D 0xffff0000 |
| 940 | |
| 941 | //7. RF Register |
| 942 | //Zebra1 |
| 943 | #define bZebra1_HSSIEnable 0x8 // Useless |
| 944 | #define bZebra1_TRxControl 0xc00 |
| 945 | #define bZebra1_TRxGainSetting 0x07f |
| 946 | #define bZebra1_RxCorner 0xc00 |
| 947 | #define bZebra1_TxChargePump 0x38 |
| 948 | #define bZebra1_RxChargePump 0x7 |
| 949 | #define bZebra1_ChannelNum 0xf80 |
| 950 | #define bZebra1_TxLPFBW 0x400 |
| 951 | #define bZebra1_RxLPFBW 0x600 |
| 952 | |
| 953 | //Zebra4 |
| 954 | #define bRTL8256RegModeCtrl1 0x100 // Useless |
| 955 | #define bRTL8256RegModeCtrl0 0x40 |
| 956 | #define bRTL8256_TxLPFBW 0x18 |
| 957 | #define bRTL8256_RxLPFBW 0x600 |
| 958 | |
| 959 | //RTL8258 |
| 960 | #define bRTL8258_TxLPFBW 0xc // Useless |
| 961 | #define bRTL8258_RxLPFBW 0xc00 |
| 962 | #define bRTL8258_RSSILPFBW 0xc0 |
| 963 | |
| 964 | |
| 965 | // |
| 966 | // Other Definition |
| 967 | // |
| 968 | |
| 969 | //byte endable for sb_write |
| 970 | #define bByte0 0x1 // Useless |
| 971 | #define bByte1 0x2 |
| 972 | #define bByte2 0x4 |
| 973 | #define bByte3 0x8 |
| 974 | #define bWord0 0x3 |
| 975 | #define bWord1 0xc |
| 976 | #define bDWord 0xf |
| 977 | |
| 978 | //for PutRegsetting & GetRegSetting BitMask |
| 979 | #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f |
| 980 | #define bMaskByte1 0xff00 |
| 981 | #define bMaskByte2 0xff0000 |
| 982 | #define bMaskByte3 0xff000000 |
| 983 | #define bMaskHWord 0xffff0000 |
| 984 | #define bMaskLWord 0x0000ffff |
| 985 | #define bMaskDWord 0xffffffff |
| 986 | |
| 987 | //for PutRFRegsetting & GetRFRegSetting BitMask |
| 988 | #define bMask12Bits 0xfffff // RF Reg mask bits |
| 989 | #define bMask20Bits 0xfffff // RF Reg mask bits T65 RF |
| 990 | #define bRFRegOffsetMask 0xfffff |
| 991 | |
| 992 | #define bEnable 0x1 // Useless |
| 993 | #define bDisable 0x0 |
| 994 | |
| 995 | #define LeftAntenna 0x0 // Useless |
| 996 | #define RightAntenna 0x1 |
| 997 | |
| 998 | #define tCheckTxStatus 500 //500ms // Useless |
| 999 | #define tUpdateRxCounter 100 //100ms |
| 1000 | |
| 1001 | #define rateCCK 0 // Useless |
| 1002 | #define rateOFDM 1 |
| 1003 | #define rateHT 2 |
| 1004 | |
| 1005 | //define Register-End |
| 1006 | #define bPMAC_End 0x1ff // Useless |
| 1007 | #define bFPGAPHY0_End 0x8ff |
| 1008 | #define bFPGAPHY1_End 0x9ff |
| 1009 | #define bCCKPHY0_End 0xaff |
| 1010 | #define bOFDMPHY0_End 0xcff |
| 1011 | #define bOFDMPHY1_End 0xdff |
| 1012 | |
| 1013 | //define max debug item in each debug page |
| 1014 | //#define bMaxItem_FPGA_PHY0 0x9 |
| 1015 | //#define bMaxItem_FPGA_PHY1 0x3 |
| 1016 | //#define bMaxItem_PHY_11B 0x16 |
| 1017 | //#define bMaxItem_OFDM_PHY0 0x29 |
| 1018 | //#define bMaxItem_OFDM_PHY1 0x0 |
| 1019 | |
| 1020 | #define bPMACControl 0x0 // Useless |
| 1021 | #define bWMACControl 0x1 |
| 1022 | #define bWNICControl 0x2 |
| 1023 | |
| 1024 | #define PathA 0x0 // Useless |
| 1025 | #define PathB 0x1 |
| 1026 | #define PathC 0x2 |
| 1027 | #define PathD 0x3 |
| 1028 | |
| 1029 | /*--------------------------Define Parameters-------------------------------*/ |
| 1030 | |
| 1031 | |
| 1032 | #endif //__INC_HAL8192SPHYREG_H |
| 1033 | |