Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci GPIO Support |
| 3 | * |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 4 | * Copyright (c) 2006-2007 David Brownell |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/irq.h> |
| 21 | #include <linux/bitops.h> |
| 22 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 23 | #include <mach/cputype.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 24 | #include <mach/irqs.h> |
| 25 | #include <mach/hardware.h> |
| 26 | #include <mach/gpio.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 27 | |
| 28 | #include <asm/mach/irq.h> |
| 29 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 30 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 31 | static DEFINE_SPINLOCK(gpio_lock); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 32 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 33 | struct davinci_gpio { |
| 34 | struct gpio_chip chip; |
| 35 | struct gpio_controller *__iomem regs; |
| 36 | }; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 37 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 38 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 39 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 40 | static unsigned __initdata ngpio; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 41 | |
| 42 | /* create a non-inlined version */ |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 43 | static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 44 | { |
| 45 | return __gpio_to_controller(gpio); |
| 46 | } |
| 47 | |
Kevin Hilman | dc75602 | 2009-05-11 11:04:53 -0700 | [diff] [blame^] | 48 | static int __init davinci_gpio_irq_setup(void); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 49 | |
| 50 | /*--------------------------------------------------------------------------*/ |
| 51 | |
| 52 | /* |
| 53 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
| 54 | * needed, and enable the GPIO clock. |
| 55 | */ |
| 56 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 57 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 58 | { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 59 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
| 60 | struct gpio_controller *__iomem g = d->regs; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 61 | u32 temp; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 62 | |
| 63 | spin_lock(&gpio_lock); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 64 | temp = __raw_readl(&g->dir); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 65 | temp |= (1 << offset); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 66 | __raw_writel(temp, &g->dir); |
| 67 | spin_unlock(&gpio_lock); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 68 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 69 | return 0; |
| 70 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 71 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 72 | /* |
| 73 | * Read the pin's value (works even if it's set up as output); |
| 74 | * returns zero/nonzero. |
| 75 | * |
| 76 | * Note that changes are synched to the GPIO clock, so reading values back |
| 77 | * right after you've set them may give old values. |
| 78 | */ |
| 79 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 80 | { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 81 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
| 82 | struct gpio_controller *__iomem g = d->regs; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 83 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 84 | return (1 << offset) & __raw_readl(&g->in_data); |
| 85 | } |
| 86 | |
| 87 | static int |
| 88 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
| 89 | { |
| 90 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
| 91 | struct gpio_controller *__iomem g = d->regs; |
| 92 | u32 temp; |
| 93 | u32 mask = 1 << offset; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 94 | |
| 95 | spin_lock(&gpio_lock); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 96 | temp = __raw_readl(&g->dir); |
| 97 | temp &= ~mask; |
| 98 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); |
| 99 | __raw_writel(temp, &g->dir); |
| 100 | spin_unlock(&gpio_lock); |
| 101 | return 0; |
| 102 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 103 | |
| 104 | /* |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 105 | * Assuming the pin is muxed as a gpio output, set its output value. |
| 106 | */ |
| 107 | static void |
| 108 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 109 | { |
| 110 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
| 111 | struct gpio_controller *__iomem g = d->regs; |
| 112 | |
| 113 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
| 114 | } |
| 115 | |
| 116 | static int __init davinci_gpio_setup(void) |
| 117 | { |
| 118 | int i, base; |
| 119 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 120 | /* The gpio banks conceptually expose a segmented bitmap, |
| 121 | * and "ngpio" is one more than the largest zero-based |
| 122 | * bit index that's valid. |
| 123 | */ |
| 124 | if (cpu_is_davinci_dm355()) { /* or dm335() */ |
| 125 | ngpio = 104; |
| 126 | } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ |
| 127 | ngpio = 71; |
| 128 | } else if (cpu_is_davinci_dm646x()) { |
| 129 | /* NOTE: each bank has several "reserved" bits, |
| 130 | * unusable as GPIOs. Only 33 of the GPIO numbers |
| 131 | * are usable, and we're not rejecting the others. |
| 132 | */ |
| 133 | ngpio = 43; |
| 134 | } else { |
| 135 | /* if cpu_is_davinci_dm643x() ngpio = 111 */ |
| 136 | pr_err("GPIO setup: how many GPIOs?\n"); |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | |
| 140 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) |
| 141 | ngpio = DAVINCI_N_GPIO; |
| 142 | |
| 143 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 144 | chips[i].chip.label = "DaVinci"; |
| 145 | |
| 146 | chips[i].chip.direction_input = davinci_direction_in; |
| 147 | chips[i].chip.get = davinci_gpio_get; |
| 148 | chips[i].chip.direction_output = davinci_direction_out; |
| 149 | chips[i].chip.set = davinci_gpio_set; |
| 150 | |
| 151 | chips[i].chip.base = base; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 152 | chips[i].chip.ngpio = ngpio - base; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 153 | if (chips[i].chip.ngpio > 32) |
| 154 | chips[i].chip.ngpio = 32; |
| 155 | |
| 156 | chips[i].regs = gpio2controller(base); |
| 157 | |
| 158 | gpiochip_add(&chips[i].chip); |
| 159 | } |
| 160 | |
Kevin Hilman | dc75602 | 2009-05-11 11:04:53 -0700 | [diff] [blame^] | 161 | davinci_gpio_irq_setup(); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 162 | return 0; |
| 163 | } |
| 164 | pure_initcall(davinci_gpio_setup); |
| 165 | |
| 166 | /*--------------------------------------------------------------------------*/ |
| 167 | /* |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 168 | * We expect irqs will normally be set up as input pins, but they can also be |
| 169 | * used as output pins ... which is convenient for testing. |
| 170 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 171 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
| 172 | * to their GPIOBNK0 irq, with a bit less overhead but less flexibility |
| 173 | * on triggering (e.g. no edge options). We don't try to use those. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 174 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 175 | * All those INTC hookups (direct, plus several IRQ banks) can also |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 176 | * serve as EDMA event triggers. |
| 177 | */ |
| 178 | |
| 179 | static void gpio_irq_disable(unsigned irq) |
| 180 | { |
| 181 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 182 | u32 mask = __gpio_mask(irq_to_gpio(irq)); |
| 183 | |
| 184 | __raw_writel(mask, &g->clr_falling); |
| 185 | __raw_writel(mask, &g->clr_rising); |
| 186 | } |
| 187 | |
| 188 | static void gpio_irq_enable(unsigned irq) |
| 189 | { |
| 190 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 191 | u32 mask = __gpio_mask(irq_to_gpio(irq)); |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 192 | unsigned status = irq_desc[irq].status; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 193 | |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 194 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 195 | if (!status) |
| 196 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 197 | |
| 198 | if (status & IRQ_TYPE_EDGE_FALLING) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 199 | __raw_writel(mask, &g->set_falling); |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 200 | if (status & IRQ_TYPE_EDGE_RISING) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 201 | __raw_writel(mask, &g->set_rising); |
| 202 | } |
| 203 | |
| 204 | static int gpio_irq_type(unsigned irq, unsigned trigger) |
| 205 | { |
| 206 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 207 | u32 mask = __gpio_mask(irq_to_gpio(irq)); |
| 208 | |
| 209 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 210 | return -EINVAL; |
| 211 | |
| 212 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; |
| 213 | irq_desc[irq].status |= trigger; |
| 214 | |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 215 | /* don't enable the IRQ if it's currently disabled */ |
| 216 | if (irq_desc[irq].depth == 0) { |
| 217 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
| 218 | ? &g->set_falling : &g->clr_falling); |
| 219 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
| 220 | ? &g->set_rising : &g->clr_rising); |
| 221 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 222 | return 0; |
| 223 | } |
| 224 | |
| 225 | static struct irq_chip gpio_irqchip = { |
| 226 | .name = "GPIO", |
| 227 | .enable = gpio_irq_enable, |
| 228 | .disable = gpio_irq_disable, |
| 229 | .set_type = gpio_irq_type, |
| 230 | }; |
| 231 | |
| 232 | static void |
| 233 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 234 | { |
| 235 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 236 | u32 mask = 0xffff; |
| 237 | |
| 238 | /* we only care about one bank */ |
| 239 | if (irq & 1) |
| 240 | mask <<= 16; |
| 241 | |
| 242 | /* temporarily mask (level sensitive) parent IRQ */ |
Kevin Hilman | dc75602 | 2009-05-11 11:04:53 -0700 | [diff] [blame^] | 243 | desc->chip->mask(irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 244 | desc->chip->ack(irq); |
| 245 | while (1) { |
| 246 | u32 status; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 247 | int n; |
| 248 | int res; |
| 249 | |
| 250 | /* ack any irqs */ |
| 251 | status = __raw_readl(&g->intstat) & mask; |
| 252 | if (!status) |
| 253 | break; |
| 254 | __raw_writel(status, &g->intstat); |
| 255 | if (irq & 1) |
| 256 | status >>= 16; |
| 257 | |
| 258 | /* now demux them to the right lowlevel handler */ |
| 259 | n = (int)get_irq_data(irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 260 | while (status) { |
| 261 | res = ffs(status); |
| 262 | n += res; |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame] | 263 | generic_handle_irq(n - 1); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 264 | status >>= res; |
| 265 | } |
| 266 | } |
| 267 | desc->chip->unmask(irq); |
| 268 | /* now it may re-trigger */ |
| 269 | } |
| 270 | |
| 271 | /* |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 272 | * NOTE: for suspend/resume, probably best to make a platform_device with |
| 273 | * suspend_late/resume_resume calls hooking into results of the set_wake() |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 274 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
| 275 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 276 | * (dm6446) can be set appropriately for GPIOV33 pins. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 277 | */ |
| 278 | |
| 279 | static int __init davinci_gpio_irq_setup(void) |
| 280 | { |
| 281 | unsigned gpio, irq, bank; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 282 | unsigned bank_irq; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 283 | struct clk *clk; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 284 | u32 binten = 0; |
| 285 | |
| 286 | if (cpu_is_davinci_dm355()) { /* or dm335() */ |
| 287 | bank_irq = IRQ_DM355_GPIOBNK0; |
| 288 | } else if (cpu_is_davinci_dm644x()) { |
| 289 | bank_irq = IRQ_GPIOBNK0; |
| 290 | } else if (cpu_is_davinci_dm646x()) { |
| 291 | bank_irq = IRQ_DM646X_GPIOBNK0; |
| 292 | } else { |
| 293 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
| 294 | return -EINVAL; |
| 295 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 296 | |
| 297 | clk = clk_get(NULL, "gpio"); |
| 298 | if (IS_ERR(clk)) { |
| 299 | printk(KERN_ERR "Error %ld getting gpio clock?\n", |
| 300 | PTR_ERR(clk)); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 301 | return PTR_ERR(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 302 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 303 | clk_enable(clk); |
| 304 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 305 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
| 306 | gpio < ngpio; |
| 307 | bank++, bank_irq++) { |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 308 | struct gpio_controller *__iomem g = gpio2controller(gpio); |
| 309 | unsigned i; |
| 310 | |
| 311 | __raw_writel(~0, &g->clr_falling); |
| 312 | __raw_writel(~0, &g->clr_rising); |
| 313 | |
| 314 | /* set up all irqs in this bank */ |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 315 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
| 316 | set_irq_chip_data(bank_irq, g); |
| 317 | set_irq_data(bank_irq, (void *)irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 318 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 319 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 320 | set_irq_chip(irq, &gpio_irqchip); |
| 321 | set_irq_chip_data(irq, g); |
| 322 | set_irq_handler(irq, handle_simple_irq); |
| 323 | set_irq_flags(irq, IRQF_VALID); |
| 324 | } |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 325 | |
| 326 | binten |= BIT(bank); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
| 330 | * bits be set/cleared dynamically. |
| 331 | */ |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 332 | __raw_writel(binten, (void *__iomem) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 333 | IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); |
| 334 | |
| 335 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); |
| 336 | |
| 337 | return 0; |
| 338 | } |