| Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2013 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #define NV04_PFB_BOOT_0 0x00100000 |
| 26 | # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 |
| 27 | # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 |
| 28 | # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 |
| 29 | # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 |
| 30 | # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 |
| 31 | # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 |
| 32 | # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 |
| 33 | # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 |
| 34 | # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 |
| 35 | # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 |
| 36 | # define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 |
| 37 | # define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 |
| 38 | # define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 |
| 39 | # define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 |
| 40 | # define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 |
| 41 | |
| 42 | #include "priv.h" |
| 43 | |
| 44 | static int |
| 45 | nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, |
| 46 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 47 | struct nouveau_object **pobject) |
| 48 | { |
| 49 | struct nouveau_fb *pfb = nouveau_fb(parent); |
| 50 | struct nouveau_ram *ram; |
| 51 | u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); |
| 52 | int ret; |
| 53 | |
| 54 | ret = nouveau_ram_create(parent, engine, oclass, &ram); |
| 55 | *pobject = nv_object(ram); |
| 56 | if (ret) |
| 57 | return ret; |
| 58 | |
| 59 | if (boot0 & 0x00000100) { |
| 60 | ram->size = ((boot0 >> 12) & 0xf) * 2 + 2; |
| 61 | ram->size *= 1024 * 1024; |
| 62 | } else { |
| 63 | switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { |
| 64 | case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: |
| 65 | ram->size = 32 * 1024 * 1024; |
| 66 | break; |
| 67 | case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: |
| 68 | ram->size = 16 * 1024 * 1024; |
| 69 | break; |
| 70 | case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: |
| 71 | ram->size = 8 * 1024 * 1024; |
| 72 | break; |
| 73 | case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: |
| 74 | ram->size = 4 * 1024 * 1024; |
| 75 | break; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | if ((boot0 & 0x00000038) <= 0x10) |
| 80 | ram->type = NV_MEM_TYPE_SGRAM; |
| 81 | else |
| 82 | ram->type = NV_MEM_TYPE_SDRAM; |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | struct nouveau_oclass |
| 87 | nv04_ram_oclass = { |
| 88 | .handle = 0, |
| 89 | .ofuncs = &(struct nouveau_ofuncs) { |
| 90 | .ctor = nv04_ram_create, |
| 91 | .dtor = _nouveau_ram_dtor, |
| 92 | .init = _nouveau_ram_init, |
| 93 | .fini = _nouveau_ram_fini, |
| 94 | } |
| 95 | }; |