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Catalin Marinas9cce7a42012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable-hwdef.h>
27#include <asm/pgtable.h>
28
29#include "proc-macros.S"
30
Catalin Marinas35a86972014-04-02 17:55:40 +010031#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
Catalin Marinas9cce7a42012-03-05 11:49:28 +000033#else
Catalin Marinas35a86972014-04-02 17:55:40 +010034#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
Catalin Marinas9cce7a42012-03-05 11:49:28 +000035#endif
36
Catalin Marinas35a86972014-04-02 17:55:40 +010037#ifdef CONFIG_SMP
38#define TCR_SMP_FLAGS TCR_SHARED
39#else
40#define TCR_SMP_FLAGS 0
41#endif
42
43/* PTWs cacheable, inner/outer WBWA */
44#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
45
Catalin Marinas9cce7a42012-03-05 11:49:28 +000046#define MAIR(attr, mt) ((attr) << ((mt) * 8))
47
48/*
49 * cpu_cache_off()
50 *
51 * Turn the CPU D-cache off.
52 */
53ENTRY(cpu_cache_off)
54 mrs x0, sctlr_el1
55 bic x0, x0, #1 << 2 // clear SCTLR.C
56 msr sctlr_el1, x0
57 isb
58 ret
59ENDPROC(cpu_cache_off)
60
61/*
62 * cpu_reset(loc)
63 *
64 * Perform a soft reset of the system. Put the CPU into the same state
65 * as it would be if it had been reset, and branch to what would be the
66 * reset vector. It must be executed with the flat identity mapping.
67 *
68 * - loc - location to jump to for soft reset
69 */
70 .align 5
71ENTRY(cpu_reset)
72 mrs x1, sctlr_el1
73 bic x1, x1, #1
74 msr sctlr_el1, x1 // disable the MMU
75 isb
76 ret x0
77ENDPROC(cpu_reset)
78
Arun Chandran5e051532014-08-18 10:06:58 +010079ENTRY(cpu_soft_restart)
80 /* Save address of cpu_reset() and reset address */
81 mov x19, x0
82 mov x20, x1
83
84 /* Turn D-cache off */
85 bl cpu_cache_off
86
87 /* Push out all dirty data, and ensure cache is empty */
88 bl flush_cache_all
89
90 mov x0, x20
91 ret x19
92ENDPROC(cpu_soft_restart)
93
Catalin Marinas9cce7a42012-03-05 11:49:28 +000094/*
95 * cpu_do_idle()
96 *
97 * Idle the processor (wait for interrupt).
98 */
99ENTRY(cpu_do_idle)
100 dsb sy // WFI may enter a low-power mode
101 wfi
102 ret
103ENDPROC(cpu_do_idle)
104
Lorenzo Pieralisiaf3cfdb2015-01-26 18:33:44 +0000105#ifdef CONFIG_CPU_PM
Lorenzo Pieralisi6732bc62013-07-17 10:14:45 +0100106/**
107 * cpu_do_suspend - save CPU registers context
108 *
109 * x0: virtual address of context pointer
110 */
111ENTRY(cpu_do_suspend)
112 mrs x2, tpidr_el0
113 mrs x3, tpidrro_el0
114 mrs x4, contextidr_el1
115 mrs x5, mair_el1
116 mrs x6, cpacr_el1
117 mrs x7, ttbr1_el1
118 mrs x8, tcr_el1
119 mrs x9, vbar_el1
120 mrs x10, mdscr_el1
121 mrs x11, oslsr_el1
122 mrs x12, sctlr_el1
123 stp x2, x3, [x0]
124 stp x4, x5, [x0, #16]
125 stp x6, x7, [x0, #32]
126 stp x8, x9, [x0, #48]
127 stp x10, x11, [x0, #64]
128 str x12, [x0, #80]
129 ret
130ENDPROC(cpu_do_suspend)
131
132/**
133 * cpu_do_resume - restore CPU register context
134 *
135 * x0: Physical address of context pointer
136 * x1: ttbr0_el1 to be restored
137 *
138 * Returns:
139 * sctlr_el1 value in x0
140 */
141ENTRY(cpu_do_resume)
142 /*
143 * Invalidate local tlb entries before turning on MMU
144 */
145 tlbi vmalle1
146 ldp x2, x3, [x0]
147 ldp x4, x5, [x0, #16]
148 ldp x6, x7, [x0, #32]
149 ldp x8, x9, [x0, #48]
150 ldp x10, x11, [x0, #64]
151 ldr x12, [x0, #80]
152 msr tpidr_el0, x2
153 msr tpidrro_el0, x3
154 msr contextidr_el1, x4
155 msr mair_el1, x5
156 msr cpacr_el1, x6
157 msr ttbr0_el1, x1
158 msr ttbr1_el1, x7
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000159 tcr_set_idmap_t0sz x8, x7
Lorenzo Pieralisi6732bc62013-07-17 10:14:45 +0100160 msr tcr_el1, x8
161 msr vbar_el1, x9
162 msr mdscr_el1, x10
163 /*
164 * Restore oslsr_el1 by writing oslar_el1
165 */
166 ubfx x11, x11, #1, #1
167 msr oslar_el1, x11
168 mov x0, x12
169 dsb nsh // Make sure local tlb invalidation completed
170 isb
171 ret
172ENDPROC(cpu_do_resume)
173#endif
174
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000175/*
Jingoo Han812944e2014-01-27 07:19:32 +0000176 * cpu_do_switch_mm(pgd_phys, tsk)
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000177 *
178 * Set the translation table base pointer to be pgd_phys.
179 *
180 * - pgd_phys - physical address of new TTB
181 */
182ENTRY(cpu_do_switch_mm)
183 mmid w1, x1 // get mm->context.id
184 bfi x0, x1, #48, #16 // set the ASID
185 msr ttbr0_el1, x0 // set TTBR0
186 isb
187 ret
188ENDPROC(cpu_do_switch_mm)
189
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000190 .section ".text.init", #alloc, #execinstr
191
192/*
193 * __cpu_setup
194 *
195 * Initialise the processor for turning the MMU on. Return in x0 the
196 * value of the SCTLR_EL1 register.
197 */
198ENTRY(__cpu_setup)
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000199 ic iallu // I+BTB cache invalidate
Mark Rutland3cea71b2013-12-02 16:11:00 +0000200 tlbi vmalle1is // invalidate I + D TLBs
Will Deacondc60b772014-05-02 16:24:15 +0100201 dsb ish
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000202
203 mov x0, #3 << 20
204 msr cpacr_el1, x0 // Enable FP/ASIMD
Will Deacon9c413e22013-05-08 17:01:12 +0100205 msr mdscr_el1, xzr // Reset mdscr_el1
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000206 /*
207 * Memory region attributes for LPAE:
208 *
209 * n = AttrIndx[2:0]
210 * n MAIR
211 * DEVICE_nGnRnE 000 00000000
212 * DEVICE_nGnRE 001 00000100
213 * DEVICE_GRE 010 00001100
214 * NORMAL_NC 011 01000100
215 * NORMAL 100 11111111
216 */
217 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
218 MAIR(0x04, MT_DEVICE_nGnRE) | \
219 MAIR(0x0c, MT_DEVICE_GRE) | \
220 MAIR(0x44, MT_NORMAL_NC) | \
221 MAIR(0xff, MT_NORMAL)
222 msr mair_el1, x5
223 /*
224 * Prepare SCTLR
225 */
226 adr x5, crval
227 ldp w5, w6, [x5]
228 mrs x0, sctlr_el1
229 bic x0, x0, x5 // clear bits
230 orr x0, x0, x6 // set bits
231 /*
232 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
233 * both user and kernel.
234 */
Catalin Marinas35a86972014-04-02 17:55:40 +0100235 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
236 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
Ard Biesheuveldd006da2015-03-19 16:42:27 +0000237 tcr_set_idmap_t0sz x10, x9
238
Radha Mohan Chintakuntla87366d82014-03-07 08:49:25 +0000239 /*
240 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
241 * TCR_EL1.
242 */
243 mrs x9, ID_AA64MMFR0_EL1
244 bfi x10, x9, #32, #3
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000245 msr tcr_el1, x10
246 ret // return to head.S
247ENDPROC(__cpu_setup)
248
249 /*
Suzuki K. Poulose9f71ac92014-12-17 15:50:21 +0000250 * We set the desired value explicitly, including those of the
251 * reserved bits. The values of bits EE & E0E were set early in
252 * el2_setup, which are left untouched below.
253 *
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000254 * n n T
255 * U E WT T UD US IHBS
256 * CE0 XWHW CZ ME TEEA S
257 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
Suzuki K. Poulose9f71ac92014-12-17 15:50:21 +0000258 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
259 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000260 */
261 .type crval, #object
262crval:
Suzuki K. Poulose9f71ac92014-12-17 15:50:21 +0000263 .word 0xfcffffff // clear
264 .word 0x34d5d91d // set