Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on |
| 3 | * AVR32 systems.) |
| 4 | * |
| 5 | * Copyright (C) 2007 Atmel Corporation |
Viresh Kumar | aecb7b6 | 2011-05-24 14:04:09 +0530 | [diff] [blame] | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | #ifndef DW_DMAC_H |
| 13 | #define DW_DMAC_H |
| 14 | |
| 15 | #include <linux/dmaengine.h> |
| 16 | |
| 17 | /** |
| 18 | * struct dw_dma_platform_data - Controller configuration parameters |
| 19 | * @nr_channels: Number of channels supported by hardware (max 8) |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 20 | * @is_private: The device channels should be marked as private and not for |
| 21 | * by the general purpose DMA channel allocator. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 22 | */ |
| 23 | struct dw_dma_platform_data { |
| 24 | unsigned int nr_channels; |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 25 | bool is_private; |
Viresh Kumar | b0c3130 | 2011-03-03 15:47:21 +0530 | [diff] [blame] | 26 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ |
| 27 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ |
| 28 | unsigned char chan_allocation_order; |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 29 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ |
| 30 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ |
| 31 | unsigned char chan_priority; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 32 | }; |
| 33 | |
| 34 | /** |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 35 | * enum dw_dma_slave_width - DMA slave register access width. |
| 36 | * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses |
| 37 | * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses |
| 38 | * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses |
| 39 | */ |
| 40 | enum dw_dma_slave_width { |
| 41 | DW_DMA_SLAVE_WIDTH_8BIT, |
| 42 | DW_DMA_SLAVE_WIDTH_16BIT, |
| 43 | DW_DMA_SLAVE_WIDTH_32BIT, |
| 44 | }; |
| 45 | |
Viresh KUMAR | ee66509 | 2011-03-04 15:42:51 +0530 | [diff] [blame] | 46 | /* bursts size */ |
| 47 | enum dw_dma_msize { |
| 48 | DW_DMA_MSIZE_1, |
| 49 | DW_DMA_MSIZE_4, |
| 50 | DW_DMA_MSIZE_8, |
| 51 | DW_DMA_MSIZE_16, |
| 52 | DW_DMA_MSIZE_32, |
| 53 | DW_DMA_MSIZE_64, |
| 54 | DW_DMA_MSIZE_128, |
| 55 | DW_DMA_MSIZE_256, |
| 56 | }; |
| 57 | |
| 58 | /* flow controller */ |
| 59 | enum dw_dma_fc { |
| 60 | DW_DMA_FC_D_M2M, |
| 61 | DW_DMA_FC_D_M2P, |
| 62 | DW_DMA_FC_D_P2M, |
| 63 | DW_DMA_FC_D_P2P, |
| 64 | DW_DMA_FC_P_P2M, |
| 65 | DW_DMA_FC_SP_P2P, |
| 66 | DW_DMA_FC_P_M2P, |
| 67 | DW_DMA_FC_DP_P2P, |
| 68 | }; |
| 69 | |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 70 | /** |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 71 | * struct dw_dma_slave - Controller-specific information about a slave |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 72 | * |
| 73 | * @dma_dev: required DMA master device |
| 74 | * @tx_reg: physical address of data register used for |
| 75 | * memory-to-peripheral transfers |
| 76 | * @rx_reg: physical address of data register used for |
| 77 | * peripheral-to-memory transfers |
| 78 | * @reg_width: peripheral register width |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 79 | * @cfg_hi: Platform-specific initializer for the CFG_HI register |
| 80 | * @cfg_lo: Platform-specific initializer for the CFG_LO register |
Viresh Kumar | 59c22fc | 2011-03-03 15:47:23 +0530 | [diff] [blame] | 81 | * @src_master: src master for transfers on allocated channel. |
| 82 | * @dst_master: dest master for transfers on allocated channel. |
Viresh KUMAR | ee66509 | 2011-03-04 15:42:51 +0530 | [diff] [blame] | 83 | * @src_msize: src burst size. |
| 84 | * @dst_msize: dest burst size. |
| 85 | * @fc: flow controller for DMA transfer |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 86 | */ |
| 87 | struct dw_dma_slave { |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 88 | struct device *dma_dev; |
| 89 | dma_addr_t tx_reg; |
| 90 | dma_addr_t rx_reg; |
| 91 | enum dw_dma_slave_width reg_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 92 | u32 cfg_hi; |
| 93 | u32 cfg_lo; |
Viresh Kumar | 59c22fc | 2011-03-03 15:47:23 +0530 | [diff] [blame] | 94 | u8 src_master; |
| 95 | u8 dst_master; |
Viresh KUMAR | ee66509 | 2011-03-04 15:42:51 +0530 | [diff] [blame] | 96 | u8 src_msize; |
| 97 | u8 dst_msize; |
| 98 | u8 fc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | /* Platform-configurable bits in CFG_HI */ |
| 102 | #define DWC_CFGH_FCMODE (1 << 0) |
| 103 | #define DWC_CFGH_FIFO_MODE (1 << 1) |
| 104 | #define DWC_CFGH_PROTCTL(x) ((x) << 2) |
| 105 | #define DWC_CFGH_SRC_PER(x) ((x) << 7) |
| 106 | #define DWC_CFGH_DST_PER(x) ((x) << 11) |
| 107 | |
| 108 | /* Platform-configurable bits in CFG_LO */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 109 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ |
| 110 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) |
| 111 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) |
| 112 | #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ |
| 113 | #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) |
| 114 | #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) |
| 115 | #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ |
| 116 | #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ |
| 117 | #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ |
| 118 | #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ |
| 119 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 120 | /* DMA API extensions */ |
| 121 | struct dw_cyclic_desc { |
| 122 | struct dw_desc **desc; |
| 123 | unsigned long periods; |
| 124 | void (*period_callback)(void *param); |
| 125 | void *period_callback_param; |
| 126 | }; |
| 127 | |
| 128 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, |
| 129 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 130 | enum dma_transfer_direction direction); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 131 | void dw_dma_cyclic_free(struct dma_chan *chan); |
| 132 | int dw_dma_cyclic_start(struct dma_chan *chan); |
| 133 | void dw_dma_cyclic_stop(struct dma_chan *chan); |
| 134 | |
| 135 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); |
| 136 | |
| 137 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); |
| 138 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 139 | #endif /* DW_DMAC_H */ |