blob: 26c3779d871da61ee7976dbfc180eb6ac2999b14 [file] [log] [blame]
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001/*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
Thomas Petazzoni6275afe2013-07-26 10:17:52 -030038 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
Thomas Petazzonifddddb52013-03-21 17:59:14 +010041 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
Ezequiel Garciab15d0b52013-06-07 13:47:38 -030048#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
Thomas Petazzonifddddb52013-03-21 17:59:14 +010050#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/init.h>
53#include <linux/mbus.h>
54#include <linux/io.h>
55#include <linux/ioport.h>
56#include <linux/of.h>
57#include <linux/of_address.h>
58#include <linux/debugfs.h>
Jason Gunthorpe09752a12014-04-18 14:19:51 +020059#include <linux/log2.h>
Thomas Petazzonifddddb52013-03-21 17:59:14 +010060
61/*
62 * DDR target is the same on all platforms.
63 */
64#define TARGET_DDR 0
65
66/*
67 * CPU Address Decode Windows registers
68 */
69#define WIN_CTRL_OFF 0x0000
70#define WIN_CTRL_ENABLE BIT(0)
71#define WIN_CTRL_TGT_MASK 0xf0
72#define WIN_CTRL_TGT_SHIFT 4
73#define WIN_CTRL_ATTR_MASK 0xff00
74#define WIN_CTRL_ATTR_SHIFT 8
75#define WIN_CTRL_SIZE_MASK 0xffff0000
76#define WIN_CTRL_SIZE_SHIFT 16
77#define WIN_BASE_OFF 0x0004
78#define WIN_BASE_LOW 0xffff0000
79#define WIN_BASE_HIGH 0xf
80#define WIN_REMAP_LO_OFF 0x0008
81#define WIN_REMAP_LOW 0xffff0000
82#define WIN_REMAP_HI_OFF 0x000c
83
84#define ATTR_HW_COHERENCY (0x1 << 4)
85
86#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
87#define DDR_BASE_CS_HIGH_MASK 0xf
88#define DDR_BASE_CS_LOW_MASK 0xff000000
89#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
90#define DDR_SIZE_ENABLED BIT(0)
91#define DDR_SIZE_CS_MASK 0x1c
92#define DDR_SIZE_CS_SHIFT 2
93#define DDR_SIZE_MASK 0xff000000
94
95#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
96
Thomas Petazzonifddddb52013-03-21 17:59:14 +010097struct mvebu_mbus_state;
98
99struct mvebu_mbus_soc_data {
100 unsigned int num_wins;
101 unsigned int num_remappable_wins;
102 unsigned int (*win_cfg_offset)(const int win);
103 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
104 int (*show_cpu_target)(struct mvebu_mbus_state *s,
105 struct seq_file *seq, void *v);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100106};
107
108struct mvebu_mbus_state {
109 void __iomem *mbuswins_base;
110 void __iomem *sdramwins_base;
111 struct dentry *debugfs_root;
112 struct dentry *debugfs_sdram;
113 struct dentry *debugfs_devs;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300114 struct resource pcie_mem_aperture;
115 struct resource pcie_io_aperture;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100116 const struct mvebu_mbus_soc_data *soc;
117 int hw_io_coherency;
118};
119
120static struct mvebu_mbus_state mbus_state;
121
122static struct mbus_dram_target_info mvebu_mbus_dram_info;
123const struct mbus_dram_target_info *mv_mbus_dram_info(void)
124{
125 return &mvebu_mbus_dram_info;
126}
127EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
128
129/*
130 * Functions to manipulate the address decoding windows
131 */
132
133static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
134 int win, int *enabled, u64 *base,
135 u32 *size, u8 *target, u8 *attr,
136 u64 *remap)
137{
138 void __iomem *addr = mbus->mbuswins_base +
139 mbus->soc->win_cfg_offset(win);
140 u32 basereg = readl(addr + WIN_BASE_OFF);
141 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
142
143 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
144 *enabled = 0;
145 return;
146 }
147
148 *enabled = 1;
149 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
150 *base |= (basereg & WIN_BASE_LOW);
151 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
152
153 if (target)
154 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
155
156 if (attr)
157 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
158
159 if (remap) {
160 if (win < mbus->soc->num_remappable_wins) {
161 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
162 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
163 *remap = ((u64)remap_hi << 32) | remap_low;
164 } else
165 *remap = 0;
166 }
167}
168
169static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
170 int win)
171{
172 void __iomem *addr;
173
174 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
175
176 writel(0, addr + WIN_BASE_OFF);
177 writel(0, addr + WIN_CTRL_OFF);
178 if (win < mbus->soc->num_remappable_wins) {
179 writel(0, addr + WIN_REMAP_LO_OFF);
180 writel(0, addr + WIN_REMAP_HI_OFF);
181 }
182}
183
184/* Checks whether the given window number is available */
185static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
186 const int win)
187{
188 void __iomem *addr = mbus->mbuswins_base +
189 mbus->soc->win_cfg_offset(win);
190 u32 ctrl = readl(addr + WIN_CTRL_OFF);
191 return !(ctrl & WIN_CTRL_ENABLE);
192}
193
194/*
195 * Checks whether the given (base, base+size) area doesn't overlap an
196 * existing region
197 */
198static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
199 phys_addr_t base, size_t size,
200 u8 target, u8 attr)
201{
202 u64 end = (u64)base + size;
203 int win;
204
205 for (win = 0; win < mbus->soc->num_wins; win++) {
206 u64 wbase, wend;
207 u32 wsize;
208 u8 wtarget, wattr;
209 int enabled;
210
211 mvebu_mbus_read_window(mbus, win,
212 &enabled, &wbase, &wsize,
213 &wtarget, &wattr, NULL);
214
215 if (!enabled)
216 continue;
217
218 wend = wbase + wsize;
219
220 /*
221 * Check if the current window overlaps with the
222 * proposed physical range
223 */
224 if ((u64)base < wend && end > wbase)
225 return 0;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100226 }
227
228 return 1;
229}
230
231static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
232 phys_addr_t base, size_t size)
233{
234 int win;
235
236 for (win = 0; win < mbus->soc->num_wins; win++) {
237 u64 wbase;
238 u32 wsize;
239 int enabled;
240
241 mvebu_mbus_read_window(mbus, win,
242 &enabled, &wbase, &wsize,
243 NULL, NULL, NULL);
244
245 if (!enabled)
246 continue;
247
248 if (base == wbase && size == wsize)
249 return win;
250 }
251
252 return -ENODEV;
253}
254
255static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
256 int win, phys_addr_t base, size_t size,
257 phys_addr_t remap, u8 target,
258 u8 attr)
259{
260 void __iomem *addr = mbus->mbuswins_base +
261 mbus->soc->win_cfg_offset(win);
262 u32 ctrl, remap_addr;
263
Jason Gunthorpe09752a12014-04-18 14:19:51 +0200264 if (!is_power_of_2(size)) {
265 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
266 return -EINVAL;
267 }
268
269 if ((base & (phys_addr_t)(size - 1)) != 0) {
270 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
271 size);
272 return -EINVAL;
273 }
274
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100275 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
276 (attr << WIN_CTRL_ATTR_SHIFT) |
277 (target << WIN_CTRL_TGT_SHIFT) |
278 WIN_CTRL_ENABLE;
279
280 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
281 writel(ctrl, addr + WIN_CTRL_OFF);
282 if (win < mbus->soc->num_remappable_wins) {
283 if (remap == MVEBU_MBUS_NO_REMAP)
284 remap_addr = base;
285 else
286 remap_addr = remap;
287 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
288 writel(0, addr + WIN_REMAP_HI_OFF);
289 }
290
291 return 0;
292}
293
294static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
295 phys_addr_t base, size_t size,
296 phys_addr_t remap, u8 target,
297 u8 attr)
298{
299 int win;
300
301 if (remap == MVEBU_MBUS_NO_REMAP) {
302 for (win = mbus->soc->num_remappable_wins;
303 win < mbus->soc->num_wins; win++)
304 if (mvebu_mbus_window_is_free(mbus, win))
305 return mvebu_mbus_setup_window(mbus, win, base,
306 size, remap,
307 target, attr);
308 }
309
310
311 for (win = 0; win < mbus->soc->num_wins; win++)
312 if (mvebu_mbus_window_is_free(mbus, win))
313 return mvebu_mbus_setup_window(mbus, win, base, size,
314 remap, target, attr);
315
316 return -ENOMEM;
317}
318
319/*
320 * Debugfs debugging
321 */
322
323/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
324static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
325 struct seq_file *seq, void *v)
326{
327 int i;
328
329 for (i = 0; i < 4; i++) {
330 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
331 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
332 u64 base;
333 u32 size;
334
335 if (!(sizereg & DDR_SIZE_ENABLED)) {
336 seq_printf(seq, "[%d] disabled\n", i);
337 continue;
338 }
339
340 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
341 base |= basereg & DDR_BASE_CS_LOW_MASK;
342 size = (sizereg | ~DDR_SIZE_MASK);
343
344 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
345 i, (unsigned long long)base,
346 (unsigned long long)base + size + 1,
347 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
348 }
349
350 return 0;
351}
352
353/* Special function for Dove */
354static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
355 struct seq_file *seq, void *v)
356{
357 int i;
358
359 for (i = 0; i < 2; i++) {
360 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
361 u64 base;
362 u32 size;
363
364 if (!(map & 1)) {
365 seq_printf(seq, "[%d] disabled\n", i);
366 continue;
367 }
368
369 base = map & 0xff800000;
370 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
371
372 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
373 i, (unsigned long long)base,
374 (unsigned long long)base + size, i);
375 }
376
377 return 0;
378}
379
380static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
381{
382 struct mvebu_mbus_state *mbus = &mbus_state;
383 return mbus->soc->show_cpu_target(mbus, seq, v);
384}
385
386static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
387{
388 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
389}
390
391static const struct file_operations mvebu_sdram_debug_fops = {
392 .open = mvebu_sdram_debug_open,
393 .read = seq_read,
394 .llseek = seq_lseek,
395 .release = single_release,
396};
397
398static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
399{
400 struct mvebu_mbus_state *mbus = &mbus_state;
401 int win;
402
403 for (win = 0; win < mbus->soc->num_wins; win++) {
404 u64 wbase, wremap;
405 u32 wsize;
406 u8 wtarget, wattr;
Thomas Petazzonied843a72013-07-26 10:17:51 -0300407 int enabled;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100408
409 mvebu_mbus_read_window(mbus, win,
410 &enabled, &wbase, &wsize,
411 &wtarget, &wattr, &wremap);
412
413 if (!enabled) {
414 seq_printf(seq, "[%02d] disabled\n", win);
415 continue;
416 }
417
Thomas Petazzonied843a72013-07-26 10:17:51 -0300418 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100419 win, (unsigned long long)wbase,
Thomas Petazzonied843a72013-07-26 10:17:51 -0300420 (unsigned long long)(wbase + wsize), wtarget, wattr);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100421
Jason Gunthorpe09752a12014-04-18 14:19:51 +0200422 if (!is_power_of_2(wsize) ||
423 ((wbase & (u64)(wsize - 1)) != 0))
424 seq_puts(seq, " (Invalid base/size!!)");
425
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100426 if (win < mbus->soc->num_remappable_wins) {
427 seq_printf(seq, " (remap %016llx)\n",
428 (unsigned long long)wremap);
429 } else
430 seq_printf(seq, "\n");
431 }
432
433 return 0;
434}
435
436static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
437{
438 return single_open(file, mvebu_devs_debug_show, inode->i_private);
439}
440
441static const struct file_operations mvebu_devs_debug_fops = {
442 .open = mvebu_devs_debug_open,
443 .read = seq_read,
444 .llseek = seq_lseek,
445 .release = single_release,
446};
447
448/*
449 * SoC-specific functions and definitions
450 */
451
452static unsigned int orion_mbus_win_offset(int win)
453{
454 return win << 4;
455}
456
457static unsigned int armada_370_xp_mbus_win_offset(int win)
458{
459 /* The register layout is a bit annoying and the below code
460 * tries to cope with it.
461 * - At offset 0x0, there are the registers for the first 8
462 * windows, with 4 registers of 32 bits per window (ctrl,
463 * base, remap low, remap high)
464 * - Then at offset 0x80, there is a hole of 0x10 bytes for
465 * the internal registers base address and internal units
466 * sync barrier register.
467 * - Then at offset 0x90, there the registers for 12
468 * windows, with only 2 registers of 32 bits per window
469 * (ctrl, base).
470 */
471 if (win < 8)
472 return win << 4;
473 else
474 return 0x90 + ((win - 8) << 3);
475}
476
477static unsigned int mv78xx0_mbus_win_offset(int win)
478{
479 if (win < 8)
480 return win << 4;
481 else
482 return 0x900 + ((win - 8) << 4);
483}
484
485static void __init
486mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
487{
488 int i;
489 int cs;
490
491 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
492
493 for (i = 0, cs = 0; i < 4; i++) {
494 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
495 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
496
497 /*
498 * We only take care of entries for which the chip
499 * select is enabled, and that don't have high base
500 * address bits set (devices can only access the first
501 * 32 bits of the memory).
502 */
503 if ((size & DDR_SIZE_ENABLED) &&
504 !(base & DDR_BASE_CS_HIGH_MASK)) {
505 struct mbus_dram_window *w;
506
507 w = &mvebu_mbus_dram_info.cs[cs++];
508 w->cs_index = i;
509 w->mbus_attr = 0xf & ~(1 << i);
510 if (mbus->hw_io_coherency)
511 w->mbus_attr |= ATTR_HW_COHERENCY;
512 w->base = base & DDR_BASE_CS_LOW_MASK;
513 w->size = (size | ~DDR_SIZE_MASK) + 1;
514 }
515 }
516 mvebu_mbus_dram_info.num_cs = cs;
517}
518
519static void __init
520mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
521{
522 int i;
523 int cs;
524
525 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
526
527 for (i = 0, cs = 0; i < 2; i++) {
528 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
529
530 /*
531 * Chip select enabled?
532 */
533 if (map & 1) {
534 struct mbus_dram_window *w;
535
536 w = &mvebu_mbus_dram_info.cs[cs++];
537 w->cs_index = i;
538 w->mbus_attr = 0; /* CS address decoding done inside */
539 /* the DDR controller, no need to */
540 /* provide attributes */
541 w->base = map & 0xff800000;
542 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
543 }
544 }
545
546 mvebu_mbus_dram_info.num_cs = cs;
547}
548
Thomas Petazzoni59cb2fc2013-07-26 10:17:53 -0300549static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100550 .num_wins = 20,
551 .num_remappable_wins = 8,
552 .win_cfg_offset = armada_370_xp_mbus_win_offset,
553 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
554 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100555};
556
557static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
558 .num_wins = 8,
559 .num_remappable_wins = 4,
560 .win_cfg_offset = orion_mbus_win_offset,
561 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
562 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100563};
564
565static const struct mvebu_mbus_soc_data dove_mbus_data = {
566 .num_wins = 8,
567 .num_remappable_wins = 4,
568 .win_cfg_offset = orion_mbus_win_offset,
569 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
570 .show_cpu_target = mvebu_sdram_debug_show_dove,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100571};
572
573/*
574 * Some variants of Orion5x have 4 remappable windows, some other have
575 * only two of them.
576 */
577static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
578 .num_wins = 8,
579 .num_remappable_wins = 4,
580 .win_cfg_offset = orion_mbus_win_offset,
581 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
582 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100583};
584
585static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
586 .num_wins = 8,
587 .num_remappable_wins = 2,
588 .win_cfg_offset = orion_mbus_win_offset,
589 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
590 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100591};
592
593static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
594 .num_wins = 14,
595 .num_remappable_wins = 8,
596 .win_cfg_offset = mv78xx0_mbus_win_offset,
597 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
598 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100599};
600
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100601static const struct of_device_id of_mvebu_mbus_ids[] = {
602 { .compatible = "marvell,armada370-mbus",
Thomas Petazzoni59cb2fc2013-07-26 10:17:53 -0300603 .data = &armada_370_xp_mbus_data, },
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100604 { .compatible = "marvell,armadaxp-mbus",
Thomas Petazzoni59cb2fc2013-07-26 10:17:53 -0300605 .data = &armada_370_xp_mbus_data, },
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100606 { .compatible = "marvell,kirkwood-mbus",
607 .data = &kirkwood_mbus_data, },
608 { .compatible = "marvell,dove-mbus",
609 .data = &dove_mbus_data, },
610 { .compatible = "marvell,orion5x-88f5281-mbus",
611 .data = &orion5x_4win_mbus_data, },
612 { .compatible = "marvell,orion5x-88f5182-mbus",
613 .data = &orion5x_2win_mbus_data, },
614 { .compatible = "marvell,orion5x-88f5181-mbus",
615 .data = &orion5x_2win_mbus_data, },
616 { .compatible = "marvell,orion5x-88f6183-mbus",
617 .data = &orion5x_4win_mbus_data, },
618 { .compatible = "marvell,mv78xx0-mbus",
619 .data = &mv78xx0_mbus_data, },
620 { },
621};
622
623/*
624 * Public API of the driver
625 */
Thomas Petazzoni6a63b092013-07-26 10:17:39 -0300626int mvebu_mbus_add_window_remap_by_id(unsigned int target,
627 unsigned int attribute,
628 phys_addr_t base, size_t size,
629 phys_addr_t remap)
630{
631 struct mvebu_mbus_state *s = &mbus_state;
632
633 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
634 pr_err("cannot add window '%x:%x', conflicts with another window\n",
635 target, attribute);
636 return -EINVAL;
637 }
638
639 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
640}
641
Thomas Petazzoni6a63b092013-07-26 10:17:39 -0300642int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
643 phys_addr_t base, size_t size)
644{
645 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
646 size, MVEBU_MBUS_NO_REMAP);
647}
648
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100649int mvebu_mbus_del_window(phys_addr_t base, size_t size)
650{
651 int win;
652
653 win = mvebu_mbus_find_window(&mbus_state, base, size);
654 if (win < 0)
655 return win;
656
657 mvebu_mbus_disable_window(&mbus_state, win);
658 return 0;
659}
660
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300661void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
662{
663 if (!res)
664 return;
665 *res = mbus_state.pcie_mem_aperture;
666}
667
668void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
669{
670 if (!res)
671 return;
672 *res = mbus_state.pcie_io_aperture;
673}
674
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100675static __init int mvebu_mbus_debugfs_init(void)
676{
677 struct mvebu_mbus_state *s = &mbus_state;
678
679 /*
680 * If no base has been initialized, doesn't make sense to
681 * register the debugfs entries. We may be on a multiplatform
682 * kernel that isn't running a Marvell EBU SoC.
683 */
684 if (!s->mbuswins_base)
685 return 0;
686
687 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
688 if (s->debugfs_root) {
689 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
690 s->debugfs_root, NULL,
691 &mvebu_sdram_debug_fops);
692 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
693 s->debugfs_root, NULL,
694 &mvebu_devs_debug_fops);
695 }
696
697 return 0;
698}
699fs_initcall(mvebu_mbus_debugfs_init);
700
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -0300701static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
702 phys_addr_t mbuswins_phys_base,
703 size_t mbuswins_size,
704 phys_addr_t sdramwins_phys_base,
705 size_t sdramwins_size)
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100706{
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100707 int win;
708
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100709 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
710 if (!mbus->mbuswins_base)
711 return -ENOMEM;
712
713 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
714 if (!mbus->sdramwins_base) {
715 iounmap(mbus_state.mbuswins_base);
716 return -ENOMEM;
717 }
718
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100719 for (win = 0; win < mbus->soc->num_wins; win++)
720 mvebu_mbus_disable_window(mbus, win);
721
722 mbus->soc->setup_cpu_target(mbus);
723
724 return 0;
725}
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -0300726
727int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
728 size_t mbuswins_size,
729 phys_addr_t sdramwins_phys_base,
730 size_t sdramwins_size)
731{
732 const struct of_device_id *of_id;
733
Dan Carpenter7663cfd2013-11-13 10:50:24 +0300734 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -0300735 if (!strcmp(of_id->compatible, soc))
736 break;
737
Dan Carpenter7663cfd2013-11-13 10:50:24 +0300738 if (!of_id->compatible[0]) {
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -0300739 pr_err("could not find a matching SoC family\n");
740 return -ENODEV;
741 }
742
743 mbus_state.soc = of_id->data;
744
745 return mvebu_mbus_common_init(&mbus_state,
746 mbuswins_phys_base,
747 mbuswins_size,
748 sdramwins_phys_base,
749 sdramwins_size);
750}
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300751
752#ifdef CONFIG_OF
Ezequiel Garciabb24cab2013-07-26 10:17:46 -0300753/*
754 * The window IDs in the ranges DT property have the following format:
755 * - bits 28 to 31: MBus custom field
756 * - bits 24 to 27: window target ID
757 * - bits 16 to 23: window attribute ID
758 * - bits 0 to 15: unused
759 */
760#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
761#define TARGET(id) (((id) & 0x0F000000) >> 24)
762#define ATTR(id) (((id) & 0x00FF0000) >> 16)
763
764static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
765 u32 base, u32 size,
766 u8 target, u8 attr)
767{
Ezequiel Garciabb24cab2013-07-26 10:17:46 -0300768 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
Thomas Petazzonied843a72013-07-26 10:17:51 -0300769 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
770 target, attr);
Ezequiel Garciabb24cab2013-07-26 10:17:46 -0300771 return -EBUSY;
772 }
773
774 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
775 target, attr)) {
Thomas Petazzonied843a72013-07-26 10:17:51 -0300776 pr_err("cannot add window '%04x:%04x', too many windows\n",
777 target, attr);
Ezequiel Garciabb24cab2013-07-26 10:17:46 -0300778 return -ENOMEM;
779 }
780 return 0;
781}
782
783static int __init
784mbus_parse_ranges(struct device_node *node,
785 int *addr_cells, int *c_addr_cells, int *c_size_cells,
786 int *cell_count, const __be32 **ranges_start,
787 const __be32 **ranges_end)
788{
789 const __be32 *prop;
790 int ranges_len, tuple_len;
791
792 /* Allow a node with no 'ranges' property */
793 *ranges_start = of_get_property(node, "ranges", &ranges_len);
794 if (*ranges_start == NULL) {
795 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
796 *ranges_start = *ranges_end = NULL;
797 return 0;
798 }
799 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
800
801 *addr_cells = of_n_addr_cells(node);
802
803 prop = of_get_property(node, "#address-cells", NULL);
804 *c_addr_cells = be32_to_cpup(prop);
805
806 prop = of_get_property(node, "#size-cells", NULL);
807 *c_size_cells = be32_to_cpup(prop);
808
809 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
810 tuple_len = (*cell_count) * sizeof(__be32);
811
812 if (ranges_len % tuple_len) {
813 pr_warn("malformed ranges entry '%s'\n", node->name);
814 return -EINVAL;
815 }
816 return 0;
817}
818
819static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
820 struct device_node *np)
821{
822 int addr_cells, c_addr_cells, c_size_cells;
823 int i, ret, cell_count;
824 const __be32 *r, *ranges_start, *ranges_end;
825
826 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
827 &c_size_cells, &cell_count,
828 &ranges_start, &ranges_end);
829 if (ret < 0)
830 return ret;
831
832 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
833 u32 windowid, base, size;
834 u8 target, attr;
835
836 /*
837 * An entry with a non-zero custom field do not
838 * correspond to a static window, so skip it.
839 */
840 windowid = of_read_number(r, 1);
841 if (CUSTOM(windowid))
842 continue;
843
844 target = TARGET(windowid);
845 attr = ATTR(windowid);
846
847 base = of_read_number(r + c_addr_cells, addr_cells);
848 size = of_read_number(r + c_addr_cells + addr_cells,
849 c_size_cells);
850 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
851 if (ret < 0)
852 return ret;
853 }
854 return 0;
855}
856
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300857static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
858 struct resource *mem,
859 struct resource *io)
860{
861 u32 reg[2];
862 int ret;
863
864 /*
Jason Gunthorpe8553bca2013-09-17 14:11:04 -0600865 * These are optional, so we make sure that resource_size(x) will
866 * return 0.
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300867 */
868 memset(mem, 0, sizeof(struct resource));
Jason Gunthorpe8553bca2013-09-17 14:11:04 -0600869 mem->end = -1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300870 memset(io, 0, sizeof(struct resource));
Jason Gunthorpe8553bca2013-09-17 14:11:04 -0600871 io->end = -1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300872
873 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
874 if (!ret) {
875 mem->start = reg[0];
Jason Gunthorpea723e752014-02-12 15:57:07 -0700876 mem->end = mem->start + reg[1] - 1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300877 mem->flags = IORESOURCE_MEM;
878 }
879
880 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
881 if (!ret) {
882 io->start = reg[0];
Jason Gunthorpea723e752014-02-12 15:57:07 -0700883 io->end = io->start + reg[1] - 1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300884 io->flags = IORESOURCE_IO;
885 }
886}
887
Thomas Petazzoni5686a1e2014-04-14 15:47:01 +0200888int __init mvebu_mbus_dt_init(bool is_coherent)
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300889{
890 struct resource mbuswins_res, sdramwins_res;
891 struct device_node *np, *controller;
892 const struct of_device_id *of_id;
893 const __be32 *prop;
894 int ret;
895
Josh Cartwright087a4ab2014-02-11 10:24:00 -0600896 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300897 if (!np) {
898 pr_err("could not find a matching SoC family\n");
899 return -ENODEV;
900 }
901
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300902 mbus_state.soc = of_id->data;
903
904 prop = of_get_property(np, "controller", NULL);
905 if (!prop) {
906 pr_err("required 'controller' property missing\n");
907 return -EINVAL;
908 }
909
910 controller = of_find_node_by_phandle(be32_to_cpup(prop));
911 if (!controller) {
912 pr_err("could not find an 'mbus-controller' node\n");
913 return -ENODEV;
914 }
915
916 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
917 pr_err("cannot get MBUS register address\n");
918 return -EINVAL;
919 }
920
921 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
922 pr_err("cannot get SDRAM register address\n");
923 return -EINVAL;
924 }
925
Thomas Petazzoni5686a1e2014-04-14 15:47:01 +0200926 mbus_state.hw_io_coherency = is_coherent;
927
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300928 /* Get optional pcie-{mem,io}-aperture properties */
929 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
930 &mbus_state.pcie_io_aperture);
931
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300932 ret = mvebu_mbus_common_init(&mbus_state,
933 mbuswins_res.start,
934 resource_size(&mbuswins_res),
935 sdramwins_res.start,
936 resource_size(&sdramwins_res));
Ezequiel Garciabb24cab2013-07-26 10:17:46 -0300937 if (ret)
938 return ret;
939
940 /* Setup statically declared windows in the DT */
941 return mbus_dt_setup(&mbus_state, np);
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -0300942}
943#endif