blob: 1335b2e1bed4c66efe95ee2f679129d3856ccb43 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +00001/include/ "skeleton.dtsi"
2
Ezequiel Garcia3ec81e72013-07-26 10:18:04 -03003#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
4
Jason Cooper3d468b62012-02-27 16:07:13 +00005/ {
Andrew Lunn77843502012-07-18 19:22:54 +02006 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +02007 interrupt-parent = <&intc>;
8
Adam Baker33a66752013-06-02 22:59:50 +01009 cpus {
10 #address-cells = <1>;
11 #size-cells = <0>;
12
13 cpu@0 {
14 device_type = "cpu";
15 compatible = "marvell,feroceon";
Andrew Lunn22904142013-09-13 22:09:52 +020016 reg = <0>;
Adam Baker33a66752013-06-02 22:59:50 +010017 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
18 clock-names = "cpu_clk", "ddrclk", "powersave";
19 };
20 };
21
Andrew Lunnf9e75922012-11-17 17:00:44 +010022 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 };
Jason Cooper3d468b62012-02-27 16:07:13 +000026
Ezequiel Garcia455f81a2013-07-26 10:18:03 -030027 mbus {
28 compatible = "marvell,kirkwood-mbus", "simple-bus";
Ezequiel Garcia54397d82013-07-26 10:18:05 -030029 #address-cells = <2>;
30 #size-cells = <1>;
Ezequiel Garcia455f81a2013-07-26 10:18:03 -030031 controller = <&mbusc>;
Ezequiel Garcia54397d82013-07-26 10:18:05 -030032 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
33 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
Ezequiel Garcia455f81a2013-07-26 10:18:03 -030034 };
35
Jason Cooper163f2ce2012-03-15 01:00:27 +000036 ocp@f1000000 {
37 compatible = "simple-bus";
Ezequiel Garcia01db5272013-06-18 12:31:19 -030038 ranges = <0x00000000 0xf1000000 0x0100000
39 0xf4000000 0xf4000000 0x0000400
Andrew Lunnf37fbd32012-09-03 20:29:34 +020040 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +000041 #address-cells = <1>;
42 #size-cells = <1>;
43
Ezequiel Garcia455f81a2013-07-26 10:18:03 -030044 mbusc: mbus-controller@20000 {
45 compatible = "marvell,mbus-controller";
46 reg = <0x20000 0x80>, <0x1500 0x20>;
47 };
48
Sebastian Hesselbarth15f18592013-07-02 13:03:38 +020049 timer: timer@20300 {
50 compatible = "marvell,orion-timer";
51 reg = <0x20300 0x20>;
52 interrupt-parent = <&bridge_intc>;
53 interrupts = <1>, <2>;
54 clocks = <&core_clk 0>;
55 };
56
57 intc: main-interrupt-ctrl@20200 {
58 compatible = "marvell,orion-intc";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x20200 0x10>, <0x20210 0x10>;
62 };
63
64 bridge_intc: bridge-interrupt-ctrl@20110 {
65 compatible = "marvell,orion-bridge-intc";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x20110 0x8>;
69 interrupts = <1>;
70 marvell,#interrupts = <6>;
71 };
72
Andrew Lunn1611f872012-11-17 15:22:28 +010073 core_clk: core-clocks@10030 {
74 compatible = "marvell,kirkwood-core-clock";
75 reg = <0x10030 0x4>;
76 #clock-cells = <1>;
77 };
78
Andrew Lunn278b45b2012-06-27 13:40:04 +020079 gpio0: gpio@10100 {
80 compatible = "marvell,orion-gpio";
81 #gpio-cells = <2>;
82 gpio-controller;
83 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +010084 ngpios = <32>;
85 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +010086 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +020087 interrupts = <35>, <36>, <37>, <38>;
Andrew Lunnde887472013-02-03 11:34:26 +010088 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +020089 };
90
91 gpio1: gpio@10140 {
92 compatible = "marvell,orion-gpio";
93 #gpio-cells = <2>;
94 gpio-controller;
95 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +010096 ngpios = <18>;
97 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +010098 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +020099 interrupts = <39>, <40>, <41>;
Andrew Lunnde887472013-02-03 11:34:26 +0100100 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200101 };
102
Jason Cooper163f2ce2012-03-15 01:00:27 +0000103 serial@12000 {
104 compatible = "ns16550a";
105 reg = <0x12000 0x100>;
106 reg-shift = <2>;
107 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100108 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000109 status = "disabled";
110 };
111
112 serial@12100 {
113 compatible = "ns16550a";
114 reg = <0x12100 0x100>;
115 reg-shift = <2>;
116 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100117 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000118 status = "disabled";
119 };
Jason Coopere871b872012-03-06 23:55:04 +0000120
Michael Walle76372122012-06-06 20:30:57 +0200121 spi@10600 {
122 compatible = "marvell,orion-spi";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 cell-index = <0>;
126 interrupts = <23>;
127 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100128 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200129 status = "disabled";
130 };
131
Andrew Lunn1611f872012-11-17 15:22:28 +0100132 gate_clk: clock-gating-control@2011c {
133 compatible = "marvell,kirkwood-gating-clock";
134 reg = <0x2011c 0x4>;
135 clocks = <&core_clk 0>;
136 #clock-cells = <1>;
137 };
138
Sebastian Hesselbarth15f18592013-07-02 13:03:38 +0200139 wdt: watchdog-timer@20300 {
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200140 compatible = "marvell,orion-wdt";
141 reg = <0x20300 0x28>;
Sebastian Hesselbarth15f18592013-07-02 13:03:38 +0200142 interrupt-parent = <&bridge_intc>;
143 interrupts = <3>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100144 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200145 status = "okay";
146 };
147
Andrew Lunnc896ed02012-11-18 11:44:57 +0100148 xor@60800 {
149 compatible = "marvell,orion-xor";
150 reg = <0x60800 0x100
151 0x60A00 0x100>;
152 status = "okay";
153 clocks = <&gate_clk 8>;
154
155 xor00 {
156 interrupts = <5>;
157 dmacap,memcpy;
158 dmacap,xor;
159 };
160 xor01 {
161 interrupts = <6>;
162 dmacap,memcpy;
163 dmacap,xor;
164 dmacap,memset;
165 };
166 };
167
168 xor@60900 {
169 compatible = "marvell,orion-xor";
170 reg = <0x60900 0x100
Quentin Armitageddf7e392013-09-19 12:00:29 +0100171 0x60B00 0x100>;
Andrew Lunnc896ed02012-11-18 11:44:57 +0100172 status = "okay";
173 clocks = <&gate_clk 16>;
174
175 xor00 {
176 interrupts = <7>;
177 dmacap,memcpy;
178 dmacap,xor;
179 };
180 xor01 {
181 interrupts = <8>;
182 dmacap,memcpy;
183 dmacap,xor;
184 dmacap,memset;
185 };
186 };
187
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200188 ehci@50000 {
189 compatible = "marvell,orion-ehci";
190 reg = <0x50000 0x1000>;
191 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100192 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200193 status = "okay";
194 };
195
Jamie Lentin858156b2012-04-18 11:06:42 +0100196 nand@3000000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cle = <0>;
200 ale = <1>;
201 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200202 compatible = "marvell,orion-nand";
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300203 reg = <0xf4000000 0x400>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100204 chip-delay = <25>;
205 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100206 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100207 status = "disabled";
208 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200209
210 i2c@11000 {
211 compatible = "marvell,mv64xxx-i2c";
212 reg = <0x11000 0x20>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 interrupts = <29>;
216 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100217 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200218 status = "disabled";
219 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200220
221 crypto@30000 {
222 compatible = "marvell,orion-crypto";
223 reg = <0x30000 0x10000>,
224 <0xf5000000 0x800>;
225 reg-names = "regs", "sram";
226 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100227 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200228 status = "okay";
229 };
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +0200230
231 mdio: mdio-bus@72004 {
232 compatible = "marvell,orion-mdio";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 reg = <0x72004 0x84>;
236 interrupts = <46>;
237 clocks = <&gate_clk 0>;
238 status = "disabled";
239
240 /* add phy nodes in board file */
241 };
242
243 eth0: ethernet-controller@72000 {
244 compatible = "marvell,kirkwood-eth";
245 #address-cells = <1>;
246 #size-cells = <0>;
247 reg = <0x72000 0x4000>;
248 clocks = <&gate_clk 0>;
249 marvell,tx-checksum-limit = <1600>;
250 status = "disabled";
251
252 ethernet0-port@0 {
253 device_type = "network";
254 compatible = "marvell,kirkwood-eth-port";
255 reg = <0>;
256 interrupts = <11>;
257 /* overwrite MAC address in bootloader */
258 local-mac-address = [00 00 00 00 00 00];
259 /* set phy-handle property in board file */
260 };
261 };
262
263 eth1: ethernet-controller@76000 {
264 compatible = "marvell,kirkwood-eth";
265 #address-cells = <1>;
266 #size-cells = <0>;
267 reg = <0x76000 0x4000>;
268 clocks = <&gate_clk 19>;
269 marvell,tx-checksum-limit = <1600>;
270 status = "disabled";
271
272 ethernet1-port@0 {
273 device_type = "network";
274 compatible = "marvell,kirkwood-eth-port";
275 reg = <0>;
276 interrupts = <15>;
277 /* overwrite MAC address in bootloader */
278 local-mac-address = [00 00 00 00 00 00];
279 /* set phy-handle property in board file */
280 };
281 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000282 };
283};