blob: 47e6bafeb743d759416afaacc718bf3cae5c03db [file] [log] [blame]
Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Jesse Barnes585fb112008-07-29 11:54:06 -070028/*
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
31 */
32#define INTEL_GMCH_CTRL 0x52
33#define INTEL_GMCH_ENABLED 0x4
34#define INTEL_GMCH_MEM_MASK 0x1
35#define INTEL_GMCH_MEM_64M 0x1
36#define INTEL_GMCH_MEM_128M 0
37
38#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
39#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
40#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
41#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
42#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
43#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
44#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
45
46#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
47#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
48
49/* PCI config space */
50
51#define HPLLCC 0xc0 /* 855 only */
52#define GC_CLOCK_CONTROL_MASK (3 << 0)
53#define GC_CLOCK_133_200 (0 << 0)
54#define GC_CLOCK_100_200 (1 << 0)
55#define GC_CLOCK_100_133 (2 << 0)
56#define GC_CLOCK_166_250 (3 << 0)
57#define GCFGC 0xf0 /* 915+ only */
58#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
59#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
60#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
61#define GC_DISPLAY_CLOCK_MASK (7 << 4)
62#define LBB 0xf4
63
64/* VGA stuff */
65
66#define VGA_ST01_MDA 0x3ba
67#define VGA_ST01_CGA 0x3da
68
69#define VGA_MSR_WRITE 0x3c2
70#define VGA_MSR_READ 0x3cc
71#define VGA_MSR_MEM_EN (1<<1)
72#define VGA_MSR_CGA_MODE (1<<0)
73
74#define VGA_SR_INDEX 0x3c4
75#define VGA_SR_DATA 0x3c5
76
77#define VGA_AR_INDEX 0x3c0
78#define VGA_AR_VID_EN (1<<5)
79#define VGA_AR_DATA_WRITE 0x3c0
80#define VGA_AR_DATA_READ 0x3c1
81
82#define VGA_GR_INDEX 0x3ce
83#define VGA_GR_DATA 0x3cf
84/* GR05 */
85#define VGA_GR_MEM_READ_MODE_SHIFT 3
86#define VGA_GR_MEM_READ_MODE_PLANE 1
87/* GR06 */
88#define VGA_GR_MEM_MODE_MASK 0xc
89#define VGA_GR_MEM_MODE_SHIFT 2
90#define VGA_GR_MEM_A0000_AFFFF 0
91#define VGA_GR_MEM_A0000_BFFFF 1
92#define VGA_GR_MEM_B0000_B7FFF 2
93#define VGA_GR_MEM_B0000_BFFFF 3
94
95#define VGA_DACMASK 0x3c6
96#define VGA_DACRX 0x3c7
97#define VGA_DACWX 0x3c8
98#define VGA_DACDATA 0x3c9
99
100#define VGA_CR_INDEX_MDA 0x3b4
101#define VGA_CR_DATA_MDA 0x3b5
102#define VGA_CR_INDEX_CGA 0x3d4
103#define VGA_CR_DATA_CGA 0x3d5
104
105/*
106 * Memory interface instructions used by the kernel
107 */
108#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
109
110#define MI_NOOP MI_INSTR(0, 0)
111#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
112#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
113#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
114#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
115#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
116#define MI_FLUSH MI_INSTR(0x04, 0)
117#define MI_READ_FLUSH (1 << 0)
118#define MI_EXE_FLUSH (1 << 1)
119#define MI_NO_WRITE_FLUSH (1 << 2)
120#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
121#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
122#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
123#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
124#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
125#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
126#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
127#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
128#define MI_STORE_DWORD_INDEX_SHIFT 2
129#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
130#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
131#define MI_BATCH_NON_SECURE (1)
132#define MI_BATCH_NON_SECURE_I965 (1<<8)
133#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
134
135/*
136 * 3D instructions used by the kernel
137 */
138#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
139
140#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
141#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
142#define SC_UPDATE_SCISSOR (0x1<<1)
143#define SC_ENABLE_MASK (0x1<<0)
144#define SC_ENABLE (0x1<<0)
145#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
146#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
147#define SCI_YMIN_MASK (0xffff<<16)
148#define SCI_XMIN_MASK (0xffff<<0)
149#define SCI_YMAX_MASK (0xffff<<16)
150#define SCI_XMAX_MASK (0xffff<<0)
151#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
152#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
153#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
154#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
155#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
156#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
157#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
158#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
159#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
160#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
161#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
162#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
163#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
164#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
165#define BLT_DEPTH_8 (0<<24)
166#define BLT_DEPTH_16_565 (1<<24)
167#define BLT_DEPTH_16_1555 (2<<24)
168#define BLT_DEPTH_32 (3<<24)
169#define BLT_ROP_GXCOPY (0xcc<<16)
170#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
171#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
172#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
173#define ASYNC_FLIP (1<<22)
174#define DISPLAY_PLANE_A (0<<20)
175#define DISPLAY_PLANE_B (1<<20)
176
177/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800178 * Fence registers
179 */
180#define FENCE_REG_830_0 0x2000
181#define I830_FENCE_START_MASK 0x07f80000
182#define I830_FENCE_TILING_Y_SHIFT 12
183#define I830_FENCE_SIZE_BITS(size) ((get_order(size >> 19) - 1) << 8)
184#define I830_FENCE_PITCH_SHIFT 4
185#define I830_FENCE_REG_VALID (1<<0)
186
187#define I915_FENCE_START_MASK 0x0ff00000
188#define I915_FENCE_SIZE_BITS(size) ((get_order(size >> 20) - 1) << 8)
189
190#define FENCE_REG_965_0 0x03000
191#define I965_FENCE_PITCH_SHIFT 2
192#define I965_FENCE_TILING_Y_SHIFT 1
193#define I965_FENCE_REG_VALID (1<<0)
194
195/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700196 * Instruction and interrupt control regs
197 */
Jesse Barnes585fb112008-07-29 11:54:06 -0700198#define PRB0_TAIL 0x02030
199#define PRB0_HEAD 0x02034
200#define PRB0_START 0x02038
201#define PRB0_CTL 0x0203c
202#define TAIL_ADDR 0x001FFFF8
203#define HEAD_WRAP_COUNT 0xFFE00000
204#define HEAD_WRAP_ONE 0x00200000
205#define HEAD_ADDR 0x001FFFFC
206#define RING_NR_PAGES 0x001FF000
207#define RING_REPORT_MASK 0x00000006
208#define RING_REPORT_64K 0x00000002
209#define RING_REPORT_128K 0x00000004
210#define RING_NO_REPORT 0x00000000
211#define RING_VALID_MASK 0x00000001
212#define RING_VALID 0x00000001
213#define RING_INVALID 0x00000000
214#define PRB1_TAIL 0x02040 /* 915+ only */
215#define PRB1_HEAD 0x02044 /* 915+ only */
216#define PRB1_START 0x02048 /* 915+ only */
217#define PRB1_CTL 0x0204c /* 915+ only */
218#define ACTHD_I965 0x02074
219#define HWS_PGA 0x02080
220#define HWS_ADDRESS_MASK 0xfffff000
221#define HWS_START_ADDRESS_SHIFT 4
222#define IPEIR 0x02088
223#define NOPID 0x02094
224#define HWSTAM 0x02098
225#define SCPD0 0x0209c /* 915+ only */
226#define IER 0x020a0
227#define IIR 0x020a4
228#define IMR 0x020a8
229#define ISR 0x020ac
230#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
231#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
232#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
233#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
234#define I915_HWB_OOM_INTERRUPT (1<<13)
235#define I915_SYNC_STATUS_INTERRUPT (1<<12)
236#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
237#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
238#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
239#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
240#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
241#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
242#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
243#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
244#define I915_DEBUG_INTERRUPT (1<<2)
245#define I915_USER_INTERRUPT (1<<1)
246#define I915_ASLE_INTERRUPT (1<<0)
247#define EIR 0x020b0
248#define EMR 0x020b4
249#define ESR 0x020b8
250#define INSTPM 0x020c0
251#define ACTHD 0x020c8
252#define FW_BLC 0x020d8
253#define FW_BLC_SELF 0x020e0 /* 915+ only */
254#define MI_ARB_STATE 0x020e4 /* 915+ only */
255#define CACHE_MODE_0 0x02120 /* 915+ only */
256#define CM0_MASK_SHIFT 16
257#define CM0_IZ_OPT_DISABLE (1<<6)
258#define CM0_ZR_OPT_DISABLE (1<<5)
259#define CM0_DEPTH_EVICT_DISABLE (1<<4)
260#define CM0_COLOR_EVICT_DISABLE (1<<3)
261#define CM0_DEPTH_WRITE_DISABLE (1<<1)
262#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
263#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
264
Jesse Barnesde151cf2008-11-12 10:03:55 -0800265
Jesse Barnes585fb112008-07-29 11:54:06 -0700266/*
267 * Framebuffer compression (915+ only)
268 */
269
270#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
271#define FBC_LL_BASE 0x03204 /* 4k page aligned */
272#define FBC_CONTROL 0x03208
273#define FBC_CTL_EN (1<<31)
274#define FBC_CTL_PERIODIC (1<<30)
275#define FBC_CTL_INTERVAL_SHIFT (16)
276#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
277#define FBC_CTL_STRIDE_SHIFT (5)
278#define FBC_CTL_FENCENO (1<<0)
279#define FBC_COMMAND 0x0320c
280#define FBC_CMD_COMPRESS (1<<0)
281#define FBC_STATUS 0x03210
282#define FBC_STAT_COMPRESSING (1<<31)
283#define FBC_STAT_COMPRESSED (1<<30)
284#define FBC_STAT_MODIFIED (1<<29)
285#define FBC_STAT_CURRENT_LINE (1<<0)
286#define FBC_CONTROL2 0x03214
287#define FBC_CTL_FENCE_DBL (0<<4)
288#define FBC_CTL_IDLE_IMM (0<<2)
289#define FBC_CTL_IDLE_FULL (1<<2)
290#define FBC_CTL_IDLE_LINE (2<<2)
291#define FBC_CTL_IDLE_DEBUG (3<<2)
292#define FBC_CTL_CPU_FENCE (1<<1)
293#define FBC_CTL_PLANEA (0<<0)
294#define FBC_CTL_PLANEB (1<<0)
295#define FBC_FENCE_OFF 0x0321b
296
297#define FBC_LL_SIZE (1536)
298
299/*
300 * GPIO regs
301 */
302#define GPIOA 0x5010
303#define GPIOB 0x5014
304#define GPIOC 0x5018
305#define GPIOD 0x501c
306#define GPIOE 0x5020
307#define GPIOF 0x5024
308#define GPIOG 0x5028
309#define GPIOH 0x502c
310# define GPIO_CLOCK_DIR_MASK (1 << 0)
311# define GPIO_CLOCK_DIR_IN (0 << 1)
312# define GPIO_CLOCK_DIR_OUT (1 << 1)
313# define GPIO_CLOCK_VAL_MASK (1 << 2)
314# define GPIO_CLOCK_VAL_OUT (1 << 3)
315# define GPIO_CLOCK_VAL_IN (1 << 4)
316# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
317# define GPIO_DATA_DIR_MASK (1 << 8)
318# define GPIO_DATA_DIR_IN (0 << 9)
319# define GPIO_DATA_DIR_OUT (1 << 9)
320# define GPIO_DATA_VAL_MASK (1 << 10)
321# define GPIO_DATA_VAL_OUT (1 << 11)
322# define GPIO_DATA_VAL_IN (1 << 12)
323# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
324
325/*
326 * Clock control & power management
327 */
328
329#define VGA0 0x6000
330#define VGA1 0x6004
331#define VGA_PD 0x6010
332#define VGA0_PD_P2_DIV_4 (1 << 7)
333#define VGA0_PD_P1_DIV_2 (1 << 5)
334#define VGA0_PD_P1_SHIFT 0
335#define VGA0_PD_P1_MASK (0x1f << 0)
336#define VGA1_PD_P2_DIV_4 (1 << 15)
337#define VGA1_PD_P1_DIV_2 (1 << 13)
338#define VGA1_PD_P1_SHIFT 8
339#define VGA1_PD_P1_MASK (0x1f << 8)
340#define DPLL_A 0x06014
341#define DPLL_B 0x06018
342#define DPLL_VCO_ENABLE (1 << 31)
343#define DPLL_DVO_HIGH_SPEED (1 << 30)
344#define DPLL_SYNCLOCK_ENABLE (1 << 29)
345#define DPLL_VGA_MODE_DIS (1 << 28)
346#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
347#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
348#define DPLL_MODE_MASK (3 << 26)
349#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
350#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
351#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
352#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
353#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
354#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
355
356#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
357#define I915_CRC_ERROR_ENABLE (1UL<<29)
358#define I915_CRC_DONE_ENABLE (1UL<<28)
359#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
360#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
361#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
362#define I915_DPST_EVENT_ENABLE (1UL<<23)
363#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
364#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
365#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
366#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
367#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
368#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
369#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
370#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
371#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
372#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
373#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
374#define I915_DPST_EVENT_STATUS (1UL<<7)
375#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
376#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
377#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
378#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
379#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
380#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
381
382#define SRX_INDEX 0x3c4
383#define SRX_DATA 0x3c5
384#define SR01 1
385#define SR01_SCREEN_OFF (1<<5)
386
387#define PPCR 0x61204
388#define PPCR_ON (1<<0)
389
390#define DVOB 0x61140
391#define DVOB_ON (1<<31)
392#define DVOC 0x61160
393#define DVOC_ON (1<<31)
394#define LVDS 0x61180
395#define LVDS_ON (1<<31)
396
397#define ADPA 0x61100
398#define ADPA_DPMS_MASK (~(3<<10))
399#define ADPA_DPMS_ON (0<<10)
400#define ADPA_DPMS_SUSPEND (1<<10)
401#define ADPA_DPMS_STANDBY (2<<10)
402#define ADPA_DPMS_OFF (3<<10)
403
404#define RING_TAIL 0x00
405#define TAIL_ADDR 0x001FFFF8
406#define RING_HEAD 0x04
407#define HEAD_WRAP_COUNT 0xFFE00000
408#define HEAD_WRAP_ONE 0x00200000
409#define HEAD_ADDR 0x001FFFFC
410#define RING_START 0x08
411#define START_ADDR 0xFFFFF000
412#define RING_LEN 0x0C
413#define RING_NR_PAGES 0x001FF000
414#define RING_REPORT_MASK 0x00000006
415#define RING_REPORT_64K 0x00000002
416#define RING_REPORT_128K 0x00000004
417#define RING_NO_REPORT 0x00000000
418#define RING_VALID_MASK 0x00000001
419#define RING_VALID 0x00000001
420#define RING_INVALID 0x00000000
421
422/* Scratch pad debug 0 reg:
423 */
424#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
425/*
426 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
427 * this field (only one bit may be set).
428 */
429#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
430#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
431/* i830, required in DVO non-gang */
432#define PLL_P2_DIVIDE_BY_4 (1 << 23)
433#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
434#define PLL_REF_INPUT_DREFCLK (0 << 13)
435#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
436#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
437#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
438#define PLL_REF_INPUT_MASK (3 << 13)
439#define PLL_LOAD_PULSE_PHASE_SHIFT 9
440/*
441 * Parallel to Serial Load Pulse phase selection.
442 * Selects the phase for the 10X DPLL clock for the PCIe
443 * digital display port. The range is 4 to 13; 10 or more
444 * is just a flip delay. The default is 6
445 */
446#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
447#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
448/*
449 * SDVO multiplier for 945G/GM. Not used on 965.
450 */
451#define SDVO_MULTIPLIER_MASK 0x000000ff
452#define SDVO_MULTIPLIER_SHIFT_HIRES 4
453#define SDVO_MULTIPLIER_SHIFT_VGA 0
454#define DPLL_A_MD 0x0601c /* 965+ only */
455/*
456 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
457 *
458 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
459 */
460#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
461#define DPLL_MD_UDI_DIVIDER_SHIFT 24
462/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
463#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
464#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
465/*
466 * SDVO/UDI pixel multiplier.
467 *
468 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
469 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
470 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
471 * dummy bytes in the datastream at an increased clock rate, with both sides of
472 * the link knowing how many bytes are fill.
473 *
474 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
475 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
476 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
477 * through an SDVO command.
478 *
479 * This register field has values of multiplication factor minus 1, with
480 * a maximum multiplier of 5 for SDVO.
481 */
482#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
483#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
484/*
485 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
486 * This best be set to the default value (3) or the CRT won't work. No,
487 * I don't entirely understand what this does...
488 */
489#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
490#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
491#define DPLL_B_MD 0x06020 /* 965+ only */
492#define FPA0 0x06040
493#define FPA1 0x06044
494#define FPB0 0x06048
495#define FPB1 0x0604c
496#define FP_N_DIV_MASK 0x003f0000
497#define FP_N_DIV_SHIFT 16
498#define FP_M1_DIV_MASK 0x00003f00
499#define FP_M1_DIV_SHIFT 8
500#define FP_M2_DIV_MASK 0x0000003f
501#define FP_M2_DIV_SHIFT 0
502#define DPLL_TEST 0x606c
503#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
504#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
505#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
506#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
507#define DPLLB_TEST_N_BYPASS (1 << 19)
508#define DPLLB_TEST_M_BYPASS (1 << 18)
509#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
510#define DPLLA_TEST_N_BYPASS (1 << 3)
511#define DPLLA_TEST_M_BYPASS (1 << 2)
512#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
513#define D_STATE 0x6104
514#define CG_2D_DIS 0x6200
515#define CG_3D_DIS 0x6204
516
517/*
518 * Palette regs
519 */
520
521#define PALETTE_A 0x0a000
522#define PALETTE_B 0x0a800
523
Eric Anholt673a3942008-07-30 12:06:12 -0700524/* MCH MMIO space */
525
526/*
527 * MCHBAR mirror.
528 *
529 * This mirrors the MCHBAR MMIO space whose location is determined by
530 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
531 * every way. It is not accessible from the CP register read instructions.
532 *
533 */
534#define MCHBAR_MIRROR_BASE 0x10000
535
536/** 915-945 and GM965 MCH register controlling DRAM channel access */
537#define DCC 0x10200
538#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
539#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
540#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
541#define DCC_ADDRESSING_MODE_MASK (3 << 0)
542#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -0800543#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -0700544
545/** 965 MCH register controlling DRAM channel configuration */
546#define C0DRB3 0x10206
547#define C1DRB3 0x10606
548
Keith Packard881ee982008-11-02 23:08:44 -0800549/** GM965 GM45 render standby register */
550#define MCHBAR_RENDER_STANDBY 0x111B8
551
Jesse Barnes585fb112008-07-29 11:54:06 -0700552/*
553 * Overlay regs
554 */
555
556#define OVADD 0x30000
557#define DOVSTA 0x30008
558#define OC_BUF (0x3<<20)
559#define OGAMC5 0x30010
560#define OGAMC4 0x30014
561#define OGAMC3 0x30018
562#define OGAMC2 0x3001c
563#define OGAMC1 0x30020
564#define OGAMC0 0x30024
565
566/*
567 * Display engine regs
568 */
569
570/* Pipe A timing regs */
571#define HTOTAL_A 0x60000
572#define HBLANK_A 0x60004
573#define HSYNC_A 0x60008
574#define VTOTAL_A 0x6000c
575#define VBLANK_A 0x60010
576#define VSYNC_A 0x60014
577#define PIPEASRC 0x6001c
578#define BCLRPAT_A 0x60020
579
580/* Pipe B timing regs */
581#define HTOTAL_B 0x61000
582#define HBLANK_B 0x61004
583#define HSYNC_B 0x61008
584#define VTOTAL_B 0x6100c
585#define VBLANK_B 0x61010
586#define VSYNC_B 0x61014
587#define PIPEBSRC 0x6101c
588#define BCLRPAT_B 0x61020
589
590/* VGA port control */
591#define ADPA 0x61100
592#define ADPA_DAC_ENABLE (1<<31)
593#define ADPA_DAC_DISABLE 0
594#define ADPA_PIPE_SELECT_MASK (1<<30)
595#define ADPA_PIPE_A_SELECT 0
596#define ADPA_PIPE_B_SELECT (1<<30)
597#define ADPA_USE_VGA_HVPOLARITY (1<<15)
598#define ADPA_SETS_HVPOLARITY 0
599#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
600#define ADPA_VSYNC_CNTL_ENABLE 0
601#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
602#define ADPA_HSYNC_CNTL_ENABLE 0
603#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
604#define ADPA_VSYNC_ACTIVE_LOW 0
605#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
606#define ADPA_HSYNC_ACTIVE_LOW 0
607#define ADPA_DPMS_MASK (~(3<<10))
608#define ADPA_DPMS_ON (0<<10)
609#define ADPA_DPMS_SUSPEND (1<<10)
610#define ADPA_DPMS_STANDBY (2<<10)
611#define ADPA_DPMS_OFF (3<<10)
612
613/* Hotplug control (945+ only) */
614#define PORT_HOTPLUG_EN 0x61110
615#define SDVOB_HOTPLUG_INT_EN (1 << 26)
616#define SDVOC_HOTPLUG_INT_EN (1 << 25)
617#define TV_HOTPLUG_INT_EN (1 << 18)
618#define CRT_HOTPLUG_INT_EN (1 << 9)
619#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
620
621#define PORT_HOTPLUG_STAT 0x61114
622#define CRT_HOTPLUG_INT_STATUS (1 << 11)
623#define TV_HOTPLUG_INT_STATUS (1 << 10)
624#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
625#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
626#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
627#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
628#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
629#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
630
631/* SDVO port control */
632#define SDVOB 0x61140
633#define SDVOC 0x61160
634#define SDVO_ENABLE (1 << 31)
635#define SDVO_PIPE_B_SELECT (1 << 30)
636#define SDVO_STALL_SELECT (1 << 29)
637#define SDVO_INTERRUPT_ENABLE (1 << 26)
638/**
639 * 915G/GM SDVO pixel multiplier.
640 *
641 * Programmed value is multiplier - 1, up to 5x.
642 *
643 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
644 */
645#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
646#define SDVO_PORT_MULTIPLY_SHIFT 23
647#define SDVO_PHASE_SELECT_MASK (15 << 19)
648#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
649#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
650#define SDVOC_GANG_MODE (1 << 16)
651#define SDVO_BORDER_ENABLE (1 << 7)
652#define SDVOB_PCIE_CONCURRENCY (1 << 3)
653#define SDVO_DETECTED (1 << 2)
654/* Bits to be preserved when writing */
655#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
656#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
657
658/* DVO port control */
659#define DVOA 0x61120
660#define DVOB 0x61140
661#define DVOC 0x61160
662#define DVO_ENABLE (1 << 31)
663#define DVO_PIPE_B_SELECT (1 << 30)
664#define DVO_PIPE_STALL_UNUSED (0 << 28)
665#define DVO_PIPE_STALL (1 << 28)
666#define DVO_PIPE_STALL_TV (2 << 28)
667#define DVO_PIPE_STALL_MASK (3 << 28)
668#define DVO_USE_VGA_SYNC (1 << 15)
669#define DVO_DATA_ORDER_I740 (0 << 14)
670#define DVO_DATA_ORDER_FP (1 << 14)
671#define DVO_VSYNC_DISABLE (1 << 11)
672#define DVO_HSYNC_DISABLE (1 << 10)
673#define DVO_VSYNC_TRISTATE (1 << 9)
674#define DVO_HSYNC_TRISTATE (1 << 8)
675#define DVO_BORDER_ENABLE (1 << 7)
676#define DVO_DATA_ORDER_GBRG (1 << 6)
677#define DVO_DATA_ORDER_RGGB (0 << 6)
678#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
679#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
680#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
681#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
682#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
683#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
684#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
685#define DVO_PRESERVE_MASK (0x7<<24)
686#define DVOA_SRCDIM 0x61124
687#define DVOB_SRCDIM 0x61144
688#define DVOC_SRCDIM 0x61164
689#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
690#define DVO_SRCDIM_VERTICAL_SHIFT 0
691
692/* LVDS port control */
693#define LVDS 0x61180
694/*
695 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
696 * the DPLL semantics change when the LVDS is assigned to that pipe.
697 */
698#define LVDS_PORT_EN (1 << 31)
699/* Selects pipe B for LVDS data. Must be set on pre-965. */
700#define LVDS_PIPEB_SELECT (1 << 30)
701/*
702 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
703 * pixel.
704 */
705#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
706#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
707#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
708/*
709 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
710 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
711 * on.
712 */
713#define LVDS_A3_POWER_MASK (3 << 6)
714#define LVDS_A3_POWER_DOWN (0 << 6)
715#define LVDS_A3_POWER_UP (3 << 6)
716/*
717 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
718 * is set.
719 */
720#define LVDS_CLKB_POWER_MASK (3 << 4)
721#define LVDS_CLKB_POWER_DOWN (0 << 4)
722#define LVDS_CLKB_POWER_UP (3 << 4)
723/*
724 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
725 * setting for whether we are in dual-channel mode. The B3 pair will
726 * additionally only be powered up when LVDS_A3_POWER_UP is set.
727 */
728#define LVDS_B0B3_POWER_MASK (3 << 2)
729#define LVDS_B0B3_POWER_DOWN (0 << 2)
730#define LVDS_B0B3_POWER_UP (3 << 2)
731
732/* Panel power sequencing */
733#define PP_STATUS 0x61200
734#define PP_ON (1 << 31)
735/*
736 * Indicates that all dependencies of the panel are on:
737 *
738 * - PLL enabled
739 * - pipe enabled
740 * - LVDS/DVOB/DVOC on
741 */
742#define PP_READY (1 << 30)
743#define PP_SEQUENCE_NONE (0 << 28)
744#define PP_SEQUENCE_ON (1 << 28)
745#define PP_SEQUENCE_OFF (2 << 28)
746#define PP_SEQUENCE_MASK 0x30000000
747#define PP_CONTROL 0x61204
748#define POWER_TARGET_ON (1 << 0)
749#define PP_ON_DELAYS 0x61208
750#define PP_OFF_DELAYS 0x6120c
751#define PP_DIVISOR 0x61210
752
753/* Panel fitting */
754#define PFIT_CONTROL 0x61230
755#define PFIT_ENABLE (1 << 31)
756#define PFIT_PIPE_MASK (3 << 29)
757#define PFIT_PIPE_SHIFT 29
758#define VERT_INTERP_DISABLE (0 << 10)
759#define VERT_INTERP_BILINEAR (1 << 10)
760#define VERT_INTERP_MASK (3 << 10)
761#define VERT_AUTO_SCALE (1 << 9)
762#define HORIZ_INTERP_DISABLE (0 << 6)
763#define HORIZ_INTERP_BILINEAR (1 << 6)
764#define HORIZ_INTERP_MASK (3 << 6)
765#define HORIZ_AUTO_SCALE (1 << 5)
766#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
767#define PFIT_PGM_RATIOS 0x61234
768#define PFIT_VERT_SCALE_MASK 0xfff00000
769#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
770#define PFIT_AUTO_RATIOS 0x61238
771
772/* Backlight control */
773#define BLC_PWM_CTL 0x61254
774#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
775#define BLC_PWM_CTL2 0x61250 /* 965+ only */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100776#define BLM_COMBINATION_MODE (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -0700777/*
778 * This is the most significant 15 bits of the number of backlight cycles in a
779 * complete cycle of the modulated backlight control.
780 *
781 * The actual value is this field multiplied by two.
782 */
783#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
784#define BLM_LEGACY_MODE (1 << 16)
785/*
786 * This is the number of cycles out of the backlight modulation cycle for which
787 * the backlight is on.
788 *
789 * This field must be no greater than the number of cycles in the complete
790 * backlight modulation cycle.
791 */
792#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
793#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
794
795/* TV port control */
796#define TV_CTL 0x68000
797/** Enables the TV encoder */
798# define TV_ENC_ENABLE (1 << 31)
799/** Sources the TV encoder input from pipe B instead of A. */
800# define TV_ENC_PIPEB_SELECT (1 << 30)
801/** Outputs composite video (DAC A only) */
802# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
803/** Outputs SVideo video (DAC B/C) */
804# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
805/** Outputs Component video (DAC A/B/C) */
806# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
807/** Outputs Composite and SVideo (DAC A/B/C) */
808# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
809# define TV_TRILEVEL_SYNC (1 << 21)
810/** Enables slow sync generation (945GM only) */
811# define TV_SLOW_SYNC (1 << 20)
812/** Selects 4x oversampling for 480i and 576p */
813# define TV_OVERSAMPLE_4X (0 << 18)
814/** Selects 2x oversampling for 720p and 1080i */
815# define TV_OVERSAMPLE_2X (1 << 18)
816/** Selects no oversampling for 1080p */
817# define TV_OVERSAMPLE_NONE (2 << 18)
818/** Selects 8x oversampling */
819# define TV_OVERSAMPLE_8X (3 << 18)
820/** Selects progressive mode rather than interlaced */
821# define TV_PROGRESSIVE (1 << 17)
822/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
823# define TV_PAL_BURST (1 << 16)
824/** Field for setting delay of Y compared to C */
825# define TV_YC_SKEW_MASK (7 << 12)
826/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
827# define TV_ENC_SDP_FIX (1 << 11)
828/**
829 * Enables a fix for the 915GM only.
830 *
831 * Not sure what it does.
832 */
833# define TV_ENC_C0_FIX (1 << 10)
834/** Bits that must be preserved by software */
835# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
836# define TV_FUSE_STATE_MASK (3 << 4)
837/** Read-only state that reports all features enabled */
838# define TV_FUSE_STATE_ENABLED (0 << 4)
839/** Read-only state that reports that Macrovision is disabled in hardware*/
840# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
841/** Read-only state that reports that TV-out is disabled in hardware. */
842# define TV_FUSE_STATE_DISABLED (2 << 4)
843/** Normal operation */
844# define TV_TEST_MODE_NORMAL (0 << 0)
845/** Encoder test pattern 1 - combo pattern */
846# define TV_TEST_MODE_PATTERN_1 (1 << 0)
847/** Encoder test pattern 2 - full screen vertical 75% color bars */
848# define TV_TEST_MODE_PATTERN_2 (2 << 0)
849/** Encoder test pattern 3 - full screen horizontal 75% color bars */
850# define TV_TEST_MODE_PATTERN_3 (3 << 0)
851/** Encoder test pattern 4 - random noise */
852# define TV_TEST_MODE_PATTERN_4 (4 << 0)
853/** Encoder test pattern 5 - linear color ramps */
854# define TV_TEST_MODE_PATTERN_5 (5 << 0)
855/**
856 * This test mode forces the DACs to 50% of full output.
857 *
858 * This is used for load detection in combination with TVDAC_SENSE_MASK
859 */
860# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
861# define TV_TEST_MODE_MASK (7 << 0)
862
863#define TV_DAC 0x68004
864/**
865 * Reports that DAC state change logic has reported change (RO).
866 *
867 * This gets cleared when TV_DAC_STATE_EN is cleared
868*/
869# define TVDAC_STATE_CHG (1 << 31)
870# define TVDAC_SENSE_MASK (7 << 28)
871/** Reports that DAC A voltage is above the detect threshold */
872# define TVDAC_A_SENSE (1 << 30)
873/** Reports that DAC B voltage is above the detect threshold */
874# define TVDAC_B_SENSE (1 << 29)
875/** Reports that DAC C voltage is above the detect threshold */
876# define TVDAC_C_SENSE (1 << 28)
877/**
878 * Enables DAC state detection logic, for load-based TV detection.
879 *
880 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
881 * to off, for load detection to work.
882 */
883# define TVDAC_STATE_CHG_EN (1 << 27)
884/** Sets the DAC A sense value to high */
885# define TVDAC_A_SENSE_CTL (1 << 26)
886/** Sets the DAC B sense value to high */
887# define TVDAC_B_SENSE_CTL (1 << 25)
888/** Sets the DAC C sense value to high */
889# define TVDAC_C_SENSE_CTL (1 << 24)
890/** Overrides the ENC_ENABLE and DAC voltage levels */
891# define DAC_CTL_OVERRIDE (1 << 7)
892/** Sets the slew rate. Must be preserved in software */
893# define ENC_TVDAC_SLEW_FAST (1 << 6)
894# define DAC_A_1_3_V (0 << 4)
895# define DAC_A_1_1_V (1 << 4)
896# define DAC_A_0_7_V (2 << 4)
897# define DAC_A_OFF (3 << 4)
898# define DAC_B_1_3_V (0 << 2)
899# define DAC_B_1_1_V (1 << 2)
900# define DAC_B_0_7_V (2 << 2)
901# define DAC_B_OFF (3 << 2)
902# define DAC_C_1_3_V (0 << 0)
903# define DAC_C_1_1_V (1 << 0)
904# define DAC_C_0_7_V (2 << 0)
905# define DAC_C_OFF (3 << 0)
906
907/**
908 * CSC coefficients are stored in a floating point format with 9 bits of
909 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
910 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
911 * -1 (0x3) being the only legal negative value.
912 */
913#define TV_CSC_Y 0x68010
914# define TV_RY_MASK 0x07ff0000
915# define TV_RY_SHIFT 16
916# define TV_GY_MASK 0x00000fff
917# define TV_GY_SHIFT 0
918
919#define TV_CSC_Y2 0x68014
920# define TV_BY_MASK 0x07ff0000
921# define TV_BY_SHIFT 16
922/**
923 * Y attenuation for component video.
924 *
925 * Stored in 1.9 fixed point.
926 */
927# define TV_AY_MASK 0x000003ff
928# define TV_AY_SHIFT 0
929
930#define TV_CSC_U 0x68018
931# define TV_RU_MASK 0x07ff0000
932# define TV_RU_SHIFT 16
933# define TV_GU_MASK 0x000007ff
934# define TV_GU_SHIFT 0
935
936#define TV_CSC_U2 0x6801c
937# define TV_BU_MASK 0x07ff0000
938# define TV_BU_SHIFT 16
939/**
940 * U attenuation for component video.
941 *
942 * Stored in 1.9 fixed point.
943 */
944# define TV_AU_MASK 0x000003ff
945# define TV_AU_SHIFT 0
946
947#define TV_CSC_V 0x68020
948# define TV_RV_MASK 0x0fff0000
949# define TV_RV_SHIFT 16
950# define TV_GV_MASK 0x000007ff
951# define TV_GV_SHIFT 0
952
953#define TV_CSC_V2 0x68024
954# define TV_BV_MASK 0x07ff0000
955# define TV_BV_SHIFT 16
956/**
957 * V attenuation for component video.
958 *
959 * Stored in 1.9 fixed point.
960 */
961# define TV_AV_MASK 0x000007ff
962# define TV_AV_SHIFT 0
963
964#define TV_CLR_KNOBS 0x68028
965/** 2s-complement brightness adjustment */
966# define TV_BRIGHTNESS_MASK 0xff000000
967# define TV_BRIGHTNESS_SHIFT 24
968/** Contrast adjustment, as a 2.6 unsigned floating point number */
969# define TV_CONTRAST_MASK 0x00ff0000
970# define TV_CONTRAST_SHIFT 16
971/** Saturation adjustment, as a 2.6 unsigned floating point number */
972# define TV_SATURATION_MASK 0x0000ff00
973# define TV_SATURATION_SHIFT 8
974/** Hue adjustment, as an integer phase angle in degrees */
975# define TV_HUE_MASK 0x000000ff
976# define TV_HUE_SHIFT 0
977
978#define TV_CLR_LEVEL 0x6802c
979/** Controls the DAC level for black */
980# define TV_BLACK_LEVEL_MASK 0x01ff0000
981# define TV_BLACK_LEVEL_SHIFT 16
982/** Controls the DAC level for blanking */
983# define TV_BLANK_LEVEL_MASK 0x000001ff
984# define TV_BLANK_LEVEL_SHIFT 0
985
986#define TV_H_CTL_1 0x68030
987/** Number of pixels in the hsync. */
988# define TV_HSYNC_END_MASK 0x1fff0000
989# define TV_HSYNC_END_SHIFT 16
990/** Total number of pixels minus one in the line (display and blanking). */
991# define TV_HTOTAL_MASK 0x00001fff
992# define TV_HTOTAL_SHIFT 0
993
994#define TV_H_CTL_2 0x68034
995/** Enables the colorburst (needed for non-component color) */
996# define TV_BURST_ENA (1 << 31)
997/** Offset of the colorburst from the start of hsync, in pixels minus one. */
998# define TV_HBURST_START_SHIFT 16
999# define TV_HBURST_START_MASK 0x1fff0000
1000/** Length of the colorburst */
1001# define TV_HBURST_LEN_SHIFT 0
1002# define TV_HBURST_LEN_MASK 0x0001fff
1003
1004#define TV_H_CTL_3 0x68038
1005/** End of hblank, measured in pixels minus one from start of hsync */
1006# define TV_HBLANK_END_SHIFT 16
1007# define TV_HBLANK_END_MASK 0x1fff0000
1008/** Start of hblank, measured in pixels minus one from start of hsync */
1009# define TV_HBLANK_START_SHIFT 0
1010# define TV_HBLANK_START_MASK 0x0001fff
1011
1012#define TV_V_CTL_1 0x6803c
1013/** XXX */
1014# define TV_NBR_END_SHIFT 16
1015# define TV_NBR_END_MASK 0x07ff0000
1016/** XXX */
1017# define TV_VI_END_F1_SHIFT 8
1018# define TV_VI_END_F1_MASK 0x00003f00
1019/** XXX */
1020# define TV_VI_END_F2_SHIFT 0
1021# define TV_VI_END_F2_MASK 0x0000003f
1022
1023#define TV_V_CTL_2 0x68040
1024/** Length of vsync, in half lines */
1025# define TV_VSYNC_LEN_MASK 0x07ff0000
1026# define TV_VSYNC_LEN_SHIFT 16
1027/** Offset of the start of vsync in field 1, measured in one less than the
1028 * number of half lines.
1029 */
1030# define TV_VSYNC_START_F1_MASK 0x00007f00
1031# define TV_VSYNC_START_F1_SHIFT 8
1032/**
1033 * Offset of the start of vsync in field 2, measured in one less than the
1034 * number of half lines.
1035 */
1036# define TV_VSYNC_START_F2_MASK 0x0000007f
1037# define TV_VSYNC_START_F2_SHIFT 0
1038
1039#define TV_V_CTL_3 0x68044
1040/** Enables generation of the equalization signal */
1041# define TV_EQUAL_ENA (1 << 31)
1042/** Length of vsync, in half lines */
1043# define TV_VEQ_LEN_MASK 0x007f0000
1044# define TV_VEQ_LEN_SHIFT 16
1045/** Offset of the start of equalization in field 1, measured in one less than
1046 * the number of half lines.
1047 */
1048# define TV_VEQ_START_F1_MASK 0x0007f00
1049# define TV_VEQ_START_F1_SHIFT 8
1050/**
1051 * Offset of the start of equalization in field 2, measured in one less than
1052 * the number of half lines.
1053 */
1054# define TV_VEQ_START_F2_MASK 0x000007f
1055# define TV_VEQ_START_F2_SHIFT 0
1056
1057#define TV_V_CTL_4 0x68048
1058/**
1059 * Offset to start of vertical colorburst, measured in one less than the
1060 * number of lines from vertical start.
1061 */
1062# define TV_VBURST_START_F1_MASK 0x003f0000
1063# define TV_VBURST_START_F1_SHIFT 16
1064/**
1065 * Offset to the end of vertical colorburst, measured in one less than the
1066 * number of lines from the start of NBR.
1067 */
1068# define TV_VBURST_END_F1_MASK 0x000000ff
1069# define TV_VBURST_END_F1_SHIFT 0
1070
1071#define TV_V_CTL_5 0x6804c
1072/**
1073 * Offset to start of vertical colorburst, measured in one less than the
1074 * number of lines from vertical start.
1075 */
1076# define TV_VBURST_START_F2_MASK 0x003f0000
1077# define TV_VBURST_START_F2_SHIFT 16
1078/**
1079 * Offset to the end of vertical colorburst, measured in one less than the
1080 * number of lines from the start of NBR.
1081 */
1082# define TV_VBURST_END_F2_MASK 0x000000ff
1083# define TV_VBURST_END_F2_SHIFT 0
1084
1085#define TV_V_CTL_6 0x68050
1086/**
1087 * Offset to start of vertical colorburst, measured in one less than the
1088 * number of lines from vertical start.
1089 */
1090# define TV_VBURST_START_F3_MASK 0x003f0000
1091# define TV_VBURST_START_F3_SHIFT 16
1092/**
1093 * Offset to the end of vertical colorburst, measured in one less than the
1094 * number of lines from the start of NBR.
1095 */
1096# define TV_VBURST_END_F3_MASK 0x000000ff
1097# define TV_VBURST_END_F3_SHIFT 0
1098
1099#define TV_V_CTL_7 0x68054
1100/**
1101 * Offset to start of vertical colorburst, measured in one less than the
1102 * number of lines from vertical start.
1103 */
1104# define TV_VBURST_START_F4_MASK 0x003f0000
1105# define TV_VBURST_START_F4_SHIFT 16
1106/**
1107 * Offset to the end of vertical colorburst, measured in one less than the
1108 * number of lines from the start of NBR.
1109 */
1110# define TV_VBURST_END_F4_MASK 0x000000ff
1111# define TV_VBURST_END_F4_SHIFT 0
1112
1113#define TV_SC_CTL_1 0x68060
1114/** Turns on the first subcarrier phase generation DDA */
1115# define TV_SC_DDA1_EN (1 << 31)
1116/** Turns on the first subcarrier phase generation DDA */
1117# define TV_SC_DDA2_EN (1 << 30)
1118/** Turns on the first subcarrier phase generation DDA */
1119# define TV_SC_DDA3_EN (1 << 29)
1120/** Sets the subcarrier DDA to reset frequency every other field */
1121# define TV_SC_RESET_EVERY_2 (0 << 24)
1122/** Sets the subcarrier DDA to reset frequency every fourth field */
1123# define TV_SC_RESET_EVERY_4 (1 << 24)
1124/** Sets the subcarrier DDA to reset frequency every eighth field */
1125# define TV_SC_RESET_EVERY_8 (2 << 24)
1126/** Sets the subcarrier DDA to never reset the frequency */
1127# define TV_SC_RESET_NEVER (3 << 24)
1128/** Sets the peak amplitude of the colorburst.*/
1129# define TV_BURST_LEVEL_MASK 0x00ff0000
1130# define TV_BURST_LEVEL_SHIFT 16
1131/** Sets the increment of the first subcarrier phase generation DDA */
1132# define TV_SCDDA1_INC_MASK 0x00000fff
1133# define TV_SCDDA1_INC_SHIFT 0
1134
1135#define TV_SC_CTL_2 0x68064
1136/** Sets the rollover for the second subcarrier phase generation DDA */
1137# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1138# define TV_SCDDA2_SIZE_SHIFT 16
1139/** Sets the increent of the second subcarrier phase generation DDA */
1140# define TV_SCDDA2_INC_MASK 0x00007fff
1141# define TV_SCDDA2_INC_SHIFT 0
1142
1143#define TV_SC_CTL_3 0x68068
1144/** Sets the rollover for the third subcarrier phase generation DDA */
1145# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1146# define TV_SCDDA3_SIZE_SHIFT 16
1147/** Sets the increent of the third subcarrier phase generation DDA */
1148# define TV_SCDDA3_INC_MASK 0x00007fff
1149# define TV_SCDDA3_INC_SHIFT 0
1150
1151#define TV_WIN_POS 0x68070
1152/** X coordinate of the display from the start of horizontal active */
1153# define TV_XPOS_MASK 0x1fff0000
1154# define TV_XPOS_SHIFT 16
1155/** Y coordinate of the display from the start of vertical active (NBR) */
1156# define TV_YPOS_MASK 0x00000fff
1157# define TV_YPOS_SHIFT 0
1158
1159#define TV_WIN_SIZE 0x68074
1160/** Horizontal size of the display window, measured in pixels*/
1161# define TV_XSIZE_MASK 0x1fff0000
1162# define TV_XSIZE_SHIFT 16
1163/**
1164 * Vertical size of the display window, measured in pixels.
1165 *
1166 * Must be even for interlaced modes.
1167 */
1168# define TV_YSIZE_MASK 0x00000fff
1169# define TV_YSIZE_SHIFT 0
1170
1171#define TV_FILTER_CTL_1 0x68080
1172/**
1173 * Enables automatic scaling calculation.
1174 *
1175 * If set, the rest of the registers are ignored, and the calculated values can
1176 * be read back from the register.
1177 */
1178# define TV_AUTO_SCALE (1 << 31)
1179/**
1180 * Disables the vertical filter.
1181 *
1182 * This is required on modes more than 1024 pixels wide */
1183# define TV_V_FILTER_BYPASS (1 << 29)
1184/** Enables adaptive vertical filtering */
1185# define TV_VADAPT (1 << 28)
1186# define TV_VADAPT_MODE_MASK (3 << 26)
1187/** Selects the least adaptive vertical filtering mode */
1188# define TV_VADAPT_MODE_LEAST (0 << 26)
1189/** Selects the moderately adaptive vertical filtering mode */
1190# define TV_VADAPT_MODE_MODERATE (1 << 26)
1191/** Selects the most adaptive vertical filtering mode */
1192# define TV_VADAPT_MODE_MOST (3 << 26)
1193/**
1194 * Sets the horizontal scaling factor.
1195 *
1196 * This should be the fractional part of the horizontal scaling factor divided
1197 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1198 *
1199 * (src width - 1) / ((oversample * dest width) - 1)
1200 */
1201# define TV_HSCALE_FRAC_MASK 0x00003fff
1202# define TV_HSCALE_FRAC_SHIFT 0
1203
1204#define TV_FILTER_CTL_2 0x68084
1205/**
1206 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1207 *
1208 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1209 */
1210# define TV_VSCALE_INT_MASK 0x00038000
1211# define TV_VSCALE_INT_SHIFT 15
1212/**
1213 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1214 *
1215 * \sa TV_VSCALE_INT_MASK
1216 */
1217# define TV_VSCALE_FRAC_MASK 0x00007fff
1218# define TV_VSCALE_FRAC_SHIFT 0
1219
1220#define TV_FILTER_CTL_3 0x68088
1221/**
1222 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1223 *
1224 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1225 *
1226 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1227 */
1228# define TV_VSCALE_IP_INT_MASK 0x00038000
1229# define TV_VSCALE_IP_INT_SHIFT 15
1230/**
1231 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1232 *
1233 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1234 *
1235 * \sa TV_VSCALE_IP_INT_MASK
1236 */
1237# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1238# define TV_VSCALE_IP_FRAC_SHIFT 0
1239
1240#define TV_CC_CONTROL 0x68090
1241# define TV_CC_ENABLE (1 << 31)
1242/**
1243 * Specifies which field to send the CC data in.
1244 *
1245 * CC data is usually sent in field 0.
1246 */
1247# define TV_CC_FID_MASK (1 << 27)
1248# define TV_CC_FID_SHIFT 27
1249/** Sets the horizontal position of the CC data. Usually 135. */
1250# define TV_CC_HOFF_MASK 0x03ff0000
1251# define TV_CC_HOFF_SHIFT 16
1252/** Sets the vertical position of the CC data. Usually 21 */
1253# define TV_CC_LINE_MASK 0x0000003f
1254# define TV_CC_LINE_SHIFT 0
1255
1256#define TV_CC_DATA 0x68094
1257# define TV_CC_RDY (1 << 31)
1258/** Second word of CC data to be transmitted. */
1259# define TV_CC_DATA_2_MASK 0x007f0000
1260# define TV_CC_DATA_2_SHIFT 16
1261/** First word of CC data to be transmitted. */
1262# define TV_CC_DATA_1_MASK 0x0000007f
1263# define TV_CC_DATA_1_SHIFT 0
1264
1265#define TV_H_LUMA_0 0x68100
1266#define TV_H_LUMA_59 0x681ec
1267#define TV_H_CHROMA_0 0x68200
1268#define TV_H_CHROMA_59 0x682ec
1269#define TV_V_LUMA_0 0x68300
1270#define TV_V_LUMA_42 0x683a8
1271#define TV_V_CHROMA_0 0x68400
1272#define TV_V_CHROMA_42 0x684a8
1273
1274/* Display & cursor control */
1275
1276/* Pipe A */
1277#define PIPEADSL 0x70000
1278#define PIPEACONF 0x70008
1279#define PIPEACONF_ENABLE (1<<31)
1280#define PIPEACONF_DISABLE 0
1281#define PIPEACONF_DOUBLE_WIDE (1<<30)
1282#define I965_PIPECONF_ACTIVE (1<<30)
1283#define PIPEACONF_SINGLE_WIDE 0
1284#define PIPEACONF_PIPE_UNLOCKED 0
1285#define PIPEACONF_PIPE_LOCKED (1<<25)
1286#define PIPEACONF_PALETTE 0
1287#define PIPEACONF_GAMMA (1<<24)
1288#define PIPECONF_FORCE_BORDER (1<<25)
1289#define PIPECONF_PROGRESSIVE (0 << 21)
1290#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1291#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1292#define PIPEASTAT 0x70024
1293#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1294#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1295#define PIPE_CRC_DONE_ENABLE (1UL<<28)
1296#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1297#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1298#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1299#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1300#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1301#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1302#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1303#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1304#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1305#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1306#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1307#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1308#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1309#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1310#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1311#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1312#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1313#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1314#define PIPE_DPST_EVENT_STATUS (1UL<<7)
1315#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1316#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1317#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1318#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1319#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1320#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1321#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1322
1323#define DSPARB 0x70030
1324#define DSPARB_CSTART_MASK (0x7f << 7)
1325#define DSPARB_CSTART_SHIFT 7
1326#define DSPARB_BSTART_MASK (0x7f)
1327#define DSPARB_BSTART_SHIFT 0
1328/*
1329 * The two pipe frame counter registers are not synchronized, so
1330 * reading a stable value is somewhat tricky. The following code
1331 * should work:
1332 *
1333 * do {
1334 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1335 * PIPE_FRAME_HIGH_SHIFT;
1336 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1337 * PIPE_FRAME_LOW_SHIFT);
1338 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1339 * PIPE_FRAME_HIGH_SHIFT);
1340 * } while (high1 != high2);
1341 * frame = (high1 << 8) | low1;
1342 */
1343#define PIPEAFRAMEHIGH 0x70040
1344#define PIPE_FRAME_HIGH_MASK 0x0000ffff
1345#define PIPE_FRAME_HIGH_SHIFT 0
1346#define PIPEAFRAMEPIXEL 0x70044
1347#define PIPE_FRAME_LOW_MASK 0xff000000
1348#define PIPE_FRAME_LOW_SHIFT 24
1349#define PIPE_PIXEL_MASK 0x00ffffff
1350#define PIPE_PIXEL_SHIFT 0
1351
1352/* Cursor A & B regs */
1353#define CURACNTR 0x70080
1354#define CURSOR_MODE_DISABLE 0x00
1355#define CURSOR_MODE_64_32B_AX 0x07
1356#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1357#define MCURSOR_GAMMA_ENABLE (1 << 26)
1358#define CURABASE 0x70084
1359#define CURAPOS 0x70088
1360#define CURSOR_POS_MASK 0x007FF
1361#define CURSOR_POS_SIGN 0x8000
1362#define CURSOR_X_SHIFT 0
1363#define CURSOR_Y_SHIFT 16
1364#define CURBCNTR 0x700c0
1365#define CURBBASE 0x700c4
1366#define CURBPOS 0x700c8
1367
1368/* Display A control */
1369#define DSPACNTR 0x70180
1370#define DISPLAY_PLANE_ENABLE (1<<31)
1371#define DISPLAY_PLANE_DISABLE 0
1372#define DISPPLANE_GAMMA_ENABLE (1<<30)
1373#define DISPPLANE_GAMMA_DISABLE 0
1374#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1375#define DISPPLANE_8BPP (0x2<<26)
1376#define DISPPLANE_15_16BPP (0x4<<26)
1377#define DISPPLANE_16BPP (0x5<<26)
1378#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1379#define DISPPLANE_32BPP (0x7<<26)
1380#define DISPPLANE_STEREO_ENABLE (1<<25)
1381#define DISPPLANE_STEREO_DISABLE 0
1382#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1383#define DISPPLANE_SEL_PIPE_A 0
1384#define DISPPLANE_SEL_PIPE_B (1<<24)
1385#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1386#define DISPPLANE_SRC_KEY_DISABLE 0
1387#define DISPPLANE_LINE_DOUBLE (1<<20)
1388#define DISPPLANE_NO_LINE_DOUBLE 0
1389#define DISPPLANE_STEREO_POLARITY_FIRST 0
1390#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1391#define DSPAADDR 0x70184
1392#define DSPASTRIDE 0x70188
1393#define DSPAPOS 0x7018C /* reserved */
1394#define DSPASIZE 0x70190
1395#define DSPASURF 0x7019C /* 965+ only */
1396#define DSPATILEOFF 0x701A4 /* 965+ only */
1397
1398/* VBIOS flags */
1399#define SWF00 0x71410
1400#define SWF01 0x71414
1401#define SWF02 0x71418
1402#define SWF03 0x7141c
1403#define SWF04 0x71420
1404#define SWF05 0x71424
1405#define SWF06 0x71428
1406#define SWF10 0x70410
1407#define SWF11 0x70414
1408#define SWF14 0x71420
1409#define SWF30 0x72414
1410#define SWF31 0x72418
1411#define SWF32 0x7241c
1412
1413/* Pipe B */
1414#define PIPEBDSL 0x71000
1415#define PIPEBCONF 0x71008
1416#define PIPEBSTAT 0x71024
1417#define PIPEBFRAMEHIGH 0x71040
1418#define PIPEBFRAMEPIXEL 0x71044
1419
1420/* Display B control */
1421#define DSPBCNTR 0x71180
1422#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1423#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1424#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1425#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1426#define DSPBADDR 0x71184
1427#define DSPBSTRIDE 0x71188
1428#define DSPBPOS 0x7118C
1429#define DSPBSIZE 0x71190
1430#define DSPBSURF 0x7119C
1431#define DSPBTILEOFF 0x711A4
1432
1433/* VBIOS regs */
1434#define VGACNTRL 0x71400
1435# define VGA_DISP_DISABLE (1 << 31)
1436# define VGA_2X_MODE (1 << 30)
1437# define VGA_PIPE_B_SELECT (1 << 29)
1438
1439#endif /* _I915_REG_H_ */