Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1999 ARM Limited |
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
Ilya Yanok | 74bef9a | 2009-03-03 02:49:23 +0300 | [diff] [blame] | 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/io.h> |
Ilya Yanok | 74bef9a | 2009-03-03 02:49:23 +0300 | [diff] [blame] | 22 | #include <linux/err.h> |
| 23 | #include <linux/delay.h> |
Shawn Guo | c1e31d1 | 2013-05-10 10:19:01 +0800 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 26 | |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 27 | #include <asm/system_misc.h> |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 28 | #include <asm/proc-fns.h> |
Arnaud Patard (Rtp) | c2932bf | 2010-10-27 14:40:55 +0200 | [diff] [blame] | 29 | #include <asm/mach-types.h> |
Shawn Guo | e6a0756 | 2013-07-08 21:45:20 +0800 | [diff] [blame] | 30 | #include <asm/hardware/cache-l2x0.h> |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 31 | |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 32 | #include "common.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 33 | #include "hardware.h" |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 34 | |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 35 | static void __iomem *wdog_base; |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 36 | static struct clk *wdog_clk; |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * Reset the system. It is called by machine_restart(). |
| 40 | */ |
Robin Holt | 7b6d864 | 2013-07-08 16:01:40 -0700 | [diff] [blame] | 41 | void mxc_restart(enum reboot_mode mode, const char *cmd) |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 42 | { |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 43 | unsigned int wcr_enable; |
| 44 | |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 45 | if (wdog_clk) |
| 46 | clk_enable(wdog_clk); |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 47 | |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 48 | if (cpu_is_mx1()) |
| 49 | wcr_enable = (1 << 0); |
| 50 | else |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 51 | wcr_enable = (1 << 2); |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 52 | |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 53 | /* Assert SRS signal */ |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 54 | __raw_writew(wcr_enable, wdog_base); |
Ilya Yanok | 74bef9a | 2009-03-03 02:49:23 +0300 | [diff] [blame] | 55 | |
| 56 | /* wait for reset to assert... */ |
| 57 | mdelay(500); |
| 58 | |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 59 | pr_err("%s: Watchdog reset failed to assert reset\n", __func__); |
Ilya Yanok | 74bef9a | 2009-03-03 02:49:23 +0300 | [diff] [blame] | 60 | |
| 61 | /* delay to allow the serial port to show the message */ |
| 62 | mdelay(50); |
| 63 | |
| 64 | /* we'll take a jump through zero as a poor second */ |
Russell King | e879c86 | 2011-11-01 13:16:26 +0000 | [diff] [blame] | 65 | soft_restart(0); |
Juergen Beisert | eea643f | 2008-07-05 10:02:56 +0200 | [diff] [blame] | 66 | } |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 67 | |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 68 | void __init mxc_arch_reset_init(void __iomem *base) |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 69 | { |
| 70 | wdog_base = base; |
Shawn Guo | 18cb680 | 2013-05-10 09:13:44 +0800 | [diff] [blame] | 71 | |
| 72 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); |
| 73 | if (IS_ERR(wdog_clk)) { |
| 74 | pr_warn("%s: failed to get wdog clock\n", __func__); |
| 75 | wdog_clk = NULL; |
| 76 | return; |
| 77 | } |
| 78 | |
| 79 | clk_prepare(wdog_clk); |
Sascha Hauer | be124c9 | 2009-06-04 12:19:02 +0200 | [diff] [blame] | 80 | } |
Shawn Guo | c1e31d1 | 2013-05-10 10:19:01 +0800 | [diff] [blame] | 81 | |
| 82 | void __init mxc_arch_reset_init_dt(void) |
| 83 | { |
| 84 | struct device_node *np; |
| 85 | |
| 86 | np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt"); |
| 87 | wdog_base = of_iomap(np, 0); |
| 88 | WARN_ON(!wdog_base); |
| 89 | |
| 90 | wdog_clk = of_clk_get(np, 0); |
| 91 | if (IS_ERR(wdog_clk)) { |
| 92 | pr_warn("%s: failed to get wdog clock\n", __func__); |
| 93 | wdog_clk = NULL; |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | clk_prepare(wdog_clk); |
| 98 | } |
Shawn Guo | e6a0756 | 2013-07-08 21:45:20 +0800 | [diff] [blame] | 99 | |
| 100 | #ifdef CONFIG_CACHE_L2X0 |
Vincent Stehlé | 10eff77 | 2013-07-10 11:45:46 +0200 | [diff] [blame] | 101 | void __init imx_init_l2cache(void) |
Shawn Guo | e6a0756 | 2013-07-08 21:45:20 +0800 | [diff] [blame] | 102 | { |
| 103 | void __iomem *l2x0_base; |
| 104 | struct device_node *np; |
| 105 | unsigned int val; |
| 106 | |
| 107 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); |
| 108 | if (!np) |
| 109 | goto out; |
| 110 | |
| 111 | l2x0_base = of_iomap(np, 0); |
| 112 | if (!l2x0_base) { |
| 113 | of_node_put(np); |
| 114 | goto out; |
| 115 | } |
| 116 | |
| 117 | /* Configure the L2 PREFETCH and POWER registers */ |
| 118 | val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); |
| 119 | val |= 0x70800000; |
Jason Liu | 9779f0e | 2013-09-16 09:29:03 +0800 | [diff] [blame] | 120 | /* |
| 121 | * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 |
| 122 | * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 |
| 123 | * But according to ARM PL310 errata: 752271 |
| 124 | * ID: 752271: Double linefill feature can cause data corruption |
| 125 | * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 |
| 126 | * Workaround: The only workaround to this erratum is to disable the |
| 127 | * double linefill feature. This is the default behavior. |
| 128 | */ |
| 129 | if (cpu_is_imx6q()) |
| 130 | val &= ~(1 << 30 | 1 << 23); |
Shawn Guo | e6a0756 | 2013-07-08 21:45:20 +0800 | [diff] [blame] | 131 | writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); |
| 132 | val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; |
| 133 | writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); |
| 134 | |
| 135 | iounmap(l2x0_base); |
| 136 | of_node_put(np); |
| 137 | |
| 138 | out: |
| 139 | l2x0_of_init(0, ~0UL); |
| 140 | } |
| 141 | #endif |