Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 1 | /* |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 2 | * TQM85xx (40/41/55/60) board specific routines |
| 3 | * |
| 4 | * Copyright (c) 2005 DENX Software Engineering |
| 5 | * Stefan Roese <sr@denx.de> |
| 6 | * |
| 7 | * Based on original work by |
| 8 | * Kumar Gala <galak@kernel.crashing.org> |
| 9 | * Copyright 2004 Freescale Semiconductor Inc. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 17 | #include <linux/stddef.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/reboot.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/kdev_t.h> |
| 24 | #include <linux/major.h> |
| 25 | #include <linux/console.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/seq_file.h> |
| 28 | #include <linux/root_dev.h> |
| 29 | #include <linux/serial.h> |
| 30 | #include <linux/tty.h> /* for linux/serial_core.h */ |
| 31 | #include <linux/serial_core.h> |
| 32 | #include <linux/initrd.h> |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/fsl_devices.h> |
| 35 | |
| 36 | #include <asm/system.h> |
| 37 | #include <asm/pgtable.h> |
| 38 | #include <asm/page.h> |
| 39 | #include <asm/atomic.h> |
| 40 | #include <asm/time.h> |
| 41 | #include <asm/io.h> |
| 42 | #include <asm/machdep.h> |
| 43 | #include <asm/open_pic.h> |
| 44 | #include <asm/bootinfo.h> |
| 45 | #include <asm/pci-bridge.h> |
| 46 | #include <asm/mpc85xx.h> |
| 47 | #include <asm/irq.h> |
| 48 | #include <asm/immap_85xx.h> |
| 49 | #include <asm/kgdb.h> |
| 50 | #include <asm/ppc_sys.h> |
| 51 | #include <asm/cpm2.h> |
| 52 | #include <mm/mmu_decl.h> |
| 53 | |
| 54 | #include <syslib/ppc85xx_setup.h> |
| 55 | #include <syslib/cpm2_pic.h> |
| 56 | #include <syslib/ppc85xx_common.h> |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 57 | |
| 58 | #ifndef CONFIG_PCI |
| 59 | unsigned long isa_io_base = 0; |
| 60 | unsigned long isa_mem_base = 0; |
| 61 | #endif |
| 62 | |
| 63 | |
| 64 | extern unsigned long total_memory; /* in mm/init */ |
| 65 | |
| 66 | unsigned char __res[sizeof (bd_t)]; |
| 67 | |
| 68 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ |
| 69 | static u_char tqm85xx_openpic_initsenses[] __initdata = { |
| 70 | MPC85XX_INTERNAL_IRQ_SENSES, |
| 71 | 0x0, /* External 0: */ |
| 72 | 0x0, /* External 1: */ |
| 73 | #if defined(CONFIG_PCI) |
| 74 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI INTA */ |
| 75 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI INTB */ |
| 76 | #else |
| 77 | 0x0, /* External 2: */ |
| 78 | 0x0, /* External 3: */ |
| 79 | #endif |
| 80 | 0x0, /* External 4: */ |
| 81 | 0x0, /* External 5: */ |
| 82 | 0x0, /* External 6: */ |
| 83 | 0x0, /* External 7: */ |
| 84 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: PHY */ |
| 85 | 0x0, /* External 9: */ |
| 86 | 0x0, /* External 10: */ |
| 87 | 0x0, /* External 11: */ |
| 88 | }; |
| 89 | |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 90 | /* ************************************************************************ |
| 91 | * |
| 92 | * Setup the architecture |
| 93 | * |
| 94 | */ |
| 95 | static void __init |
| 96 | tqm85xx_setup_arch(void) |
| 97 | { |
| 98 | bd_t *binfo = (bd_t *) __res; |
| 99 | unsigned int freq; |
| 100 | struct gianfar_platform_data *pdata; |
| 101 | struct gianfar_mdio_data *mdata; |
| 102 | |
| 103 | #ifdef CONFIG_MPC8560 |
| 104 | cpm2_reset(); |
| 105 | #endif |
| 106 | |
| 107 | /* get the core frequency */ |
| 108 | freq = binfo->bi_intfreq; |
| 109 | |
| 110 | if (ppc_md.progress) |
| 111 | ppc_md.progress("tqm85xx_setup_arch()", 0); |
| 112 | |
| 113 | /* Set loops_per_jiffy to a half-way reasonable value, |
| 114 | for use until calibrate_delay gets called. */ |
| 115 | loops_per_jiffy = freq / HZ; |
| 116 | |
| 117 | #ifdef CONFIG_PCI |
| 118 | /* setup PCI host bridges */ |
| 119 | mpc85xx_setup_hose(); |
| 120 | #endif |
| 121 | |
| 122 | #ifndef CONFIG_MPC8560 |
| 123 | #if defined(CONFIG_SERIAL_8250) |
| 124 | mpc85xx_early_serial_map(); |
| 125 | #endif |
| 126 | |
| 127 | #ifdef CONFIG_SERIAL_TEXT_DEBUG |
| 128 | /* Invalidate the entry we stole earlier the serial ports |
| 129 | * should be properly mapped */ |
| 130 | invalidate_tlbcam_entry(num_tlbcam_entries - 1); |
| 131 | #endif |
| 132 | #endif /* CONFIG_MPC8560 */ |
| 133 | |
| 134 | /* setup the board related info for the MDIO bus */ |
| 135 | mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); |
| 136 | |
| 137 | mdata->irq[0] = MPC85xx_IRQ_EXT8; |
| 138 | mdata->irq[1] = MPC85xx_IRQ_EXT8; |
Andy Fleming | a9b1497 | 2006-10-19 19:52:26 -0500 | [diff] [blame] | 139 | mdata->irq[2] = PHY_POLL; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 140 | mdata->irq[3] = MPC85xx_IRQ_EXT8; |
Andy Fleming | a9b1497 | 2006-10-19 19:52:26 -0500 | [diff] [blame] | 141 | mdata->irq[31] = PHY_POLL; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 142 | |
| 143 | /* setup the board related information for the enet controllers */ |
| 144 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); |
| 145 | if (pdata) { |
| 146 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 147 | pdata->bus_id = 0; |
| 148 | pdata->phy_id = 2; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 149 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
| 150 | } |
| 151 | |
| 152 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); |
| 153 | if (pdata) { |
| 154 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 155 | pdata->bus_id = 0; |
| 156 | pdata->phy_id = 1; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 157 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
| 158 | } |
| 159 | |
| 160 | #ifdef CONFIG_MPC8540 |
| 161 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); |
| 162 | if (pdata) { |
| 163 | pdata->board_flags = 0; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 164 | pdata->bus_id = 0; |
| 165 | pdata->phy_id = 3; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 166 | memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); |
| 167 | } |
| 168 | #endif |
| 169 | |
| 170 | #ifdef CONFIG_BLK_DEV_INITRD |
| 171 | if (initrd_start) |
| 172 | ROOT_DEV = Root_RAM0; |
| 173 | else |
| 174 | #endif |
| 175 | #ifdef CONFIG_ROOT_NFS |
| 176 | ROOT_DEV = Root_NFS; |
| 177 | #else |
| 178 | ROOT_DEV = Root_HDA1; |
| 179 | #endif |
| 180 | } |
| 181 | |
| 182 | #ifdef CONFIG_MPC8560 |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 183 | static irqreturn_t cpm2_cascade(int irq, void *dev_id) |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 184 | { |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 185 | while ((irq = cpm2_get_irq()) >= 0) |
| 186 | __do_IRQ(irq); |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 187 | return IRQ_HANDLED; |
| 188 | } |
| 189 | |
| 190 | static struct irqaction cpm2_irqaction = { |
| 191 | .handler = cpm2_cascade, |
Thomas Gleixner | bc59d28 | 2006-07-01 19:29:22 -0700 | [diff] [blame] | 192 | .flags = IRQF_DISABLED, |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 193 | .mask = CPU_MASK_NONE, |
| 194 | .name = "cpm2_cascade", |
| 195 | }; |
| 196 | #endif /* CONFIG_MPC8560 */ |
| 197 | |
| 198 | void __init |
| 199 | tqm85xx_init_IRQ(void) |
| 200 | { |
| 201 | bd_t *binfo = (bd_t *) __res; |
| 202 | |
| 203 | /* Determine the Physical Address of the OpenPIC regs */ |
| 204 | phys_addr_t OpenPIC_PAddr = |
| 205 | binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; |
| 206 | OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); |
| 207 | OpenPIC_InitSenses = tqm85xx_openpic_initsenses; |
| 208 | OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses); |
| 209 | |
| 210 | /* Skip reserved space and internal sources */ |
| 211 | openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); |
| 212 | |
| 213 | /* Map PIC IRQs 0-11 */ |
| 214 | openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000); |
| 215 | |
| 216 | /* we let openpic interrupts starting from an offset, to |
| 217 | * leave space for cascading interrupts underneath. |
| 218 | */ |
| 219 | openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); |
| 220 | |
| 221 | #ifdef CONFIG_MPC8560 |
| 222 | /* Setup CPM2 PIC */ |
| 223 | cpm2_init_IRQ(); |
| 224 | |
| 225 | setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); |
| 226 | #endif /* CONFIG_MPC8560 */ |
| 227 | |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | int tqm85xx_show_cpuinfo(struct seq_file *m) |
| 232 | { |
| 233 | uint pvid, svid, phid1; |
| 234 | uint memsize = total_memory; |
| 235 | bd_t *binfo = (bd_t *) __res; |
| 236 | unsigned int freq; |
| 237 | |
| 238 | /* get the core frequency */ |
| 239 | freq = binfo->bi_intfreq; |
| 240 | |
| 241 | pvid = mfspr(SPRN_PVR); |
| 242 | svid = mfspr(SPRN_SVR); |
| 243 | |
| 244 | seq_printf(m, "Vendor\t\t: TQ Components\n"); |
| 245 | seq_printf(m, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec->ppc_sys_name); |
| 246 | seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); |
| 247 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); |
| 248 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); |
| 249 | |
| 250 | /* Display cpu Pll setting */ |
| 251 | phid1 = mfspr(SPRN_HID1); |
| 252 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); |
| 253 | |
| 254 | /* Display the amount of memory */ |
| 255 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | #if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_DS1337) |
| 261 | extern ulong ds1337_get_rtc_time(void); |
| 262 | extern int ds1337_set_rtc_time(unsigned long nowtime); |
| 263 | |
| 264 | static int __init |
| 265 | tqm85xx_rtc_hookup(void) |
| 266 | { |
| 267 | struct timespec tv; |
| 268 | |
| 269 | ppc_md.set_rtc_time = ds1337_set_rtc_time; |
| 270 | ppc_md.get_rtc_time = ds1337_get_rtc_time; |
| 271 | |
| 272 | tv.tv_nsec = 0; |
| 273 | tv.tv_sec = (ppc_md.get_rtc_time)(); |
| 274 | do_settimeofday(&tv); |
| 275 | |
| 276 | return 0; |
| 277 | } |
| 278 | late_initcall(tqm85xx_rtc_hookup); |
| 279 | #endif |
| 280 | |
| 281 | #ifdef CONFIG_PCI |
| 282 | /* |
| 283 | * interrupt routing |
| 284 | */ |
| 285 | int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 286 | { |
| 287 | static char pci_irq_table[][4] = |
| 288 | /* |
| 289 | * PCI IDSEL/INTPIN->INTLINE |
| 290 | * A B C D |
| 291 | */ |
| 292 | { |
| 293 | {PIRQA, PIRQB, 0, 0}, |
| 294 | }; |
| 295 | |
| 296 | const long min_idsel = 0x1c, max_idsel = 0x1c, irqs_per_slot = 4; |
| 297 | return PCI_IRQ_TABLE_LOOKUP; |
| 298 | } |
| 299 | |
| 300 | int mpc85xx_exclude_device(u_char bus, u_char devfn) |
| 301 | { |
| 302 | if (bus == 0 && PCI_SLOT(devfn) == 0) |
| 303 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 304 | else |
| 305 | return PCIBIOS_SUCCESSFUL; |
| 306 | } |
| 307 | |
| 308 | #endif /* CONFIG_PCI */ |
| 309 | |
| 310 | #ifdef CONFIG_RAPIDIO |
Kumar Gala | de3c8d4 | 2008-01-23 06:12:06 -0600 | [diff] [blame^] | 311 | extern void mpc85xx_rio_setup(int law_start, int law_size); |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 312 | void platform_rio_init(void) |
| 313 | { |
| 314 | /* 512MB RIO LAW at 0xc0000000 */ |
| 315 | mpc85xx_rio_setup(0xc0000000, 0x20000000); |
| 316 | } |
| 317 | #endif /* CONFIG_RAPIDIO */ |
| 318 | |
| 319 | /* ************************************************************************ */ |
| 320 | void __init |
| 321 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 322 | unsigned long r6, unsigned long r7) |
| 323 | { |
| 324 | /* parse_bootinfo must always be called first */ |
| 325 | parse_bootinfo(find_bootinfo()); |
| 326 | |
| 327 | /* |
| 328 | * If we were passed in a board information, copy it into the |
| 329 | * residual data area. |
| 330 | */ |
| 331 | if (r3) { |
| 332 | memcpy((void *) __res, (void *) (r3 + KERNELBASE), |
| 333 | sizeof (bd_t)); |
| 334 | } |
| 335 | |
| 336 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560) |
| 337 | { |
| 338 | bd_t *binfo = (bd_t *) __res; |
| 339 | struct uart_port p; |
| 340 | |
| 341 | /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ |
| 342 | settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base, |
| 343 | binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); |
| 344 | |
| 345 | memset(&p, 0, sizeof (p)); |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 346 | p.iotype = UPIO_MEM; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 347 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET; |
| 348 | p.uartclk = binfo->bi_busfreq; |
| 349 | |
| 350 | gen550_init(0, &p); |
| 351 | |
| 352 | memset(&p, 0, sizeof (p)); |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 353 | p.iotype = UPIO_MEM; |
Kumar Gala | a819f8b | 2005-12-09 11:57:44 -0600 | [diff] [blame] | 354 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET; |
| 355 | p.uartclk = binfo->bi_busfreq; |
| 356 | |
| 357 | gen550_init(1, &p); |
| 358 | } |
| 359 | #endif |
| 360 | |
| 361 | #if defined(CONFIG_BLK_DEV_INITRD) |
| 362 | /* |
| 363 | * If the init RAM disk has been configured in, and there's a valid |
| 364 | * starting address for it, set it up. |
| 365 | */ |
| 366 | if (r4) { |
| 367 | initrd_start = r4 + KERNELBASE; |
| 368 | initrd_end = r5 + KERNELBASE; |
| 369 | } |
| 370 | #endif /* CONFIG_BLK_DEV_INITRD */ |
| 371 | |
| 372 | /* Copy the kernel command line arguments to a safe place. */ |
| 373 | |
| 374 | if (r6) { |
| 375 | *(char *) (r7 + KERNELBASE) = 0; |
| 376 | strcpy(cmd_line, (char *) (r6 + KERNELBASE)); |
| 377 | } |
| 378 | |
| 379 | identify_ppc_sys_by_id(mfspr(SPRN_SVR)); |
| 380 | |
| 381 | /* setup the PowerPC module struct */ |
| 382 | ppc_md.setup_arch = tqm85xx_setup_arch; |
| 383 | ppc_md.show_cpuinfo = tqm85xx_show_cpuinfo; |
| 384 | |
| 385 | ppc_md.init_IRQ = tqm85xx_init_IRQ; |
| 386 | ppc_md.get_irq = openpic_get_irq; |
| 387 | |
| 388 | ppc_md.restart = mpc85xx_restart; |
| 389 | ppc_md.power_off = mpc85xx_power_off; |
| 390 | ppc_md.halt = mpc85xx_halt; |
| 391 | |
| 392 | ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory; |
| 393 | |
| 394 | ppc_md.time_init = NULL; |
| 395 | ppc_md.set_rtc_time = NULL; |
| 396 | ppc_md.get_rtc_time = NULL; |
| 397 | ppc_md.calibrate_decr = mpc85xx_calibrate_decr; |
| 398 | |
| 399 | #ifndef CONFIG_MPC8560 |
| 400 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) |
| 401 | ppc_md.progress = gen550_progress; |
| 402 | #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ |
| 403 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB) |
| 404 | ppc_md.early_serial_map = mpc85xx_early_serial_map; |
| 405 | #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */ |
| 406 | #endif /* CONFIG_MPC8560 */ |
| 407 | |
| 408 | if (ppc_md.progress) |
| 409 | ppc_md.progress("tqm85xx_init(): exit", 0); |
| 410 | |
| 411 | return; |
| 412 | } |