Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* pci-vdk.c: MB93090-MB00 (VDK) PCI support |
| 2 | * |
| 3 | * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/types.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/sched.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/ioport.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/slab.h> |
| 20 | |
| 21 | #include <asm/segment.h> |
| 22 | #include <asm/io.h> |
| 23 | #include <asm/mb-regs.h> |
| 24 | #include <asm/mb86943a.h> |
| 25 | #include "pci-frv.h" |
| 26 | |
| 27 | unsigned int __nongpreldata pci_probe = 1; |
| 28 | |
| 29 | int __nongpreldata pcibios_last_bus = -1; |
| 30 | struct pci_bus *__nongpreldata pci_root_bus; |
| 31 | struct pci_ops *__nongpreldata pci_root_ops; |
| 32 | |
| 33 | /* |
| 34 | * Functions for accessing PCI configuration space |
| 35 | */ |
| 36 | |
| 37 | #define CONFIG_CMD(bus, dev, where) \ |
| 38 | (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) |
| 39 | |
| 40 | #define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80) |
| 41 | |
| 42 | #define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3)) |
| 43 | #define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2)) |
| 44 | #define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88) |
| 45 | |
| 46 | #define __set_PciCfgDataB(A,V) \ |
| 47 | writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3))) |
| 48 | |
| 49 | #define __set_PciCfgDataW(A,V) \ |
| 50 | writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2))) |
| 51 | |
| 52 | #define __set_PciCfgDataL(A,V) \ |
| 53 | writel((V), (volatile void __iomem *) __region_CS1 + 0x88) |
| 54 | |
| 55 | #define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 56 | #define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 57 | #define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 58 | |
| 59 | #define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 60 | #define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 61 | #define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) |
| 62 | |
| 63 | static inline int __query(const struct pci_dev *dev) |
| 64 | { |
| 65 | // return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0)); |
| 66 | // return dev->bus->number==1; |
| 67 | // return dev->bus->number==0 && |
| 68 | // (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0)); |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | /*****************************************************************************/ |
| 73 | /* |
| 74 | * |
| 75 | */ |
| 76 | static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, |
| 77 | u32 *val) |
| 78 | { |
| 79 | u32 _value; |
| 80 | |
| 81 | if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { |
| 82 | _value = __get_PciBridgeDataL(where & ~3); |
| 83 | } |
| 84 | else { |
| 85 | __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); |
| 86 | _value = __get_PciCfgDataL(where & ~3); |
| 87 | } |
| 88 | |
| 89 | switch (size) { |
| 90 | case 1: |
| 91 | _value = _value >> ((where & 3) * 8); |
| 92 | break; |
| 93 | |
| 94 | case 2: |
| 95 | _value = _value >> ((where & 2) * 8); |
| 96 | break; |
| 97 | |
| 98 | case 4: |
| 99 | break; |
| 100 | |
| 101 | default: |
| 102 | BUG(); |
| 103 | } |
| 104 | |
| 105 | *val = _value; |
| 106 | return PCIBIOS_SUCCESSFUL; |
| 107 | } |
| 108 | |
| 109 | static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, |
| 110 | u32 value) |
| 111 | { |
| 112 | switch (size) { |
| 113 | case 1: |
| 114 | if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { |
| 115 | __set_PciBridgeDataB(where, value); |
| 116 | } |
| 117 | else { |
| 118 | __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); |
| 119 | __set_PciCfgDataB(where, value); |
| 120 | } |
| 121 | break; |
| 122 | |
| 123 | case 2: |
| 124 | if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { |
| 125 | __set_PciBridgeDataW(where, value); |
| 126 | } |
| 127 | else { |
| 128 | __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); |
| 129 | __set_PciCfgDataW(where, value); |
| 130 | } |
| 131 | break; |
| 132 | |
| 133 | case 4: |
| 134 | if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { |
| 135 | __set_PciBridgeDataL(where, value); |
| 136 | } |
| 137 | else { |
| 138 | __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); |
| 139 | __set_PciCfgDataL(where, value); |
| 140 | } |
| 141 | break; |
| 142 | |
| 143 | default: |
| 144 | BUG(); |
| 145 | } |
| 146 | |
| 147 | return PCIBIOS_SUCCESSFUL; |
| 148 | } |
| 149 | |
| 150 | static struct pci_ops pci_direct_frv = { |
| 151 | pci_frv_read_config, |
| 152 | pci_frv_write_config, |
| 153 | }; |
| 154 | |
| 155 | /* |
| 156 | * Before we decide to use direct hardware access mechanisms, we try to do some |
| 157 | * trivial checks to ensure it at least _seems_ to be working -- we just test |
| 158 | * whether bus 00 contains a host bridge (this is similar to checking |
| 159 | * techniques used in XFree86, but ours should be more reliable since we |
| 160 | * attempt to make use of direct access hints provided by the PCI BIOS). |
| 161 | * |
| 162 | * This should be close to trivial, but it isn't, because there are buggy |
| 163 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. |
| 164 | */ |
| 165 | static int __init pci_sanity_check(struct pci_ops *o) |
| 166 | { |
| 167 | struct pci_bus bus; /* Fake bus and device */ |
| 168 | u32 id; |
| 169 | |
| 170 | bus.number = 0; |
| 171 | |
| 172 | if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) { |
| 173 | printk("PCI: VDK Bridge device:vendor: %08x\n", id); |
| 174 | if (id == 0x200e10cf) |
| 175 | return 1; |
| 176 | } |
| 177 | |
| 178 | printk("PCI: VDK Bridge: Sanity check failed\n"); |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static struct pci_ops * __init pci_check_direct(void) |
| 183 | { |
| 184 | unsigned long flags; |
| 185 | |
| 186 | local_irq_save(flags); |
| 187 | |
| 188 | /* check if access works */ |
| 189 | if (pci_sanity_check(&pci_direct_frv)) { |
| 190 | local_irq_restore(flags); |
| 191 | printk("PCI: Using configuration frv\n"); |
| 192 | // request_mem_region(0xBE040000, 256, "FRV bridge"); |
| 193 | // request_mem_region(0xBFFFFFF4, 12, "PCI frv"); |
| 194 | return &pci_direct_frv; |
| 195 | } |
| 196 | |
| 197 | local_irq_restore(flags); |
| 198 | return NULL; |
| 199 | } |
| 200 | |
| 201 | /* |
| 202 | * Several buggy motherboards address only 16 devices and mirror |
| 203 | * them to next 16 IDs. We try to detect this `feature' on all |
| 204 | * primary buses (those containing host bridges as they are |
| 205 | * expected to be unique) and remove the ghost devices. |
| 206 | */ |
| 207 | |
| 208 | static void __init pcibios_fixup_ghosts(struct pci_bus *b) |
| 209 | { |
| 210 | struct list_head *ln, *mn; |
| 211 | struct pci_dev *d, *e; |
| 212 | int mirror = PCI_DEVFN(16,0); |
| 213 | int seen_host_bridge = 0; |
| 214 | int i; |
| 215 | |
| 216 | for (ln=b->devices.next; ln != &b->devices; ln=ln->next) { |
| 217 | d = pci_dev_b(ln); |
| 218 | if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST) |
| 219 | seen_host_bridge++; |
| 220 | for (mn=ln->next; mn != &b->devices; mn=mn->next) { |
| 221 | e = pci_dev_b(mn); |
| 222 | if (e->devfn != d->devfn + mirror || |
| 223 | e->vendor != d->vendor || |
| 224 | e->device != d->device || |
| 225 | e->class != d->class) |
| 226 | continue; |
| 227 | for(i=0; i<PCI_NUM_RESOURCES; i++) |
| 228 | if (e->resource[i].start != d->resource[i].start || |
| 229 | e->resource[i].end != d->resource[i].end || |
| 230 | e->resource[i].flags != d->resource[i].flags) |
| 231 | continue; |
| 232 | break; |
| 233 | } |
| 234 | if (mn == &b->devices) |
| 235 | return; |
| 236 | } |
| 237 | if (!seen_host_bridge) |
| 238 | return; |
| 239 | printk("PCI: Ignoring ghost devices on bus %02x\n", b->number); |
| 240 | |
| 241 | ln = &b->devices; |
| 242 | while (ln->next != &b->devices) { |
| 243 | d = pci_dev_b(ln->next); |
| 244 | if (d->devfn >= mirror) { |
| 245 | list_del(&d->global_list); |
| 246 | list_del(&d->bus_list); |
| 247 | kfree(d); |
| 248 | } else |
| 249 | ln = ln->next; |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * Discover remaining PCI buses in case there are peer host bridges. |
| 255 | * We use the number of last PCI bus provided by the PCI BIOS. |
| 256 | */ |
| 257 | static void __init pcibios_fixup_peer_bridges(void) |
| 258 | { |
| 259 | struct pci_bus bus; |
| 260 | struct pci_dev dev; |
| 261 | int n; |
| 262 | u16 l; |
| 263 | |
| 264 | if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff) |
| 265 | return; |
| 266 | printk("PCI: Peer bridge fixup\n"); |
| 267 | for (n=0; n <= pcibios_last_bus; n++) { |
| 268 | if (pci_find_bus(0, n)) |
| 269 | continue; |
| 270 | bus.number = n; |
| 271 | bus.ops = pci_root_ops; |
| 272 | dev.bus = &bus; |
| 273 | for(dev.devfn=0; dev.devfn<256; dev.devfn += 8) |
| 274 | if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) && |
| 275 | l != 0x0000 && l != 0xffff) { |
| 276 | printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l); |
| 277 | printk("PCI: Discovered peer bus %02x\n", n); |
| 278 | pci_scan_bus(n, pci_root_ops, NULL); |
| 279 | break; |
| 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | /* |
| 285 | * Exceptions for specific devices. Usually work-arounds for fatal design flaws. |
| 286 | */ |
| 287 | |
| 288 | static void __init pci_fixup_umc_ide(struct pci_dev *d) |
| 289 | { |
| 290 | /* |
| 291 | * UM8886BF IDE controller sets region type bits incorrectly, |
| 292 | * therefore they look like memory despite of them being I/O. |
| 293 | */ |
| 294 | int i; |
| 295 | |
| 296 | printk("PCI: Fixing base address flags for device %s\n", pci_name(d)); |
| 297 | for(i=0; i<4; i++) |
| 298 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; |
| 299 | } |
| 300 | |
| 301 | static void __init pci_fixup_ide_bases(struct pci_dev *d) |
| 302 | { |
| 303 | int i; |
| 304 | |
| 305 | /* |
| 306 | * PCI IDE controllers use non-standard I/O port decoding, respect it. |
| 307 | */ |
| 308 | if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) |
| 309 | return; |
| 310 | printk("PCI: IDE base address fixup for %s\n", pci_name(d)); |
| 311 | for(i=0; i<4; i++) { |
| 312 | struct resource *r = &d->resource[i]; |
| 313 | if ((r->start & ~0x80) == 0x374) { |
| 314 | r->start |= 2; |
| 315 | r->end = r->start; |
| 316 | } |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static void __init pci_fixup_ide_trash(struct pci_dev *d) |
| 321 | { |
| 322 | int i; |
| 323 | |
| 324 | /* |
| 325 | * There exist PCI IDE controllers which have utter garbage |
| 326 | * in first four base registers. Ignore that. |
| 327 | */ |
| 328 | printk("PCI: IDE base address trash cleared for %s\n", pci_name(d)); |
| 329 | for(i=0; i<4; i++) |
| 330 | d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0; |
| 331 | } |
| 332 | |
| 333 | static void __devinit pci_fixup_latency(struct pci_dev *d) |
| 334 | { |
| 335 | /* |
| 336 | * SiS 5597 and 5598 chipsets require latency timer set to |
| 337 | * at most 32 to avoid lockups. |
| 338 | */ |
| 339 | DBG("PCI: Setting max latency to 32\n"); |
| 340 | pcibios_max_latency = 32; |
| 341 | } |
| 342 | |
| 343 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); |
| 344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash); |
| 345 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); |
| 346 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); |
| 347 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); |
| 348 | |
| 349 | /* |
| 350 | * Called after each bus is probed, but before its children |
| 351 | * are examined. |
| 352 | */ |
| 353 | |
| 354 | void __init pcibios_fixup_bus(struct pci_bus *bus) |
| 355 | { |
| 356 | #if 0 |
| 357 | printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); |
| 358 | #endif |
| 359 | pcibios_fixup_ghosts(bus); |
| 360 | pci_read_bridge_bases(bus); |
| 361 | |
| 362 | if (bus->number == 0) { |
| 363 | struct list_head *ln; |
| 364 | struct pci_dev *dev; |
| 365 | for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { |
| 366 | dev = pci_dev_b(ln); |
| 367 | if (dev->devfn == 0) { |
| 368 | dev->resource[0].start = 0; |
| 369 | dev->resource[0].end = 0; |
| 370 | } |
| 371 | } |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | /* |
| 376 | * Initialization. Try all known PCI access methods. Note that we support |
| 377 | * using both PCI BIOS and direct access: in such cases, we use I/O ports |
| 378 | * to access config space, but we still keep BIOS order of cards to be |
| 379 | * compatible with 2.0.X. This should go away some day. |
| 380 | */ |
| 381 | |
| 382 | int __init pcibios_init(void) |
| 383 | { |
| 384 | struct pci_ops *dir = NULL; |
| 385 | |
| 386 | if (!mb93090_mb00_detected) |
| 387 | return -ENXIO; |
| 388 | |
| 389 | __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP; |
| 390 | |
| 391 | __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000; |
| 392 | __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000; |
| 393 | |
| 394 | *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000; |
| 395 | *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000; |
| 396 | |
| 397 | __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9; |
| 398 | __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9; |
| 399 | __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000; |
| 400 | __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000; |
| 401 | mb(); |
| 402 | |
| 403 | *(volatile unsigned long *)(__region_CS2+0x01300014) == 1; |
| 404 | |
| 405 | ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00; |
| 406 | ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff; |
| 407 | ioport_resource.end += ioport_resource.start; |
| 408 | |
David Howells | 9dec17e | 2006-07-10 04:44:51 -0700 | [diff] [blame] | 409 | printk("PCI IO window: %08llx-%08llx\n", |
| 410 | (unsigned long long) ioport_resource.start, |
| 411 | (unsigned long long) ioport_resource.end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | |
| 413 | iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00; |
| 414 | |
| 415 | /* Reserve somewhere to write to flush posted writes. */ |
| 416 | iomem_resource.start += 0x400; |
| 417 | |
| 418 | iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff; |
| 419 | iomem_resource.end += iomem_resource.start; |
| 420 | |
David Howells | 9dec17e | 2006-07-10 04:44:51 -0700 | [diff] [blame] | 421 | printk("PCI MEM window: %08llx-%08llx\n", |
| 422 | (unsigned long long) iomem_resource.start, |
| 423 | (unsigned long long) iomem_resource.end); |
| 424 | printk("PCI DMA memory: %08lx-%08lx\n", |
| 425 | dma_coherent_mem_start, dma_coherent_mem_end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 426 | |
| 427 | if (!pci_probe) |
| 428 | return -ENXIO; |
| 429 | |
| 430 | dir = pci_check_direct(); |
| 431 | if (dir) |
| 432 | pci_root_ops = dir; |
| 433 | else { |
| 434 | printk("PCI: No PCI bus detected\n"); |
| 435 | return -ENXIO; |
| 436 | } |
| 437 | |
| 438 | printk("PCI: Probing PCI hardware\n"); |
| 439 | pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL); |
| 440 | |
| 441 | pcibios_irq_init(); |
| 442 | pcibios_fixup_peer_bridges(); |
| 443 | pcibios_fixup_irqs(); |
| 444 | pcibios_resource_survey(); |
| 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | arch_initcall(pcibios_init); |
| 450 | |
| 451 | char * __init pcibios_setup(char *str) |
| 452 | { |
| 453 | if (!strcmp(str, "off")) { |
| 454 | pci_probe = 0; |
| 455 | return NULL; |
| 456 | } else if (!strncmp(str, "lastbus=", 8)) { |
| 457 | pcibios_last_bus = simple_strtol(str+8, NULL, 0); |
| 458 | return NULL; |
| 459 | } |
| 460 | return str; |
| 461 | } |
| 462 | |
| 463 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 464 | { |
| 465 | int err; |
| 466 | |
| 467 | if ((err = pcibios_enable_resources(dev, mask)) < 0) |
| 468 | return err; |
Eric W. Biederman | bba6f6f | 2007-03-28 15:36:09 +0200 | [diff] [blame] | 469 | if (!dev->msi_enabled) |
| 470 | pcibios_enable_irq(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | return 0; |
| 472 | } |