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Marek Szyprowskid947e792010-05-17 08:53:10 +02001/* linux/arch/arm/mach-s5pv210/mach-aquila.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
Marek Szyprowskib3150322010-05-17 08:53:13 +020015#include <linux/fb.h>
Marek Szyprowskid947e792010-05-17 08:53:10 +020016
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <asm/setup.h>
20#include <asm/mach-types.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
Marek Szyprowskib3150322010-05-17 08:53:13 +020024#include <mach/regs-fb.h>
Marek Szyprowskid947e792010-05-17 08:53:10 +020025
26#include <plat/regs-serial.h>
27#include <plat/s5pv210.h>
28#include <plat/devs.h>
29#include <plat/cpu.h>
Marek Szyprowskib3150322010-05-17 08:53:13 +020030#include <plat/fb.h>
Marek Szyprowskid947e792010-05-17 08:53:10 +020031
32/* Following are default values for UCON, ULCON and UFCON UART registers */
33#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \
35 S3C2410_UCON_TXIRQMODE | \
36 S3C2410_UCON_RXIRQMODE | \
37 S3C2410_UCON_RXFIFO_TOI | \
38 S3C2443_UCON_RXERR_IRQEN)
39
40#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8
41
Joonyoung Shimdf017142010-06-24 19:28:55 +090042#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
Marek Szyprowskid947e792010-05-17 08:53:10 +020043
Joonyoung Shimdf017142010-06-24 19:28:55 +090044static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
Marek Szyprowskid947e792010-05-17 08:53:10 +020045 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = S5PV210_UCON_DEFAULT,
49 .ulcon = S5PV210_ULCON_DEFAULT,
Joonyoung Shimdf017142010-06-24 19:28:55 +090050 /*
51 * Actually UART0 can support 256 bytes fifo, but aquila board
52 * supports 128 bytes fifo because of initial chip bug
53 */
54 .ufcon = S5PV210_UFCON_DEFAULT |
55 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
Marek Szyprowskid947e792010-05-17 08:53:10 +020056 },
57 [1] = {
58 .hwport = 1,
59 .flags = 0,
60 .ucon = S5PV210_UCON_DEFAULT,
61 .ulcon = S5PV210_ULCON_DEFAULT,
Joonyoung Shimdf017142010-06-24 19:28:55 +090062 .ufcon = S5PV210_UFCON_DEFAULT |
63 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
Marek Szyprowskid947e792010-05-17 08:53:10 +020064 },
65 [2] = {
66 .hwport = 2,
67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT,
Joonyoung Shimdf017142010-06-24 19:28:55 +090070 .ufcon = S5PV210_UFCON_DEFAULT |
71 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
Marek Szyprowskid947e792010-05-17 08:53:10 +020072 },
73 [3] = {
74 .hwport = 3,
75 .flags = 0,
76 .ucon = S5PV210_UCON_DEFAULT,
77 .ulcon = S5PV210_ULCON_DEFAULT,
Joonyoung Shimdf017142010-06-24 19:28:55 +090078 .ufcon = S5PV210_UFCON_DEFAULT |
79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
Marek Szyprowskid947e792010-05-17 08:53:10 +020080 },
81};
82
Marek Szyprowskib3150322010-05-17 08:53:13 +020083/* Frame Buffer */
84static struct s3c_fb_pd_win aquila_fb_win0 = {
85 .win_mode = {
86 .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60),
87 .left_margin = 16,
88 .right_margin = 16,
89 .upper_margin = 3,
90 .lower_margin = 28,
91 .hsync_len = 2,
92 .vsync_len = 2,
93 .xres = 480,
94 .yres = 800,
95 },
96 .max_bpp = 32,
97 .default_bpp = 16,
98};
99
100static struct s3c_fb_pd_win aquila_fb_win1 = {
101 .win_mode = {
102 .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60),
103 .left_margin = 16,
104 .right_margin = 16,
105 .upper_margin = 3,
106 .lower_margin = 28,
107 .hsync_len = 2,
108 .vsync_len = 2,
109 .xres = 480,
110 .yres = 800,
111 },
112 .max_bpp = 32,
113 .default_bpp = 16,
114};
115
116static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
117 .win[0] = &aquila_fb_win0,
118 .win[1] = &aquila_fb_win1,
119 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
120 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
121 VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
122 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
123};
124
Marek Szyprowskid947e792010-05-17 08:53:10 +0200125static struct platform_device *aquila_devices[] __initdata = {
Marek Szyprowskib3150322010-05-17 08:53:13 +0200126 &s3c_device_fb,
Marek Szyprowskid947e792010-05-17 08:53:10 +0200127};
128
129static void __init aquila_map_io(void)
130{
131 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
132 s3c24xx_init_clocks(24000000);
Joonyoung Shimdf017142010-06-24 19:28:55 +0900133 s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
Marek Szyprowskid947e792010-05-17 08:53:10 +0200134}
135
136static void __init aquila_machine_init(void)
137{
Marek Szyprowskib3150322010-05-17 08:53:13 +0200138 /* FB */
139 s3c_fb_set_platdata(&aquila_lcd_pdata);
140
Marek Szyprowskid947e792010-05-17 08:53:10 +0200141 platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
142}
143
144MACHINE_START(AQUILA, "Aquila")
145 /* Maintainers:
146 Marek Szyprowski <m.szyprowski@samsung.com>
147 Kyungmin Park <kyungmin.park@samsung.com> */
148 .phys_io = S3C_PA_UART & 0xfff00000,
149 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
150 .boot_params = S5P_PA_SDRAM + 0x100,
151 .init_irq = s5pv210_init_irq,
152 .map_io = aquila_map_io,
153 .init_machine = aquila_machine_init,
154 .timer = &s3c24xx_timer,
155MACHINE_END