blob: 6fdca97186e769ae485f5b4bdf4332e69aa373f8 [file] [log] [blame]
Dmitry Baryshkov9c636342008-09-10 05:01:17 +04001/*
2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
3 * which contain:
4 *
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
19
20#include <sound/ac97_codec.h>
21#include <sound/pxa2xx-lib.h>
22
23#include <asm/irq.h>
Eric Miao1f017a92008-11-28 14:19:33 +080024#include <mach/regs-ac97.h>
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040025#include <mach/pxa2xx-gpio.h>
26#include <mach/audio.h>
27
28static DEFINE_MUTEX(car_mutex);
29static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
30static volatile long gsr_bits;
31static struct clk *ac97_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040032static struct clk *ac97conf_clk;
Robert Jarzmik26ade892009-03-15 14:10:54 +010033static int reset_gpio;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040034
35/*
36 * Beware PXA27x bugs:
37 *
38 * o Slot 12 read from modem space will hang controller.
39 * o CDONE, SDONE interrupt fails after any slot 12 IO.
40 *
41 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
42 * 1 jiffy timeout if interrupt never comes).
43 */
44
Robert Jarzmik26ade892009-03-15 14:10:54 +010045enum {
46 RESETGPIO_FORCE_HIGH,
47 RESETGPIO_FORCE_LOW,
48 RESETGPIO_NORMAL_ALTFUNC
49};
50
51/**
52 * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
53 * @mode: chosen action
54 *
55 * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
56 * must be done to insure proper work of AC97 reset line. This function
57 * computes the correct gpio_mode for further use by reset functions, and
58 * applied the change through pxa_gpio_mode.
59 */
60static void set_resetgpio_mode(int resetgpio_action)
61{
62 int mode = 0;
63
64 if (reset_gpio)
65 switch (resetgpio_action) {
66 case RESETGPIO_NORMAL_ALTFUNC:
67 if (reset_gpio == 113)
Mike Rapoport1ffafeb2009-05-11 13:11:38 +030068 mode = 113 | GPIO_ALT_FN_2_OUT;
Robert Jarzmik26ade892009-03-15 14:10:54 +010069 if (reset_gpio == 95)
70 mode = 95 | GPIO_ALT_FN_1_OUT;
71 break;
72 case RESETGPIO_FORCE_LOW:
73 mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
74 break;
75 case RESETGPIO_FORCE_HIGH:
76 mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
77 break;
78 };
79
80 if (mode)
81 pxa_gpio_mode(mode);
82}
83
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040084unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
85{
86 unsigned short val = -1;
87 volatile u32 *reg_addr;
88
89 mutex_lock(&car_mutex);
90
91 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +010092 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040093 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
94 else
95 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040096 reg_addr += (reg >> 1);
97
98 /* start read access across the ac97 link */
99 GSR = GSR_CDONE | GSR_SDONE;
100 gsr_bits = 0;
101 val = *reg_addr;
102 if (reg == AC97_GPIO_STATUS)
103 goto out;
104 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
105 !((GSR | gsr_bits) & GSR_SDONE)) {
106 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
107 __func__, reg, GSR | gsr_bits);
108 val = -1;
109 goto out;
110 }
111
112 /* valid data now */
113 GSR = GSR_CDONE | GSR_SDONE;
114 gsr_bits = 0;
115 val = *reg_addr;
116 /* but we've just started another cycle... */
117 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
118
119out: mutex_unlock(&car_mutex);
120 return val;
121}
122EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
123
124void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
125 unsigned short val)
126{
127 volatile u32 *reg_addr;
128
129 mutex_lock(&car_mutex);
130
131 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100132 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400133 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
134 else
135 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400136 reg_addr += (reg >> 1);
137
138 GSR = GSR_CDONE | GSR_SDONE;
139 gsr_bits = 0;
140 *reg_addr = val;
141 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
142 !((GSR | gsr_bits) & GSR_CDONE))
143 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
144 __func__, reg, GSR | gsr_bits);
145
146 mutex_unlock(&car_mutex);
147}
148EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
149
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400150#ifdef CONFIG_PXA25x
151static inline void pxa_ac97_warm_pxa25x(void)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400152{
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400153 gsr_bits = 0;
154
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400155 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
156 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
157}
158
159static inline void pxa_ac97_cold_pxa25x(void)
160{
161 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
162 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
163
164 gsr_bits = 0;
165
166 GCR = GCR_COLD_RST;
167 GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
168 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
169}
170#endif
171
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400172#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400173static inline void pxa_ac97_warm_pxa27x(void)
174{
175 gsr_bits = 0;
176
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400177 /* warm reset broken on Bulverde,
178 so manually keep AC97 reset high */
Robert Jarzmik26ade892009-03-15 14:10:54 +0100179 set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400180 udelay(10);
181 GCR |= GCR_WARM_RST;
Robert Jarzmik26ade892009-03-15 14:10:54 +0100182 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400183 udelay(500);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400184}
185
186static inline void pxa_ac97_cold_pxa27x(void)
187{
188 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
189 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
190
191 gsr_bits = 0;
192
193 /* PXA27x Developers Manual section 13.5.2.2.1 */
194 clk_enable(ac97conf_clk);
195 udelay(5);
196 clk_disable(ac97conf_clk);
197 GCR = GCR_COLD_RST;
198 udelay(50);
199}
200#endif
201
202#ifdef CONFIG_PXA3xx
203static inline void pxa_ac97_warm_pxa3xx(void)
204{
205 int timeout = 100;
206
207 gsr_bits = 0;
208
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400209 /* Can't use interrupts */
210 GCR |= GCR_WARM_RST;
211 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
212 mdelay(1);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400213}
214
215static inline void pxa_ac97_cold_pxa3xx(void)
216{
217 int timeout = 1000;
218
219 /* Hold CLKBPB for 100us */
220 GCR = 0;
221 GCR = GCR_CLKBPB;
222 udelay(100);
223 GCR = 0;
224
225 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
226 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
227
228 gsr_bits = 0;
229
230 /* Can't use interrupts on PXA3xx */
231 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
232
233 GCR = GCR_WARM_RST | GCR_COLD_RST;
234 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
235 mdelay(10);
236}
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400237#endif
238
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400239bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
240{
Luotao Fu057de502009-03-26 13:18:03 +0100241 unsigned long gsr;
242
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400243#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100244 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400245 pxa_ac97_warm_pxa25x();
246 else
247#endif
248#ifdef CONFIG_PXA27x
249 if (cpu_is_pxa27x())
250 pxa_ac97_warm_pxa27x();
251 else
252#endif
253#ifdef CONFIG_PXA3xx
254 if (cpu_is_pxa3xx())
255 pxa_ac97_warm_pxa3xx();
256 else
257#endif
258 BUG();
Luotao Fu057de502009-03-26 13:18:03 +0100259 gsr = GSR | gsr_bits;
260 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400261 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100262 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400263
264 return false;
265 }
266
267 return true;
268}
269EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
270
271bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
272{
Luotao Fu057de502009-03-26 13:18:03 +0100273 unsigned long gsr;
274
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400275#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100276 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400277 pxa_ac97_cold_pxa25x();
278 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400279#endif
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400280#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400281 if (cpu_is_pxa27x())
282 pxa_ac97_cold_pxa27x();
283 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400284#endif
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400285#ifdef CONFIG_PXA3xx
286 if (cpu_is_pxa3xx())
287 pxa_ac97_cold_pxa3xx();
288 else
289#endif
290 BUG();
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400291
Luotao Fu057de502009-03-26 13:18:03 +0100292 gsr = GSR | gsr_bits;
293 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400294 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100295 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400296
297 return false;
298 }
299
300 return true;
301}
302EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
303
304
305void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
306{
307 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
308 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
309}
310EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
311
312static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
313{
314 long status;
315
316 status = GSR;
317 if (status) {
318 GSR = status;
319 gsr_bits |= status;
320 wake_up(&gsr_wq);
321
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400322 /* Although we don't use those we still need to clear them
323 since they tend to spuriously trigger when MMC is used
324 (hardware bug? go figure)... */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400325 if (cpu_is_pxa27x()) {
326 MISR = MISR_EOC;
327 PISR = PISR_EOC;
328 MCSR = MCSR_EOC;
329 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400330
331 return IRQ_HANDLED;
332 }
333
334 return IRQ_NONE;
335}
336
337#ifdef CONFIG_PM
338int pxa2xx_ac97_hw_suspend(void)
339{
340 GCR |= GCR_ACLINK_OFF;
341 clk_disable(ac97_clk);
342 return 0;
343}
344EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
345
346int pxa2xx_ac97_hw_resume(void)
347{
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100348 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400349 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
350 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
351 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
352 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
353 }
354 if (cpu_is_pxa27x()) {
Robert Jarzmik26ade892009-03-15 14:10:54 +0100355 /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
356 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400357 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400358 clk_enable(ac97_clk);
359 return 0;
360}
361EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
362#endif
363
364int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
365{
366 int ret;
Mark Browneae17752009-04-13 11:48:03 +0100367 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
Robert Jarzmik26ade892009-03-15 14:10:54 +0100368
369 if (pdata) {
370 switch (pdata->reset_gpio) {
371 case 95:
372 case 113:
373 reset_gpio = pdata->reset_gpio;
374 break;
375 case 0:
376 reset_gpio = 113;
377 break;
378 case -1:
379 break;
380 default:
Takashi Iwai1f218692009-03-19 14:08:58 +0100381 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
Robert Jarzmik26ade892009-03-15 14:10:54 +0100382 pdata->reset_gpio);
383 }
384 } else {
385 if (cpu_is_pxa27x())
386 reset_gpio = 113;
387 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400388
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100389 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400390 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
391 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
392 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
393 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400394 }
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400395
396 if (cpu_is_pxa27x()) {
397 /* Use GPIO 113 as AC97 Reset on Bulverde */
Robert Jarzmik26ade892009-03-15 14:10:54 +0100398 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400399 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
400 if (IS_ERR(ac97conf_clk)) {
401 ret = PTR_ERR(ac97conf_clk);
402 ac97conf_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300403 goto err_conf;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400404 }
405 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400406
407 ac97_clk = clk_get(&dev->dev, "AC97CLK");
408 if (IS_ERR(ac97_clk)) {
409 ret = PTR_ERR(ac97_clk);
410 ac97_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300411 goto err_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400412 }
413
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300414 ret = clk_enable(ac97_clk);
415 if (ret)
416 goto err_clk2;
417
418 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
419 if (ret < 0)
420 goto err_irq;
421
422 return 0;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400423
424err_irq:
425 GCR |= GCR_ACLINK_OFF;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300426err_clk2:
427 clk_put(ac97_clk);
428 ac97_clk = NULL;
429err_clk:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400430 if (ac97conf_clk) {
431 clk_put(ac97conf_clk);
432 ac97conf_clk = NULL;
433 }
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300434err_conf:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400435 return ret;
436}
437EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
438
439void pxa2xx_ac97_hw_remove(struct platform_device *dev)
440{
441 GCR |= GCR_ACLINK_OFF;
442 free_irq(IRQ_AC97, NULL);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400443 if (ac97conf_clk) {
444 clk_put(ac97conf_clk);
445 ac97conf_clk = NULL;
446 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400447 clk_disable(ac97_clk);
448 clk_put(ac97_clk);
449 ac97_clk = NULL;
450}
451EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
452
453MODULE_AUTHOR("Nicolas Pitre");
454MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
455MODULE_LICENSE("GPL");
456