Lin Huang | c1ceb8f7 | 2016-09-05 13:06:09 +0800 | [diff] [blame] | 1 | * Rockchip rk3399 DMC(Dynamic Memory Controller) device |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Must be "rockchip,rk3399-dmc". |
| 5 | - devfreq-events: Node to get DDR loading, Refer to |
| 6 | Documentation/devicetree/bindings/devfreq/ |
| 7 | rockchip-dfi.txt |
| 8 | - interrupts: The interrupt number to the CPU. The interrupt |
| 9 | specifier format depends on the interrupt controller. |
| 10 | It should be DCF interrupts, when DDR dvfs finish, |
| 11 | it will happen. |
| 12 | - clocks: Phandles for clock specified in "clock-names" property |
| 13 | - clock-names : The name of clock used by the DFI, must be |
| 14 | "pclk_ddr_mon"; |
| 15 | - operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt |
| 16 | for details. |
| 17 | - center-supply: DMC supply node. |
| 18 | - status: Marks the node enabled/disabled. |
| 19 | |
| 20 | Following properties are ddr timing: |
| 21 | |
| 22 | - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h, |
| 23 | it select ddr3 cl-trp-trcd type, default value |
| 24 | "DDR3_DEFAULT".it must selected according to |
| 25 | "Speed Bin" in ddr3 datasheet, DO NOT use |
| 26 | smaller "Speed Bin" than ddr3 exactly is. |
| 27 | |
| 28 | - rockchip,pd_idle : Config the PD_IDLE value, defined the power-down |
| 29 | idle period, memories are places into power-down |
| 30 | mode if bus is idle for PD_IDLE DFI clocks. |
| 31 | |
| 32 | - rockchip,sr_idle : Configure the SR_IDLE value, defined the |
| 33 | selfrefresh idle period, memories are places |
| 34 | into self-refresh mode if bus is idle for |
| 35 | SR_IDLE*1024 DFI clocks (DFI clocks freq is |
| 36 | half of dram's clocks), defaule value is "0". |
| 37 | |
| 38 | - rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and |
| 39 | controller clock gating idle period, memories |
| 40 | are places into self-refresh mode and memory |
| 41 | controller clock arg gating if bus is idle for |
| 42 | sr_mc_gate_idle*1024 DFI clocks. |
| 43 | |
| 44 | - rockchip,srpd_lite_idle : Defined the self-refresh power down idle |
| 45 | period, memories are places into self-refresh |
| 46 | power down mode if bus is idle for |
| 47 | srpd_lite_idle*1024 DFI clocks. This parameter |
| 48 | is for LPDDR4 only. |
| 49 | |
| 50 | - rockchip,standby_idle : Defined the standby idle period, memories are |
| 51 | places into self-refresh than controller, pi, |
| 52 | phy and dram clock will gating if bus is idle |
| 53 | for standby_idle * DFI clocks. |
| 54 | |
| 55 | - rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in |
| 56 | MHz, when ddr freq less than DRAM_DLL_DISB_FREQ, |
| 57 | ddr3 dll will bypssed note: if dll was bypassed, |
| 58 | the odt also stop working. |
| 59 | |
| 60 | - rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in |
| 61 | MHz (Mega Hz), when ddr freq less than |
| 62 | DRAM_DLL_DISB_FREQ, phy dll will bypssed. |
| 63 | note: phy dll and phy odt are independent. |
| 64 | |
| 65 | - rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined |
| 66 | the odt disable frequency in MHz (Mega Hz), |
| 67 | when ddr frequency less then ddr3_odt_disb_freq, |
| 68 | the odt on dram side and controller side are |
| 69 | both disabled. |
| 70 | |
| 71 | - rockchip,ddr3_drv : When dram type is DDR3, this parameter define |
| 72 | the dram side driver stength in ohm, default |
| 73 | value is DDR3_DS_40ohm. |
| 74 | |
| 75 | - rockchip,ddr3_odt : When dram type is DDR3, this parameter define |
| 76 | the dram side ODT stength in ohm, default value |
| 77 | is DDR3_ODT_120ohm. |
| 78 | |
| 79 | - rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define |
| 80 | the phy side CA line(incluing command line, |
| 81 | address line and clock line) driver strength. |
| 82 | Default value is PHY_DRV_ODT_40. |
| 83 | |
| 84 | - rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define |
| 85 | the phy side DQ line(incluing DQS/DQ/DM line) |
| 86 | driver strength. default value is PHY_DRV_ODT_40. |
| 87 | |
| 88 | - rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the |
| 89 | phy side odt strength, default value is |
| 90 | PHY_DRV_ODT_240. |
| 91 | |
| 92 | - rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined |
| 93 | then odt disable frequency in MHz (Mega Hz), |
| 94 | when ddr frequency less then ddr3_odt_disb_freq, |
| 95 | the odt on dram side and controller side are |
| 96 | both disabled. |
| 97 | |
| 98 | - rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define |
| 99 | the dram side driver stength in ohm, default |
| 100 | value is LP3_DS_34ohm. |
| 101 | |
| 102 | - rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define |
| 103 | the dram side ODT stength in ohm, default value |
| 104 | is LP3_ODT_240ohm. |
| 105 | |
| 106 | - rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define |
| 107 | the phy side CA line(incluing command line, |
| 108 | address line and clock line) driver strength. |
| 109 | default value is PHY_DRV_ODT_40. |
| 110 | |
| 111 | - rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define |
| 112 | the phy side DQ line(incluing DQS/DQ/DM line) |
| 113 | driver strength. default value is |
| 114 | PHY_DRV_ODT_40. |
| 115 | |
| 116 | - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define |
| 117 | the phy side odt strength, default value is |
| 118 | PHY_DRV_ODT_240. |
| 119 | |
| 120 | - rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter |
| 121 | defined the odt disable frequency in |
| 122 | MHz (Mega Hz), when ddr frequency less then |
| 123 | ddr3_odt_disb_freq, the odt on dram side and |
| 124 | controller side are both disabled. |
| 125 | |
| 126 | - rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define |
| 127 | the dram side driver stength in ohm, default |
| 128 | value is LP4_PDDS_60ohm. |
| 129 | |
| 130 | - rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define |
| 131 | the dram side ODT on dqs/dq line stength in ohm, |
| 132 | default value is LP4_DQ_ODT_40ohm. |
| 133 | |
| 134 | - rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define |
| 135 | the dram side ODT on ca line stength in ohm, |
| 136 | default value is LP4_CA_ODT_40ohm. |
| 137 | |
| 138 | - rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define |
| 139 | the phy side CA line(incluing command address |
| 140 | line) driver strength. default value is |
| 141 | PHY_DRV_ODT_40. |
| 142 | |
| 143 | - rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define |
| 144 | the phy side clock line and cs line driver |
| 145 | strength. default value is PHY_DRV_ODT_80. |
| 146 | |
| 147 | - rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define |
| 148 | the phy side DQ line(incluing DQS/DQ/DM line) |
| 149 | driver strength. default value is PHY_DRV_ODT_80. |
| 150 | |
| 151 | - rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define |
| 152 | the phy side odt strength, default value is |
| 153 | PHY_DRV_ODT_60. |
| 154 | |
| 155 | Example: |
| 156 | dmc_opp_table: dmc_opp_table { |
| 157 | compatible = "operating-points-v2"; |
| 158 | |
| 159 | opp00 { |
| 160 | opp-hz = /bits/ 64 <300000000>; |
| 161 | opp-microvolt = <900000>; |
| 162 | }; |
| 163 | opp01 { |
| 164 | opp-hz = /bits/ 64 <666000000>; |
| 165 | opp-microvolt = <900000>; |
| 166 | }; |
| 167 | }; |
| 168 | |
| 169 | dmc: dmc { |
| 170 | compatible = "rockchip,rk3399-dmc"; |
| 171 | devfreq-events = <&dfi>; |
| 172 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 173 | clocks = <&cru SCLK_DDRCLK>; |
| 174 | clock-names = "dmc_clk"; |
| 175 | operating-points-v2 = <&dmc_opp_table>; |
| 176 | center-supply = <&ppvar_centerlogic>; |
| 177 | upthreshold = <15>; |
| 178 | downdifferential = <10>; |
| 179 | rockchip,ddr3_speed_bin = <21>; |
| 180 | rockchip,pd_idle = <0x40>; |
| 181 | rockchip,sr_idle = <0x2>; |
| 182 | rockchip,sr_mc_gate_idle = <0x3>; |
| 183 | rockchip,srpd_lite_idle = <0x4>; |
| 184 | rockchip,standby_idle = <0x2000>; |
| 185 | rockchip,dram_dll_dis_freq = <300>; |
| 186 | rockchip,phy_dll_dis_freq = <125>; |
| 187 | rockchip,auto_pd_dis_freq = <666>; |
| 188 | rockchip,ddr3_odt_dis_freq = <333>; |
| 189 | rockchip,ddr3_drv = <DDR3_DS_40ohm>; |
| 190 | rockchip,ddr3_odt = <DDR3_ODT_120ohm>; |
| 191 | rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; |
| 192 | rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; |
| 193 | rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>; |
| 194 | rockchip,lpddr3_odt_dis_freq = <333>; |
| 195 | rockchip,lpddr3_drv = <LP3_DS_34ohm>; |
| 196 | rockchip,lpddr3_odt = <LP3_ODT_240ohm>; |
| 197 | rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>; |
| 198 | rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>; |
| 199 | rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>; |
| 200 | rockchip,lpddr4_odt_dis_freq = <333>; |
| 201 | rockchip,lpddr4_drv = <LP4_PDDS_60ohm>; |
| 202 | rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; |
| 203 | rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; |
| 204 | rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; |
| 205 | rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>; |
| 206 | rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>; |
| 207 | rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>; |
| 208 | status = "disabled"; |
| 209 | }; |