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Li Yang7a234d02006-10-02 20:10:10 -05001/*
2 * MPC8360E EMDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/*
14/memreserve/ 00000000 1000000;
15*/
16
Paul Gortmakercda13dd2008-01-28 16:09:36 -050017/dts-v1/;
18
Li Yang7a234d02006-10-02 20:10:10 -050019/ {
Kumar Galad71a1dc2007-02-16 09:57:22 -060020 model = "MPC8360MDS";
21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
Li Yang7a234d02006-10-02 20:10:10 -050022 #address-cells = <1>;
23 #size-cells = <1>;
Li Yang7a234d02006-10-02 20:10:10 -050024
Kumar Galaea082fa2007-12-12 01:46:12 -060025 aliases {
26 ethernet0 = &enet0;
27 ethernet1 = &enet1;
28 serial0 = &serial0;
29 serial1 = &serial1;
30 pci0 = &pci0;
31 };
32
Li Yang7a234d02006-10-02 20:10:10 -050033 cpus {
Li Yang7a234d02006-10-02 20:10:10 -050034 #address-cells = <1>;
35 #size-cells = <0>;
Li Yang7a234d02006-10-02 20:10:10 -050036
37 PowerPC,8360@0 {
38 device_type = "cpu";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050039 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <32768>; // L1, 32K
43 i-cache-size = <32768>; // L1, 32K
44 timebase-frequency = <66000000>;
45 bus-frequency = <264000000>;
46 clock-frequency = <528000000>;
Li Yang7a234d02006-10-02 20:10:10 -050047 };
48 };
49
50 memory {
51 device_type = "memory";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050052 reg = <0x00000000 0x10000000>;
Li Yang7a234d02006-10-02 20:10:10 -050053 };
54
Anton Vorontsov307db952008-08-14 21:13:42 +040055 localbus@e0005000 {
56 #address-cells = <2>;
57 #size-cells = <1>;
58 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
59 "simple-bus";
60 reg = <0xe0005000 0xd8>;
61 ranges = <0 0 0xfe000000 0x02000000
62 1 0 0xf8000000 0x00008000>;
63
64 flash@0,0 {
65 compatible = "cfi-flash";
66 reg = <0 0 0x2000000>;
67 bank-width = <2>;
68 device-width = <1>;
69 };
70
71 bcsr@1,0 {
Anton Vorontsovc9c5e522008-12-18 19:37:31 +030072 #address-cells = <1>;
73 #size-cells = <1>;
Anton Vorontsovfd657ef2008-10-18 04:23:52 +040074 compatible = "fsl,mpc8360mds-bcsr";
Anton Vorontsov307db952008-08-14 21:13:42 +040075 reg = <1 0 0x8000>;
Anton Vorontsovc9c5e522008-12-18 19:37:31 +030076 ranges = <0 1 0 0x8000>;
77
78 bcsr13: gpio-controller@d {
79 #gpio-cells = <2>;
80 compatible = "fsl,mpc8360mds-bcsr-gpio";
81 reg = <0xd 1>;
82 gpio-controller;
83 };
Anton Vorontsov307db952008-08-14 21:13:42 +040084 };
Li Yang7a234d02006-10-02 20:10:10 -050085 };
86
87 soc8360@e0000000 {
88 #address-cells = <1>;
89 #size-cells = <1>;
Li Yang7a234d02006-10-02 20:10:10 -050090 device_type = "soc";
Kim Phillipscf0d19f2008-07-29 15:29:24 -050091 compatible = "simple-bus";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050092 ranges = <0x0 0xe0000000 0x00100000>;
93 reg = <0xe0000000 0x00000200>;
94 bus-frequency = <264000000>;
Li Yang7a234d02006-10-02 20:10:10 -050095
96 wdt@200 {
97 device_type = "watchdog";
98 compatible = "mpc83xx_wdt";
Paul Gortmakercda13dd2008-01-28 16:09:36 -050099 reg = <0x200 0x100>;
Li Yang7a234d02006-10-02 20:10:10 -0500100 };
101
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400102 pmc: power@b00 {
103 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
104 reg = <0xb00 0x100 0xa00 0x100>;
105 interrupts = <80 0x8>;
106 interrupt-parent = <&ipic>;
107 };
108
Li Yang7a234d02006-10-02 20:10:10 -0500109 i2c@3000 {
Kim Phillips27f498072007-11-08 13:37:06 -0600110 #address-cells = <1>;
111 #size-cells = <0>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600112 cell-index = <0>;
Li Yang7a234d02006-10-02 20:10:10 -0500113 compatible = "fsl-i2c";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500114 reg = <0x3000 0x100>;
115 interrupts = <14 0x8>;
116 interrupt-parent = <&ipic>;
Li Yang7a234d02006-10-02 20:10:10 -0500117 dfsrr;
Kim Phillips27f498072007-11-08 13:37:06 -0600118
119 rtc@68 {
120 compatible = "dallas,ds1374";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500121 reg = <0x68>;
Kim Phillips27f498072007-11-08 13:37:06 -0600122 };
Li Yang7a234d02006-10-02 20:10:10 -0500123 };
124
125 i2c@3100 {
Kim Phillips27f498072007-11-08 13:37:06 -0600126 #address-cells = <1>;
127 #size-cells = <0>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600128 cell-index = <1>;
Li Yang7a234d02006-10-02 20:10:10 -0500129 compatible = "fsl-i2c";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500130 reg = <0x3100 0x100>;
131 interrupts = <15 0x8>;
132 interrupt-parent = <&ipic>;
Li Yang7a234d02006-10-02 20:10:10 -0500133 dfsrr;
134 };
135
Kumar Galaea082fa2007-12-12 01:46:12 -0600136 serial0: serial@4500 {
137 cell-index = <0>;
Li Yang7a234d02006-10-02 20:10:10 -0500138 device_type = "serial";
139 compatible = "ns16550";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500140 reg = <0x4500 0x100>;
141 clock-frequency = <264000000>;
142 interrupts = <9 0x8>;
143 interrupt-parent = <&ipic>;
Li Yang7a234d02006-10-02 20:10:10 -0500144 };
145
Kumar Galaea082fa2007-12-12 01:46:12 -0600146 serial1: serial@4600 {
147 cell-index = <1>;
Li Yang7a234d02006-10-02 20:10:10 -0500148 device_type = "serial";
149 compatible = "ns16550";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500150 reg = <0x4600 0x100>;
151 clock-frequency = <264000000>;
152 interrupts = <10 0x8>;
153 interrupt-parent = <&ipic>;
Li Yang7a234d02006-10-02 20:10:10 -0500154 };
155
Kumar Galadee80552008-06-27 13:45:19 -0500156 dma@82a8 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
160 reg = <0x82a8 4>;
161 ranges = <0 0x8100 0x1a8>;
162 interrupt-parent = <&ipic>;
163 interrupts = <71 8>;
164 cell-index = <0>;
165 dma-channel@0 {
166 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
167 reg = <0 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500168 cell-index = <0>;
Kumar Galadee80552008-06-27 13:45:19 -0500169 interrupt-parent = <&ipic>;
170 interrupts = <71 8>;
171 };
172 dma-channel@80 {
173 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
174 reg = <0x80 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500175 cell-index = <1>;
Kumar Galadee80552008-06-27 13:45:19 -0500176 interrupt-parent = <&ipic>;
177 interrupts = <71 8>;
178 };
179 dma-channel@100 {
180 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
181 reg = <0x100 0x80>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500182 cell-index = <2>;
Kumar Galadee80552008-06-27 13:45:19 -0500183 interrupt-parent = <&ipic>;
184 interrupts = <71 8>;
185 };
186 dma-channel@180 {
187 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
188 reg = <0x180 0x28>;
Kumar Galaaeb42762008-09-23 22:05:10 -0500189 cell-index = <3>;
Kumar Galadee80552008-06-27 13:45:19 -0500190 interrupt-parent = <&ipic>;
191 interrupts = <71 8>;
192 };
193 };
194
Li Yang7a234d02006-10-02 20:10:10 -0500195 crypto@30000 {
Kim Phillips3fd44732008-07-08 19:13:33 -0500196 compatible = "fsl,sec2.0";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500197 reg = <0x30000 0x10000>;
198 interrupts = <11 0x8>;
199 interrupt-parent = <&ipic>;
Kim Phillips3fd44732008-07-08 19:13:33 -0500200 fsl,num-channels = <4>;
201 fsl,channel-fifo-len = <24>;
202 fsl,exec-units-mask = <0x7e>;
203 fsl,descriptor-types-mask = <0x01010ebf>;
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400204 sleep = <&pmc 0x03000000>;
Li Yang7a234d02006-10-02 20:10:10 -0500205 };
206
Kumar Galad71a1dc2007-02-16 09:57:22 -0600207 ipic: pic@700 {
Li Yang7a234d02006-10-02 20:10:10 -0500208 interrupt-controller;
209 #address-cells = <0>;
210 #interrupt-cells = <2>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500211 reg = <0x700 0x100>;
Li Yang7a234d02006-10-02 20:10:10 -0500212 device_type = "ipic";
213 };
214
215 par_io@1400 {
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300216 #address-cells = <1>;
217 #size-cells = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500218 reg = <0x1400 0x100>;
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300219 ranges = <0 0x1400 0x100>;
Li Yang7a234d02006-10-02 20:10:10 -0500220 device_type = "par_io";
221 num-ports = <7>;
222
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300223 qe_pio_b: gpio-controller@18 {
224 #gpio-cells = <2>;
225 compatible = "fsl,mpc8360-qe-pario-bank",
226 "fsl,mpc8323-qe-pario-bank";
227 reg = <0x18 0x18>;
228 gpio-controller;
229 };
230
Kumar Galad71a1dc2007-02-16 09:57:22 -0600231 pio1: ucc_pin@01 {
Li Yang7a234d02006-10-02 20:10:10 -0500232 pio-map = <
233 /* port pin dir open_drain assignment has_irq */
234 0 3 1 0 1 0 /* TxD0 */
235 0 4 1 0 1 0 /* TxD1 */
236 0 5 1 0 1 0 /* TxD2 */
237 0 6 1 0 1 0 /* TxD3 */
238 1 6 1 0 3 0 /* TxD4 */
239 1 7 1 0 1 0 /* TxD5 */
240 1 9 1 0 2 0 /* TxD6 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500241 1 10 1 0 2 0 /* TxD7 */
Li Yang7a234d02006-10-02 20:10:10 -0500242 0 9 2 0 1 0 /* RxD0 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500243 0 10 2 0 1 0 /* RxD1 */
244 0 11 2 0 1 0 /* RxD2 */
245 0 12 2 0 1 0 /* RxD3 */
246 0 13 2 0 1 0 /* RxD4 */
Li Yang7a234d02006-10-02 20:10:10 -0500247 1 1 2 0 2 0 /* RxD5 */
248 1 0 2 0 2 0 /* RxD6 */
249 1 4 2 0 2 0 /* RxD7 */
250 0 7 1 0 1 0 /* TX_EN */
251 0 8 1 0 1 0 /* TX_ER */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500252 0 15 2 0 1 0 /* RX_DV */
253 0 16 2 0 1 0 /* RX_ER */
Li Yang7a234d02006-10-02 20:10:10 -0500254 0 0 2 0 1 0 /* RX_CLK */
255 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
256 2 8 2 0 1 0>; /* GTX125 - CLK9 */
257 };
Kumar Galad71a1dc2007-02-16 09:57:22 -0600258 pio2: ucc_pin@02 {
Li Yang7a234d02006-10-02 20:10:10 -0500259 pio-map = <
260 /* port pin dir open_drain assignment has_irq */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500261 0 17 1 0 1 0 /* TxD0 */
262 0 18 1 0 1 0 /* TxD1 */
263 0 19 1 0 1 0 /* TxD2 */
264 0 20 1 0 1 0 /* TxD3 */
Li Yang7a234d02006-10-02 20:10:10 -0500265 1 2 1 0 1 0 /* TxD4 */
266 1 3 1 0 2 0 /* TxD5 */
267 1 5 1 0 3 0 /* TxD6 */
268 1 8 1 0 3 0 /* TxD7 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500269 0 23 2 0 1 0 /* RxD0 */
270 0 24 2 0 1 0 /* RxD1 */
271 0 25 2 0 1 0 /* RxD2 */
272 0 26 2 0 1 0 /* RxD3 */
273 0 27 2 0 1 0 /* RxD4 */
274 1 12 2 0 2 0 /* RxD5 */
275 1 13 2 0 3 0 /* RxD6 */
276 1 11 2 0 2 0 /* RxD7 */
277 0 21 1 0 1 0 /* TX_EN */
278 0 22 1 0 1 0 /* TX_ER */
279 0 29 2 0 1 0 /* RX_DV */
280 0 30 2 0 1 0 /* RX_ER */
281 0 31 2 0 1 0 /* RX_CLK */
Li Yang7a234d02006-10-02 20:10:10 -0500282 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
283 2 3 2 0 1 0 /* GTX125 - CLK4 */
284 0 1 3 0 2 0 /* MDIO */
285 0 2 1 0 1 0>; /* MDC */
286 };
287
288 };
289 };
290
291 qe@e0100000 {
292 #address-cells = <1>;
293 #size-cells = <1>;
294 device_type = "qe";
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300295 compatible = "fsl,qe";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500296 ranges = <0x0 0xe0100000 0x00100000>;
297 reg = <0xe0100000 0x480>;
Li Yang7a234d02006-10-02 20:10:10 -0500298 brg-frequency = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500299 bus-frequency = <396000000>;
Haiying Wang01b14a92009-05-01 15:40:51 -0400300 fsl,qe-num-riscs = <2>;
301 fsl,qe-num-snums = <28>;
Li Yang7a234d02006-10-02 20:10:10 -0500302
303 muram@10000 {
Paul Gortmaker390167e2008-01-28 02:27:51 -0500304 #address-cells = <1>;
305 #size-cells = <1>;
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300306 compatible = "fsl,qe-muram", "fsl,cpm-muram";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500307 ranges = <0x0 0x00010000 0x0000c000>;
Li Yang7a234d02006-10-02 20:10:10 -0500308
Paul Gortmaker390167e2008-01-28 02:27:51 -0500309 data-only@0 {
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300310 compatible = "fsl,qe-muram-data",
311 "fsl,cpm-muram-data";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500312 reg = <0x0 0xc000>;
Li Yang7a234d02006-10-02 20:10:10 -0500313 };
314 };
315
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300316 timer@440 {
317 compatible = "fsl,mpc8360-qe-gtm",
318 "fsl,qe-gtm", "fsl,gtm";
319 reg = <0x440 0x40>;
320 clock-frequency = <132000000>;
321 interrupts = <12 13 14 15>;
322 interrupt-parent = <&qeic>;
323 };
324
Li Yang7a234d02006-10-02 20:10:10 -0500325 spi@4c0 {
Anton Vorontsovf3a2b292008-01-24 18:40:07 +0300326 cell-index = <0>;
327 compatible = "fsl,spi";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500328 reg = <0x4c0 0x40>;
Li Yang7a234d02006-10-02 20:10:10 -0500329 interrupts = <2>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500330 interrupt-parent = <&qeic>;
Li Yang7a234d02006-10-02 20:10:10 -0500331 mode = "cpu";
332 };
333
334 spi@500 {
Anton Vorontsovf3a2b292008-01-24 18:40:07 +0300335 cell-index = <1>;
336 compatible = "fsl,spi";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500337 reg = <0x500 0x40>;
Li Yang7a234d02006-10-02 20:10:10 -0500338 interrupts = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500339 interrupt-parent = <&qeic>;
Li Yang7a234d02006-10-02 20:10:10 -0500340 mode = "cpu";
341 };
342
343 usb@6c0 {
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300344 compatible = "fsl,mpc8360-qe-usb",
345 "fsl,mpc8323-qe-usb";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500346 reg = <0x6c0 0x40 0x8b00 0x100>;
347 interrupts = <11>;
348 interrupt-parent = <&qeic>;
Anton Vorontsovc9c5e522008-12-18 19:37:31 +0300349 fsl,fullspeed-clock = "clk21";
350 fsl,lowspeed-clock = "brg9";
351 gpios = <&qe_pio_b 2 0 /* USBOE */
352 &qe_pio_b 3 0 /* USBTP */
353 &qe_pio_b 8 0 /* USBTN */
354 &qe_pio_b 9 0 /* USBRP */
355 &qe_pio_b 11 0 /* USBRN */
356 &bcsr13 5 0 /* SPEED */
357 &bcsr13 4 1>; /* POWER */
Li Yang7a234d02006-10-02 20:10:10 -0500358 };
359
Kumar Galae77b28e2007-12-12 00:28:35 -0600360 enet0: ucc@2000 {
Li Yang7a234d02006-10-02 20:10:10 -0500361 device_type = "network";
362 compatible = "ucc_geth";
Kumar Galae77b28e2007-12-12 00:28:35 -0600363 cell-index = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500364 reg = <0x2000 0x200>;
365 interrupts = <32>;
366 interrupt-parent = <&qeic>;
Timur Tabieae98262007-06-22 14:33:15 -0500367 local-mac-address = [ 00 00 00 00 00 00 ];
Timur Tabi9fb1e352007-12-03 15:17:59 -0600368 rx-clock-name = "none";
369 tx-clock-name = "clk9";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500370 phy-handle = <&phy0>;
Kim Phillips0fd8c472007-04-24 07:26:14 +1000371 phy-connection-type = "rgmii-id";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500372 pio-handle = <&pio1>;
Li Yang7a234d02006-10-02 20:10:10 -0500373 };
374
Kumar Galae77b28e2007-12-12 00:28:35 -0600375 enet1: ucc@3000 {
Li Yang7a234d02006-10-02 20:10:10 -0500376 device_type = "network";
377 compatible = "ucc_geth";
Kumar Galae77b28e2007-12-12 00:28:35 -0600378 cell-index = <2>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500379 reg = <0x3000 0x200>;
380 interrupts = <33>;
381 interrupt-parent = <&qeic>;
Timur Tabieae98262007-06-22 14:33:15 -0500382 local-mac-address = [ 00 00 00 00 00 00 ];
Timur Tabi9fb1e352007-12-03 15:17:59 -0600383 rx-clock-name = "none";
384 tx-clock-name = "clk4";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500385 phy-handle = <&phy1>;
Kim Phillips0fd8c472007-04-24 07:26:14 +1000386 phy-connection-type = "rgmii-id";
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500387 pio-handle = <&pio2>;
Li Yang7a234d02006-10-02 20:10:10 -0500388 };
389
390 mdio@2120 {
391 #address-cells = <1>;
392 #size-cells = <0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500393 reg = <0x2120 0x18>;
Anton Vorontsovd0a2f822008-01-24 18:40:01 +0300394 compatible = "fsl,ucc-mdio";
Li Yang7a234d02006-10-02 20:10:10 -0500395
Kumar Galad71a1dc2007-02-16 09:57:22 -0600396 phy0: ethernet-phy@00 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500397 interrupt-parent = <&ipic>;
398 interrupts = <17 0x8>;
399 reg = <0x0>;
Li Yang7a234d02006-10-02 20:10:10 -0500400 device_type = "ethernet-phy";
Li Yang7a234d02006-10-02 20:10:10 -0500401 };
Kumar Galad71a1dc2007-02-16 09:57:22 -0600402 phy1: ethernet-phy@01 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500403 interrupt-parent = <&ipic>;
404 interrupts = <18 0x8>;
405 reg = <0x1>;
Li Yang7a234d02006-10-02 20:10:10 -0500406 device_type = "ethernet-phy";
Li Yang7a234d02006-10-02 20:10:10 -0500407 };
408 };
409
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300410 qeic: interrupt-controller@80 {
Li Yang7a234d02006-10-02 20:10:10 -0500411 interrupt-controller;
Anton Vorontsova2dd70a2008-01-24 18:39:59 +0300412 compatible = "fsl,qe-ic";
Li Yang7a234d02006-10-02 20:10:10 -0500413 #address-cells = <0>;
414 #interrupt-cells = <1>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500415 reg = <0x80 0x80>;
Li Yang7a234d02006-10-02 20:10:10 -0500416 big-endian;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500417 interrupts = <32 0x8 33 0x8>; // high:32 low:33
418 interrupt-parent = <&ipic>;
Li Yang7a234d02006-10-02 20:10:10 -0500419 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500420 };
Li Yang7a234d02006-10-02 20:10:10 -0500421
Kumar Galaea082fa2007-12-12 01:46:12 -0600422 pci0: pci@e0008500 {
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500423 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500424 interrupt-map = <
425
426 /* IDSEL 0x11 AD17 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500427 0x8800 0x0 0x0 0x1 &ipic 20 0x8
428 0x8800 0x0 0x0 0x2 &ipic 21 0x8
429 0x8800 0x0 0x0 0x3 &ipic 22 0x8
430 0x8800 0x0 0x0 0x4 &ipic 23 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500431
432 /* IDSEL 0x12 AD18 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500433 0x9000 0x0 0x0 0x1 &ipic 22 0x8
434 0x9000 0x0 0x0 0x2 &ipic 23 0x8
435 0x9000 0x0 0x0 0x3 &ipic 20 0x8
436 0x9000 0x0 0x0 0x4 &ipic 21 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500437
438 /* IDSEL 0x13 AD19 */
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500439 0x9800 0x0 0x0 0x1 &ipic 23 0x8
440 0x9800 0x0 0x0 0x2 &ipic 20 0x8
441 0x9800 0x0 0x0 0x3 &ipic 21 0x8
442 0x9800 0x0 0x0 0x4 &ipic 22 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500443
444 /* IDSEL 0x15 AD21*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500445 0xa800 0x0 0x0 0x1 &ipic 20 0x8
446 0xa800 0x0 0x0 0x2 &ipic 21 0x8
447 0xa800 0x0 0x0 0x3 &ipic 22 0x8
448 0xa800 0x0 0x0 0x4 &ipic 23 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500449
450 /* IDSEL 0x16 AD22*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500451 0xb000 0x0 0x0 0x1 &ipic 23 0x8
452 0xb000 0x0 0x0 0x2 &ipic 20 0x8
453 0xb000 0x0 0x0 0x3 &ipic 21 0x8
454 0xb000 0x0 0x0 0x4 &ipic 22 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500455
456 /* IDSEL 0x17 AD23*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500457 0xb800 0x0 0x0 0x1 &ipic 22 0x8
458 0xb800 0x0 0x0 0x2 &ipic 23 0x8
459 0xb800 0x0 0x0 0x3 &ipic 20 0x8
460 0xb800 0x0 0x0 0x4 &ipic 21 0x8
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500461
462 /* IDSEL 0x18 AD24*/
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500463 0xc000 0x0 0x0 0x1 &ipic 21 0x8
464 0xc000 0x0 0x0 0x2 &ipic 22 0x8
465 0xc000 0x0 0x0 0x3 &ipic 23 0x8
466 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
467 interrupt-parent = <&ipic>;
468 interrupts = <66 0x8>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500469 bus-range = <0 0>;
Paul Gortmakercda13dd2008-01-28 16:09:36 -0500470 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
471 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
472 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
473 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500474 #interrupt-cells = <1>;
475 #size-cells = <2>;
476 #address-cells = <3>;
John Rigby5b70a092008-10-07 13:00:18 -0600477 reg = <0xe0008500 0x100 /* internal registers */
478 0xe0008300 0x8>; /* config space access registers */
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500479 compatible = "fsl,mpc8349-pci";
480 device_type = "pci";
Anton Vorontsov1f8a25d2009-09-16 01:44:02 +0400481 sleep = <&pmc 0x00010000>;
Li Yang7a234d02006-10-02 20:10:10 -0500482 };
483};