| Prabhakar Kushwaha | eb2c5d9 | 2011-04-08 17:57:05 +0530 | [diff] [blame] | 1 | /* |
| 2 | * P2020 Device Tree Source |
| 3 | * |
| 4 | * Copyright 2011 Freescale Semiconductor Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /dts-v1/; |
| 13 | / { |
| 14 | compatible = "fsl,P2020"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; |
| 21 | |
| 22 | PowerPC,P2020@0 { |
| 23 | device_type = "cpu"; |
| 24 | reg = <0x0>; |
| 25 | next-level-cache = <&L2>; |
| 26 | }; |
| 27 | |
| 28 | PowerPC,P2020@1 { |
| 29 | device_type = "cpu"; |
| 30 | reg = <0x1>; |
| 31 | next-level-cache = <&L2>; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | localbus@ffe05000 { |
| 36 | #address-cells = <2>; |
| 37 | #size-cells = <1>; |
| 38 | compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; |
| 39 | reg = <0 0xffe05000 0 0x1000>; |
| 40 | interrupts = <19 2>; |
| 41 | interrupt-parent = <&mpic>; |
| 42 | }; |
| 43 | |
| 44 | soc@ffe00000 { |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <1>; |
| 47 | device_type = "soc"; |
| 48 | compatible = "fsl,p2020-immr", "simple-bus"; |
| 49 | ranges = <0x0 0x0 0xffe00000 0x100000>; |
| 50 | bus-frequency = <0>; // Filled out by uboot. |
| 51 | |
| 52 | ecm-law@0 { |
| 53 | compatible = "fsl,ecm-law"; |
| 54 | reg = <0x0 0x1000>; |
| 55 | fsl,num-laws = <12>; |
| 56 | }; |
| 57 | |
| 58 | ecm@1000 { |
| 59 | compatible = "fsl,p2020-ecm", "fsl,ecm"; |
| 60 | reg = <0x1000 0x1000>; |
| 61 | interrupts = <17 2>; |
| 62 | interrupt-parent = <&mpic>; |
| 63 | }; |
| 64 | |
| 65 | memory-controller@2000 { |
| 66 | compatible = "fsl,p2020-memory-controller"; |
| 67 | reg = <0x2000 0x1000>; |
| 68 | interrupt-parent = <&mpic>; |
| 69 | interrupts = <18 2>; |
| 70 | }; |
| 71 | |
| 72 | i2c@3000 { |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <0>; |
| 75 | cell-index = <0>; |
| 76 | compatible = "fsl-i2c"; |
| 77 | reg = <0x3000 0x100>; |
| 78 | interrupts = <43 2>; |
| 79 | interrupt-parent = <&mpic>; |
| 80 | dfsrr; |
| 81 | }; |
| 82 | |
| 83 | i2c@3100 { |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | cell-index = <1>; |
| 87 | compatible = "fsl-i2c"; |
| 88 | reg = <0x3100 0x100>; |
| 89 | interrupts = <43 2>; |
| 90 | interrupt-parent = <&mpic>; |
| 91 | dfsrr; |
| 92 | }; |
| 93 | |
| 94 | serial0: serial@4500 { |
| 95 | cell-index = <0>; |
| 96 | device_type = "serial"; |
| 97 | compatible = "ns16550"; |
| 98 | reg = <0x4500 0x100>; |
| 99 | clock-frequency = <0>; |
| 100 | interrupts = <42 2>; |
| 101 | interrupt-parent = <&mpic>; |
| 102 | }; |
| 103 | |
| 104 | serial1: serial@4600 { |
| 105 | cell-index = <1>; |
| 106 | device_type = "serial"; |
| 107 | compatible = "ns16550"; |
| 108 | reg = <0x4600 0x100>; |
| 109 | clock-frequency = <0>; |
| 110 | interrupts = <42 2>; |
| 111 | interrupt-parent = <&mpic>; |
| 112 | }; |
| 113 | |
| 114 | spi@7000 { |
| 115 | cell-index = <0>; |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; |
| 118 | compatible = "fsl,espi"; |
| 119 | reg = <0x7000 0x1000>; |
| 120 | interrupts = <59 0x2>; |
| 121 | interrupt-parent = <&mpic>; |
| 122 | mode = "cpu"; |
| 123 | }; |
| 124 | |
| 125 | dma@c300 { |
| 126 | #address-cells = <1>; |
| 127 | #size-cells = <1>; |
| 128 | compatible = "fsl,eloplus-dma"; |
| 129 | reg = <0xc300 0x4>; |
| 130 | ranges = <0x0 0xc100 0x200>; |
| 131 | cell-index = <1>; |
| 132 | dma-channel@0 { |
| 133 | compatible = "fsl,eloplus-dma-channel"; |
| 134 | reg = <0x0 0x80>; |
| 135 | cell-index = <0>; |
| 136 | interrupt-parent = <&mpic>; |
| 137 | interrupts = <76 2>; |
| 138 | }; |
| 139 | dma-channel@80 { |
| 140 | compatible = "fsl,eloplus-dma-channel"; |
| 141 | reg = <0x80 0x80>; |
| 142 | cell-index = <1>; |
| 143 | interrupt-parent = <&mpic>; |
| 144 | interrupts = <77 2>; |
| 145 | }; |
| 146 | dma-channel@100 { |
| 147 | compatible = "fsl,eloplus-dma-channel"; |
| 148 | reg = <0x100 0x80>; |
| 149 | cell-index = <2>; |
| 150 | interrupt-parent = <&mpic>; |
| 151 | interrupts = <78 2>; |
| 152 | }; |
| 153 | dma-channel@180 { |
| 154 | compatible = "fsl,eloplus-dma-channel"; |
| 155 | reg = <0x180 0x80>; |
| 156 | cell-index = <3>; |
| 157 | interrupt-parent = <&mpic>; |
| 158 | interrupts = <79 2>; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | gpio: gpio-controller@f000 { |
| 163 | #gpio-cells = <2>; |
| 164 | compatible = "fsl,mpc8572-gpio"; |
| 165 | reg = <0xf000 0x100>; |
| 166 | interrupts = <47 0x2>; |
| 167 | interrupt-parent = <&mpic>; |
| 168 | gpio-controller; |
| 169 | }; |
| 170 | |
| 171 | L2: l2-cache-controller@20000 { |
| 172 | compatible = "fsl,p2020-l2-cache-controller"; |
| 173 | reg = <0x20000 0x1000>; |
| 174 | cache-line-size = <32>; // 32 bytes |
| 175 | cache-size = <0x80000>; // L2,512K |
| 176 | interrupt-parent = <&mpic>; |
| 177 | interrupts = <16 2>; |
| 178 | }; |
| 179 | |
| 180 | dma@21300 { |
| 181 | #address-cells = <1>; |
| 182 | #size-cells = <1>; |
| 183 | compatible = "fsl,eloplus-dma"; |
| 184 | reg = <0x21300 0x4>; |
| 185 | ranges = <0x0 0x21100 0x200>; |
| 186 | cell-index = <0>; |
| 187 | dma-channel@0 { |
| 188 | compatible = "fsl,eloplus-dma-channel"; |
| 189 | reg = <0x0 0x80>; |
| 190 | cell-index = <0>; |
| 191 | interrupt-parent = <&mpic>; |
| 192 | interrupts = <20 2>; |
| 193 | }; |
| 194 | dma-channel@80 { |
| 195 | compatible = "fsl,eloplus-dma-channel"; |
| 196 | reg = <0x80 0x80>; |
| 197 | cell-index = <1>; |
| 198 | interrupt-parent = <&mpic>; |
| 199 | interrupts = <21 2>; |
| 200 | }; |
| 201 | dma-channel@100 { |
| 202 | compatible = "fsl,eloplus-dma-channel"; |
| 203 | reg = <0x100 0x80>; |
| 204 | cell-index = <2>; |
| 205 | interrupt-parent = <&mpic>; |
| 206 | interrupts = <22 2>; |
| 207 | }; |
| 208 | dma-channel@180 { |
| 209 | compatible = "fsl,eloplus-dma-channel"; |
| 210 | reg = <0x180 0x80>; |
| 211 | cell-index = <3>; |
| 212 | interrupt-parent = <&mpic>; |
| 213 | interrupts = <23 2>; |
| 214 | }; |
| 215 | }; |
| 216 | |
| 217 | usb@22000 { |
| 218 | #address-cells = <1>; |
| 219 | #size-cells = <0>; |
| 220 | compatible = "fsl-usb2-dr"; |
| 221 | reg = <0x22000 0x1000>; |
| 222 | interrupt-parent = <&mpic>; |
| 223 | interrupts = <28 0x2>; |
| 224 | }; |
| 225 | |
| 226 | mdio@24520 { |
| 227 | #address-cells = <1>; |
| 228 | #size-cells = <0>; |
| 229 | compatible = "fsl,gianfar-mdio"; |
| 230 | reg = <0x24520 0x20>; |
| 231 | }; |
| 232 | |
| 233 | mdio@25520 { |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <0>; |
| 236 | compatible = "fsl,gianfar-tbi"; |
| 237 | reg = <0x26520 0x20>; |
| 238 | }; |
| 239 | |
| 240 | mdio@26520 { |
| 241 | #address-cells = <1>; |
| 242 | #size-cells = <0>; |
| 243 | compatible = "fsl,gianfar-tbi"; |
| 244 | reg = <0x520 0x20>; |
| 245 | }; |
| 246 | |
| 247 | enet0: ethernet@24000 { |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <1>; |
| 250 | cell-index = <0>; |
| 251 | device_type = "network"; |
| 252 | model = "eTSEC"; |
| 253 | compatible = "gianfar"; |
| 254 | reg = <0x24000 0x1000>; |
| 255 | ranges = <0x0 0x24000 0x1000>; |
| 256 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 257 | interrupts = <29 2 30 2 34 2>; |
| 258 | interrupt-parent = <&mpic>; |
| 259 | }; |
| 260 | |
| 261 | enet1: ethernet@25000 { |
| 262 | #address-cells = <1>; |
| 263 | #size-cells = <1>; |
| 264 | cell-index = <1>; |
| 265 | device_type = "network"; |
| 266 | model = "eTSEC"; |
| 267 | compatible = "gianfar"; |
| 268 | reg = <0x25000 0x1000>; |
| 269 | ranges = <0x0 0x25000 0x1000>; |
| 270 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 271 | interrupts = <35 2 36 2 40 2>; |
| 272 | interrupt-parent = <&mpic>; |
| 273 | |
| 274 | }; |
| 275 | |
| 276 | enet2: ethernet@26000 { |
| 277 | #address-cells = <1>; |
| 278 | #size-cells = <1>; |
| 279 | cell-index = <2>; |
| 280 | device_type = "network"; |
| 281 | model = "eTSEC"; |
| 282 | compatible = "gianfar"; |
| 283 | reg = <0x26000 0x1000>; |
| 284 | ranges = <0x0 0x26000 0x1000>; |
| 285 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 286 | interrupts = <31 2 32 2 33 2>; |
| 287 | interrupt-parent = <&mpic>; |
| 288 | |
| 289 | }; |
| 290 | |
| 291 | sdhci@2e000 { |
| 292 | compatible = "fsl,p2020-esdhc", "fsl,esdhc"; |
| 293 | reg = <0x2e000 0x1000>; |
| 294 | interrupts = <72 0x2>; |
| 295 | interrupt-parent = <&mpic>; |
| 296 | /* Filled in by U-Boot */ |
| 297 | clock-frequency = <0>; |
| 298 | }; |
| 299 | |
| 300 | crypto@30000 { |
| 301 | compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", |
| 302 | "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; |
| 303 | reg = <0x30000 0x10000>; |
| 304 | interrupts = <45 2 58 2>; |
| 305 | interrupt-parent = <&mpic>; |
| 306 | fsl,num-channels = <4>; |
| 307 | fsl,channel-fifo-len = <24>; |
| 308 | fsl,exec-units-mask = <0xbfe>; |
| 309 | fsl,descriptor-types-mask = <0x3ab0ebf>; |
| 310 | }; |
| 311 | |
| 312 | mpic: pic@40000 { |
| 313 | interrupt-controller; |
| 314 | #address-cells = <0>; |
| 315 | #interrupt-cells = <2>; |
| 316 | reg = <0x40000 0x40000>; |
| 317 | compatible = "chrp,open-pic"; |
| 318 | device_type = "open-pic"; |
| 319 | }; |
| 320 | |
| 321 | msi@41600 { |
| 322 | compatible = "fsl,p2020-msi", "fsl,mpic-msi"; |
| 323 | reg = <0x41600 0x80>; |
| 324 | msi-available-ranges = <0 0x100>; |
| 325 | interrupts = < |
| 326 | 0xe0 0 |
| 327 | 0xe1 0 |
| 328 | 0xe2 0 |
| 329 | 0xe3 0 |
| 330 | 0xe4 0 |
| 331 | 0xe5 0 |
| 332 | 0xe6 0 |
| 333 | 0xe7 0>; |
| 334 | interrupt-parent = <&mpic>; |
| 335 | }; |
| 336 | |
| 337 | global-utilities@e0000 { //global utilities block |
| 338 | compatible = "fsl,p2020-guts"; |
| 339 | reg = <0xe0000 0x1000>; |
| 340 | fsl,has-rstcr; |
| 341 | }; |
| 342 | }; |
| 343 | |
| 344 | pci0: pcie@ffe08000 { |
| 345 | compatible = "fsl,mpc8548-pcie"; |
| 346 | device_type = "pci"; |
| 347 | #interrupt-cells = <1>; |
| 348 | #size-cells = <2>; |
| 349 | #address-cells = <3>; |
| 350 | reg = <0 0xffe08000 0 0x1000>; |
| 351 | bus-range = <0 255>; |
| 352 | clock-frequency = <33333333>; |
| 353 | interrupt-parent = <&mpic>; |
| 354 | interrupts = <24 2>; |
| 355 | }; |
| 356 | |
| 357 | pci1: pcie@ffe09000 { |
| 358 | compatible = "fsl,mpc8548-pcie"; |
| 359 | device_type = "pci"; |
| 360 | #interrupt-cells = <1>; |
| 361 | #size-cells = <2>; |
| 362 | #address-cells = <3>; |
| 363 | reg = <0 0xffe09000 0 0x1000>; |
| 364 | bus-range = <0 255>; |
| 365 | clock-frequency = <33333333>; |
| 366 | interrupt-parent = <&mpic>; |
| 367 | interrupts = <25 2>; |
| 368 | }; |
| 369 | |
| 370 | pci2: pcie@ffe0a000 { |
| 371 | compatible = "fsl,mpc8548-pcie"; |
| 372 | device_type = "pci"; |
| 373 | #interrupt-cells = <1>; |
| 374 | #size-cells = <2>; |
| 375 | #address-cells = <3>; |
| 376 | reg = <0 0xffe0a000 0 0x1000>; |
| 377 | bus-range = <0 255>; |
| 378 | clock-frequency = <33333333>; |
| 379 | interrupt-parent = <&mpic>; |
| 380 | interrupts = <26 2>; |
| 381 | }; |
| 382 | }; |