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Daniel Mackaff18a62012-07-25 17:56:48 +02001/* The pxa3xx skeleton simply augments the 2xx version */
Robert Jarzmik85fe55c2014-07-30 22:51:03 +02002#include "pxa2xx.dtsi"
Robert Jarzmikd96672e2015-02-07 13:13:24 +01003#include "dt-bindings/clock/pxa-clock.h"
Daniel Mackaff18a62012-07-25 17:56:48 +02004
5/ {
6 model = "Marvell PXA27x familiy SoC";
7 compatible = "marvell,pxa27x";
8
9 pxabus {
Robert Jarzmik0cd49142015-06-20 10:17:26 +020010 pdma: dma-controller@40000000 {
11 compatible = "marvell,pdma-1.0";
12 reg = <0x40000000 0x10000>;
13 interrupts = <25>;
14 #dma-channels = <32>;
15 #dma-cells = <2>;
16 status = "okay";
17 };
18
Daniel Mackaff18a62012-07-25 17:56:48 +020019 pxairq: interrupt-controller@40d00000 {
20 marvell,intc-priority;
21 marvell,intc-nr-irqs = <34>;
22 };
Mike Dunne7b4a8d2013-09-21 12:19:34 -070023
Robert Jarzmikd96672e2015-02-07 13:13:24 +010024 gpio: gpio@40e00000 {
25 compatible = "intel,pxa27x-gpio";
26 clocks = <&clks CLK_NONE>;
27 };
28
Robert Jarzmik0ec19392015-06-20 10:17:31 +020029 pxa27x_ohci: usb@4c000000 {
30 compatible = "marvell,pxa-ohci";
31 reg = <0x4c000000 0x10000>;
32 interrupts = <3>;
33 clocks = <&clks CLK_USBHOST>;
34 status = "disabled";
35 };
36
Mike Dunne7b4a8d2013-09-21 12:19:34 -070037 pwm0: pwm@40b00000 {
38 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
39 reg = <0x40b00000 0x10>;
40 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010041 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070042 };
43
44 pwm1: pwm@40b00010 {
45 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
46 reg = <0x40b00010 0x10>;
47 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010048 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070049 };
50
51 pwm2: pwm@40c00000 {
52 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
53 reg = <0x40c00000 0x10>;
54 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010055 clocks = <&clks CLK_PWM0>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070056 };
57
58 pwm3: pwm@40c00010 {
59 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
60 reg = <0x40c00010 0x10>;
61 #pwm-cells = <1>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010062 clocks = <&clks CLK_PWM1>;
Mike Dunne7b4a8d2013-09-21 12:19:34 -070063 };
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010064
65 pwri2c: i2c@40f000180 {
66 compatible = "mrvl,pxa-i2c";
67 reg = <0x40f00180 0x24>;
68 interrupts = <6>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010069 clocks = <&clks CLK_PWRI2C>;
Robert Jarzmikfb185392015-06-20 10:17:30 +020070 #address-cells = <0x1>;
71 #size-cells = <0>;
Robert Jarzmikf374d1e2015-02-07 13:26:09 +010072 status = "disabled";
73 };
Robert Jarzmikd96672e2015-02-07 13:13:24 +010074
Robert Jarzmik361818c2015-02-07 13:27:55 +010075 pxa27x_udc: udc@40600000 {
76 compatible = "marvell,pxa270-udc";
77 reg = <0x40600000 0x10000>;
78 interrupts = <11>;
79 clocks = <&clks CLK_USB>;
80 status = "disabled";
81 };
Robert Jarzmik8dcba812015-02-07 13:19:38 +010082
83 keypad: keypad@41500000 {
84 compatible = "marvell,pxa27x-keypad";
85 reg = <0x41500000 0x4c>;
86 interrupts = <4>;
87 clocks = <&clks CLK_KEYPAD>;
88 status = "disabled";
89 };
Robert Jarzmik796b7dc2015-06-20 10:17:29 +020090
91 pxa_camera: imaging@50000000 {
92 compatible = "marvell,pxa270-qci";
93 reg = <0x50000000 0x1000>;
94 interrupts = <33>;
95 dmas = <&pdma 68 0 /* Y channel */
96 &pdma 69 0 /* U channel */
97 &pdma 70 0>; /* V channel */
98 dma-names = "CI_Y", "CI_U", "CI_V";
99
100 clocks = <&clks CLK_CAMERA>;
101 clock-names = "ciclk";
102 clock-frequency = <5000000>;
103 clock-output-names = "qci_mclk";
104
105 status = "disabled";
106 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200107 };
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200108
109 clocks {
110 /*
111 * The muxing of external clocks/internal dividers for osc* clock
112 * sources has been hidden under the carpet by now.
113 */
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges;
117
Robert Jarzmikd96672e2015-02-07 13:13:24 +0100118 clks: pxa2xx_clks@41300004 {
119 compatible = "marvell,pxa270-clocks";
Robert Jarzmik85fe55c2014-07-30 22:51:03 +0200120 #clock-cells = <1>;
121 status = "okay";
122 };
123 };
Robert Jarzmik8dd30752014-10-12 22:11:08 +0200124
125 timer@40a00000 {
126 compatible = "marvell,pxa-timer";
127 reg = <0x40a00000 0x20>;
128 interrupts = <26>;
129 clocks = <&clks CLK_OSTIMER>;
130 status = "okay";
131 };
Daniel Mackaff18a62012-07-25 17:56:48 +0200132};