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H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02001#ifndef __ASM_MSR_INDEX_H
2#define __ASM_MSR_INDEX_H
3
4/* CPU model specific register (MSR) numbers */
5
6/* x86-64 specific MSRs */
7#define MSR_EFER 0xc0000080 /* extended feature register */
8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15
16/* EFER bits: */
17#define _EFER_SCE 0 /* SYSCALL/SYSRET */
18#define _EFER_LME 8 /* Long mode enable */
19#define _EFER_LMA 10 /* Long mode active (read-only) */
20#define _EFER_NX 11 /* No execute enable */
21
22#define EFER_SCE (1<<_EFER_SCE)
23#define EFER_LME (1<<_EFER_LME)
24#define EFER_LMA (1<<_EFER_LMA)
25#define EFER_NX (1<<_EFER_NX)
26
27/* Intel MSRs. Some also available on other CPUs */
28#define MSR_IA32_PERFCTR0 0x000000c1
29#define MSR_IA32_PERFCTR1 0x000000c2
30#define MSR_FSB_FREQ 0x000000cd
31
32#define MSR_MTRRcap 0x000000fe
33#define MSR_IA32_BBL_CR_CTL 0x00000119
34
35#define MSR_IA32_SYSENTER_CS 0x00000174
36#define MSR_IA32_SYSENTER_ESP 0x00000175
37#define MSR_IA32_SYSENTER_EIP 0x00000176
38
39#define MSR_IA32_MCG_CAP 0x00000179
40#define MSR_IA32_MCG_STATUS 0x0000017a
41#define MSR_IA32_MCG_CTL 0x0000017b
42
43#define MSR_IA32_PEBS_ENABLE 0x000003f1
44#define MSR_IA32_DS_AREA 0x00000600
45#define MSR_IA32_PERF_CAPABILITIES 0x00000345
46
47#define MSR_MTRRfix64K_00000 0x00000250
48#define MSR_MTRRfix16K_80000 0x00000258
49#define MSR_MTRRfix16K_A0000 0x00000259
50#define MSR_MTRRfix4K_C0000 0x00000268
51#define MSR_MTRRfix4K_C8000 0x00000269
52#define MSR_MTRRfix4K_D0000 0x0000026a
53#define MSR_MTRRfix4K_D8000 0x0000026b
54#define MSR_MTRRfix4K_E0000 0x0000026c
55#define MSR_MTRRfix4K_E8000 0x0000026d
56#define MSR_MTRRfix4K_F0000 0x0000026e
57#define MSR_MTRRfix4K_F8000 0x0000026f
58#define MSR_MTRRdefType 0x000002ff
59
60#define MSR_IA32_DEBUGCTLMSR 0x000001d9
61#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
62#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
63#define MSR_IA32_LASTINTFROMIP 0x000001dd
64#define MSR_IA32_LASTINTTOIP 0x000001de
65
Roland McGrathd2499d82008-01-30 13:30:54 +010066/* DEBUGCTLMSR bits (others vary by model): */
67#define _DEBUGCTLMSR_LBR 0 /* last branch recording */
68#define _DEBUGCTLMSR_BTF 1 /* single-step on branches */
69
70#define DEBUGCTLMSR_LBR (1UL << _DEBUGCTLMSR_LBR)
71#define DEBUGCTLMSR_BTF (1UL << _DEBUGCTLMSR_BTF)
72
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020073#define MSR_IA32_MC0_CTL 0x00000400
74#define MSR_IA32_MC0_STATUS 0x00000401
75#define MSR_IA32_MC0_ADDR 0x00000402
76#define MSR_IA32_MC0_MISC 0x00000403
77
78#define MSR_P6_PERFCTR0 0x000000c1
79#define MSR_P6_PERFCTR1 0x000000c2
80#define MSR_P6_EVNTSEL0 0x00000186
81#define MSR_P6_EVNTSEL1 0x00000187
82
Stephane Eranian4f8a6b12007-10-19 20:35:03 +020083/* AMD64 MSRs. Not complete. See the architecture manual for a more
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020084 complete list. */
Stephane Eranian4f8a6b12007-10-19 20:35:03 +020085
86#define MSR_AMD64_IBSFETCHCTL 0xc0011030
87#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
88#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
89#define MSR_AMD64_IBSOPCTL 0xc0011033
90#define MSR_AMD64_IBSOPRIP 0xc0011034
91#define MSR_AMD64_IBSOPDATA 0xc0011035
92#define MSR_AMD64_IBSOPDATA2 0xc0011036
93#define MSR_AMD64_IBSOPDATA3 0xc0011037
94#define MSR_AMD64_IBSDCLINAD 0xc0011038
95#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
96#define MSR_AMD64_IBSCTL 0xc001103a
97
Yinghai Lu2274c332008-01-30 13:33:18 +010098/* Fam 10h MSRs */
99#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
100#define FAM10H_MMIO_CONF_ENABLE (1<<0)
101#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
102#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
103#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff
104#define FAM10H_MMIO_CONF_BASE_SHIFT 20
105
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200106/* K8 MSRs */
107#define MSR_K8_TOP_MEM1 0xc001001a
108#define MSR_K8_TOP_MEM2 0xc001001d
109#define MSR_K8_SYSCFG 0xc0010010
110#define MSR_K8_HWCR 0xc0010015
111#define MSR_K8_ENABLE_C1E 0xc0010055
112#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
113#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
114#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
115
116/* K7 MSRs */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200117#define MSR_K7_EVNTSEL0 0xc0010000
118#define MSR_K7_PERFCTR0 0xc0010004
119#define MSR_K7_EVNTSEL1 0xc0010001
120#define MSR_K7_PERFCTR1 0xc0010005
121#define MSR_K7_EVNTSEL2 0xc0010002
122#define MSR_K7_PERFCTR2 0xc0010006
123#define MSR_K7_EVNTSEL3 0xc0010003
124#define MSR_K7_PERFCTR3 0xc0010007
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200125#define MSR_K7_CLK_CTL 0xc001001b
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200126#define MSR_K7_HWCR 0xc0010015
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200127#define MSR_K7_FID_VID_CTL 0xc0010041
128#define MSR_K7_FID_VID_STATUS 0xc0010042
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200129
130/* K6 MSRs */
131#define MSR_K6_EFER 0xc0000080
132#define MSR_K6_STAR 0xc0000081
133#define MSR_K6_WHCR 0xc0000082
134#define MSR_K6_UWCCR 0xc0000085
135#define MSR_K6_EPMR 0xc0000086
136#define MSR_K6_PSOR 0xc0000087
137#define MSR_K6_PFIR 0xc0000088
138
139/* Centaur-Hauls/IDT defined MSRs. */
140#define MSR_IDT_FCR1 0x00000107
141#define MSR_IDT_FCR2 0x00000108
142#define MSR_IDT_FCR3 0x00000109
143#define MSR_IDT_FCR4 0x0000010a
144
145#define MSR_IDT_MCR0 0x00000110
146#define MSR_IDT_MCR1 0x00000111
147#define MSR_IDT_MCR2 0x00000112
148#define MSR_IDT_MCR3 0x00000113
149#define MSR_IDT_MCR4 0x00000114
150#define MSR_IDT_MCR5 0x00000115
151#define MSR_IDT_MCR6 0x00000116
152#define MSR_IDT_MCR7 0x00000117
153#define MSR_IDT_MCR_CTRL 0x00000120
154
155/* VIA Cyrix defined MSRs*/
156#define MSR_VIA_FCR 0x00001107
157#define MSR_VIA_LONGHAUL 0x0000110a
158#define MSR_VIA_RNG 0x0000110b
159#define MSR_VIA_BCR2 0x00001147
160
161/* Transmeta defined MSRs */
162#define MSR_TMTA_LONGRUN_CTRL 0x80868010
163#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
164#define MSR_TMTA_LRTI_READOUT 0x80868018
165#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
166
167/* Intel defined MSRs. */
168#define MSR_IA32_P5_MC_ADDR 0x00000000
169#define MSR_IA32_P5_MC_TYPE 0x00000001
170#define MSR_IA32_TSC 0x00000010
171#define MSR_IA32_PLATFORM_ID 0x00000017
172#define MSR_IA32_EBL_CR_POWERON 0x0000002a
173
174#define MSR_IA32_APICBASE 0x0000001b
175#define MSR_IA32_APICBASE_BSP (1<<8)
176#define MSR_IA32_APICBASE_ENABLE (1<<11)
177#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
178
179#define MSR_IA32_UCODE_WRITE 0x00000079
180#define MSR_IA32_UCODE_REV 0x0000008b
181
182#define MSR_IA32_PERF_STATUS 0x00000198
183#define MSR_IA32_PERF_CTL 0x00000199
184
185#define MSR_IA32_MPERF 0x000000e7
186#define MSR_IA32_APERF 0x000000e8
187
188#define MSR_IA32_THERM_CONTROL 0x0000019a
189#define MSR_IA32_THERM_INTERRUPT 0x0000019b
190#define MSR_IA32_THERM_STATUS 0x0000019c
191#define MSR_IA32_MISC_ENABLE 0x000001a0
192
193/* Intel Model 6 */
194#define MSR_P6_EVNTSEL0 0x00000186
195#define MSR_P6_EVNTSEL1 0x00000187
196
197/* P4/Xeon+ specific */
198#define MSR_IA32_MCG_EAX 0x00000180
199#define MSR_IA32_MCG_EBX 0x00000181
200#define MSR_IA32_MCG_ECX 0x00000182
201#define MSR_IA32_MCG_EDX 0x00000183
202#define MSR_IA32_MCG_ESI 0x00000184
203#define MSR_IA32_MCG_EDI 0x00000185
204#define MSR_IA32_MCG_EBP 0x00000186
205#define MSR_IA32_MCG_ESP 0x00000187
206#define MSR_IA32_MCG_EFLAGS 0x00000188
207#define MSR_IA32_MCG_EIP 0x00000189
208#define MSR_IA32_MCG_RESERVED 0x0000018a
209
210/* Pentium IV performance counter MSRs */
211#define MSR_P4_BPU_PERFCTR0 0x00000300
212#define MSR_P4_BPU_PERFCTR1 0x00000301
213#define MSR_P4_BPU_PERFCTR2 0x00000302
214#define MSR_P4_BPU_PERFCTR3 0x00000303
215#define MSR_P4_MS_PERFCTR0 0x00000304
216#define MSR_P4_MS_PERFCTR1 0x00000305
217#define MSR_P4_MS_PERFCTR2 0x00000306
218#define MSR_P4_MS_PERFCTR3 0x00000307
219#define MSR_P4_FLAME_PERFCTR0 0x00000308
220#define MSR_P4_FLAME_PERFCTR1 0x00000309
221#define MSR_P4_FLAME_PERFCTR2 0x0000030a
222#define MSR_P4_FLAME_PERFCTR3 0x0000030b
223#define MSR_P4_IQ_PERFCTR0 0x0000030c
224#define MSR_P4_IQ_PERFCTR1 0x0000030d
225#define MSR_P4_IQ_PERFCTR2 0x0000030e
226#define MSR_P4_IQ_PERFCTR3 0x0000030f
227#define MSR_P4_IQ_PERFCTR4 0x00000310
228#define MSR_P4_IQ_PERFCTR5 0x00000311
229#define MSR_P4_BPU_CCCR0 0x00000360
230#define MSR_P4_BPU_CCCR1 0x00000361
231#define MSR_P4_BPU_CCCR2 0x00000362
232#define MSR_P4_BPU_CCCR3 0x00000363
233#define MSR_P4_MS_CCCR0 0x00000364
234#define MSR_P4_MS_CCCR1 0x00000365
235#define MSR_P4_MS_CCCR2 0x00000366
236#define MSR_P4_MS_CCCR3 0x00000367
237#define MSR_P4_FLAME_CCCR0 0x00000368
238#define MSR_P4_FLAME_CCCR1 0x00000369
239#define MSR_P4_FLAME_CCCR2 0x0000036a
240#define MSR_P4_FLAME_CCCR3 0x0000036b
241#define MSR_P4_IQ_CCCR0 0x0000036c
242#define MSR_P4_IQ_CCCR1 0x0000036d
243#define MSR_P4_IQ_CCCR2 0x0000036e
244#define MSR_P4_IQ_CCCR3 0x0000036f
245#define MSR_P4_IQ_CCCR4 0x00000370
246#define MSR_P4_IQ_CCCR5 0x00000371
247#define MSR_P4_ALF_ESCR0 0x000003ca
248#define MSR_P4_ALF_ESCR1 0x000003cb
249#define MSR_P4_BPU_ESCR0 0x000003b2
250#define MSR_P4_BPU_ESCR1 0x000003b3
251#define MSR_P4_BSU_ESCR0 0x000003a0
252#define MSR_P4_BSU_ESCR1 0x000003a1
253#define MSR_P4_CRU_ESCR0 0x000003b8
254#define MSR_P4_CRU_ESCR1 0x000003b9
255#define MSR_P4_CRU_ESCR2 0x000003cc
256#define MSR_P4_CRU_ESCR3 0x000003cd
257#define MSR_P4_CRU_ESCR4 0x000003e0
258#define MSR_P4_CRU_ESCR5 0x000003e1
259#define MSR_P4_DAC_ESCR0 0x000003a8
260#define MSR_P4_DAC_ESCR1 0x000003a9
261#define MSR_P4_FIRM_ESCR0 0x000003a4
262#define MSR_P4_FIRM_ESCR1 0x000003a5
263#define MSR_P4_FLAME_ESCR0 0x000003a6
264#define MSR_P4_FLAME_ESCR1 0x000003a7
265#define MSR_P4_FSB_ESCR0 0x000003a2
266#define MSR_P4_FSB_ESCR1 0x000003a3
267#define MSR_P4_IQ_ESCR0 0x000003ba
268#define MSR_P4_IQ_ESCR1 0x000003bb
269#define MSR_P4_IS_ESCR0 0x000003b4
270#define MSR_P4_IS_ESCR1 0x000003b5
271#define MSR_P4_ITLB_ESCR0 0x000003b6
272#define MSR_P4_ITLB_ESCR1 0x000003b7
273#define MSR_P4_IX_ESCR0 0x000003c8
274#define MSR_P4_IX_ESCR1 0x000003c9
275#define MSR_P4_MOB_ESCR0 0x000003aa
276#define MSR_P4_MOB_ESCR1 0x000003ab
277#define MSR_P4_MS_ESCR0 0x000003c0
278#define MSR_P4_MS_ESCR1 0x000003c1
279#define MSR_P4_PMH_ESCR0 0x000003ac
280#define MSR_P4_PMH_ESCR1 0x000003ad
281#define MSR_P4_RAT_ESCR0 0x000003bc
282#define MSR_P4_RAT_ESCR1 0x000003bd
283#define MSR_P4_SAAT_ESCR0 0x000003ae
284#define MSR_P4_SAAT_ESCR1 0x000003af
285#define MSR_P4_SSU_ESCR0 0x000003be
286#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
287
288#define MSR_P4_TBPU_ESCR0 0x000003c2
289#define MSR_P4_TBPU_ESCR1 0x000003c3
290#define MSR_P4_TC_ESCR0 0x000003c4
291#define MSR_P4_TC_ESCR1 0x000003c5
292#define MSR_P4_U2L_ESCR0 0x000003b0
293#define MSR_P4_U2L_ESCR1 0x000003b1
294
295/* Intel Core-based CPU performance counters */
296#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
297#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
298#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
299#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
300#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
301#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
302#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
303
304/* Geode defined MSRs */
305#define MSR_GEODE_BUSCONT_CONF0 0x00001900
306
307#endif /* __ASM_MSR_INDEX_H */