Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h |
| 2 | * |
| 3 | * Copyright (c) 2006,2007,2009 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * |
| 7 | * S3C CPU frequency scaling support - core support |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <plat/cpu-freq.h> |
| 15 | |
Ben Dooks | e6d197a | 2009-07-30 23:23:42 +0100 | [diff] [blame] | 16 | struct seq_file; |
| 17 | |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 18 | #define MAX_BANKS (8) |
| 19 | #define S3C2412_MAX_IO (8) |
| 20 | |
| 21 | /** |
| 22 | * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings |
| 23 | * @bankcon: The cached version of settings in this structure. |
| 24 | * @tacp: |
| 25 | * @tacs: Time from address valid to nCS asserted. |
| 26 | * @tcos: Time from nCS asserted to nOE or nWE asserted. |
| 27 | * @tacc: Time that nOE or nWE is asserted. |
| 28 | * @tcoh: Time nCS is held after nOE or nWE are released. |
| 29 | * @tcah: Time address is held for after |
| 30 | * @nwait_en: Whether nWAIT is enabled for this bank. |
| 31 | * |
| 32 | * This structure represents the IO timings for a S3C2410 style IO bank |
| 33 | * used by the CPU frequency support if it needs to change the settings |
| 34 | * of the IO. |
| 35 | */ |
| 36 | struct s3c2410_iobank_timing { |
| 37 | unsigned long bankcon; |
| 38 | unsigned int tacp; |
| 39 | unsigned int tacs; |
| 40 | unsigned int tcos; |
| 41 | unsigned int tacc; |
| 42 | unsigned int tcoh; /* nCS hold afrer nOE/nWE */ |
| 43 | unsigned int tcah; /* Address hold after nCS */ |
| 44 | unsigned char nwait_en; /* nWait enabled for bank. */ |
| 45 | }; |
| 46 | |
Ben Dooks | 140780a | 2009-07-30 23:23:37 +0100 | [diff] [blame] | 47 | /** |
| 48 | * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO |
| 49 | * @idcy: The idle cycle time between transactions. |
| 50 | * @wstrd: nCS release to end of read cycle. |
| 51 | * @wstwr: nCS release to end of write cycle. |
| 52 | * @wstoen: nCS assertion to nOE assertion time. |
| 53 | * @wstwen: nCS assertion to nWE assertion time. |
| 54 | * @wstbrd: Burst ready delay. |
| 55 | * @smbidcyr: Register cache for smbidcyr value. |
| 56 | * @smbwstrd: Register cache for smbwstrd value. |
| 57 | * @smbwstwr: Register cache for smbwstwr value. |
| 58 | * @smbwstoen: Register cache for smbwstoen value. |
| 59 | * @smbwstwen: Register cache for smbwstwen value. |
| 60 | * @smbwstbrd: Register cache for smbwstbrd value. |
| 61 | * |
| 62 | * Timing information for a IO bank on an S3C2412 or similar system which |
| 63 | * uses a PL093 block. |
| 64 | */ |
| 65 | struct s3c2412_iobank_timing { |
| 66 | unsigned int idcy; |
| 67 | unsigned int wstrd; |
| 68 | unsigned int wstwr; |
| 69 | unsigned int wstoen; |
| 70 | unsigned int wstwen; |
| 71 | unsigned int wstbrd; |
| 72 | |
| 73 | /* register cache */ |
| 74 | unsigned char smbidcyr; |
| 75 | unsigned char smbwstrd; |
| 76 | unsigned char smbwstwr; |
| 77 | unsigned char smbwstoen; |
| 78 | unsigned char smbwstwen; |
| 79 | unsigned char smbwstbrd; |
| 80 | }; |
| 81 | |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 82 | union s3c_iobank { |
Ben Dooks | 140780a | 2009-07-30 23:23:37 +0100 | [diff] [blame] | 83 | struct s3c2410_iobank_timing *io_2410; |
| 84 | struct s3c2412_iobank_timing *io_2412; |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * struct s3c_iotimings - Chip IO timings holder |
| 89 | * @bank: The timings for each IO bank. |
| 90 | */ |
| 91 | struct s3c_iotimings { |
| 92 | union s3c_iobank bank[MAX_BANKS]; |
| 93 | }; |
| 94 | |
| 95 | /** |
| 96 | * struct s3c_plltab - PLL table information. |
| 97 | * @vals: List of PLL values. |
| 98 | * @size: Size of the PLL table @vals. |
| 99 | */ |
| 100 | struct s3c_plltab { |
| 101 | struct s3c_pllval *vals; |
| 102 | int size; |
| 103 | }; |
| 104 | |
| 105 | /** |
Ben Dooks | d6fc87d | 2009-07-30 23:23:23 +0100 | [diff] [blame] | 106 | * struct s3c_cpufreq_config - current cpu frequency configuration |
| 107 | * @freq: The current settings for the core clocks. |
| 108 | * @max: Maxium settings, derived from core, board and user settings. |
| 109 | * @pll: The PLL table entry for the current PLL settings. |
| 110 | * @divs: The divisor settings for the core clocks. |
| 111 | * @info: The current core driver information. |
| 112 | * @board: The information for the board we are running on. |
| 113 | * @lock_pll: Set if the PLL settings cannot be changed. |
| 114 | * |
| 115 | * This is for the core drivers that need to know information about |
| 116 | * the current settings and values. It should not be needed by any |
| 117 | * device drivers. |
| 118 | */ |
| 119 | struct s3c_cpufreq_config { |
| 120 | struct s3c_freq freq; |
| 121 | struct s3c_freq max; |
| 122 | struct cpufreq_frequency_table pll; |
| 123 | struct s3c_clkdivs divs; |
| 124 | struct s3c_cpufreq_info *info; /* for core, not drivers */ |
| 125 | struct s3c_cpufreq_board *board; |
| 126 | |
| 127 | unsigned int lock_pll:1; |
| 128 | }; |
| 129 | |
| 130 | /** |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 131 | * struct s3c_cpufreq_info - Information for the CPU frequency driver. |
| 132 | * @name: The name of this implementation. |
| 133 | * @max: The maximum frequencies for the system. |
| 134 | * @latency: Transition latency to give to cpufreq. |
| 135 | * @locktime_m: The lock-time in uS for the MPLL. |
| 136 | * @locktime_u: The lock-time in uS for the UPLL. |
| 137 | * @locttime_bits: The number of bits each LOCKTIME field. |
| 138 | * @need_pll: Set if this driver needs to change the PLL values to acheive |
| 139 | * any frequency changes. This is really only need by devices like the |
| 140 | * S3C2410 where there is no or limited divider between the PLL and the |
| 141 | * ARMCLK. |
| 142 | * @resume_clocks: Update the clocks on resume. |
| 143 | * @get_iotiming: Get the current IO timing data, mainly for use at start. |
| 144 | * @set_iotiming: Update the IO timings from the cached copies calculated |
| 145 | * from the @calc_iotiming entry when changing the frequency. |
| 146 | * @calc_iotiming: Calculate and update the cached copies of the IO timings |
| 147 | * from the newly calculated frequencies. |
| 148 | * @calc_freqtable: Calculate (fill in) the given frequency table from the |
| 149 | * current frequency configuration. If the table passed in is NULL, |
| 150 | * then the return is the number of elements to be filled for allocation |
| 151 | * of the table. |
| 152 | * @set_refresh: Set the memory refresh configuration. |
| 153 | * @set_fvco: Set the PLL frequencies. |
| 154 | * @set_divs: Update the clock divisors. |
| 155 | * @calc_divs: Calculate the clock divisors. |
| 156 | */ |
| 157 | struct s3c_cpufreq_info { |
| 158 | const char *name; |
| 159 | struct s3c_freq max; |
| 160 | |
| 161 | unsigned int latency; |
| 162 | |
| 163 | unsigned int locktime_m; |
| 164 | unsigned int locktime_u; |
| 165 | unsigned char locktime_bits; |
| 166 | |
| 167 | unsigned int need_pll:1; |
| 168 | |
| 169 | /* driver routines */ |
| 170 | |
| 171 | void (*resume_clocks)(void); |
| 172 | |
| 173 | int (*get_iotiming)(struct s3c_cpufreq_config *cfg, |
| 174 | struct s3c_iotimings *timings); |
| 175 | |
| 176 | void (*set_iotiming)(struct s3c_cpufreq_config *cfg, |
| 177 | struct s3c_iotimings *timings); |
| 178 | |
| 179 | int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, |
| 180 | struct s3c_iotimings *timings); |
| 181 | |
| 182 | int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, |
| 183 | struct cpufreq_frequency_table *t, |
| 184 | size_t table_size); |
| 185 | |
Ben Dooks | e6d197a | 2009-07-30 23:23:42 +0100 | [diff] [blame] | 186 | void (*debug_io_show)(struct seq_file *seq, |
| 187 | struct s3c_cpufreq_config *cfg, |
| 188 | union s3c_iobank *iob); |
| 189 | |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 190 | void (*set_refresh)(struct s3c_cpufreq_config *cfg); |
| 191 | void (*set_fvco)(struct s3c_cpufreq_config *cfg); |
| 192 | void (*set_divs)(struct s3c_cpufreq_config *cfg); |
| 193 | int (*calc_divs)(struct s3c_cpufreq_config *cfg); |
| 194 | }; |
| 195 | |
| 196 | extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); |
| 197 | |
| 198 | extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); |
| 199 | |
Ben Dooks | e6d197a | 2009-07-30 23:23:42 +0100 | [diff] [blame] | 200 | /* exports and utilities for debugfs */ |
| 201 | extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); |
| 202 | extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); |
| 203 | |
| 204 | extern void s3c2410_iotiming_debugfs(struct seq_file *seq, |
| 205 | struct s3c_cpufreq_config *cfg, |
| 206 | union s3c_iobank *iob); |
| 207 | |
| 208 | extern void s3c2412_iotiming_debugfs(struct seq_file *seq, |
| 209 | struct s3c_cpufreq_config *cfg, |
| 210 | union s3c_iobank *iob); |
| 211 | |
| 212 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS |
| 213 | #define s3c_cpufreq_debugfs_call(x) x |
| 214 | #else |
| 215 | #define s3c_cpufreq_debugfs_call(x) NULL |
| 216 | #endif |
| 217 | |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 218 | /* Useful utility functions. */ |
| 219 | |
| 220 | extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); |
| 221 | |
| 222 | /* S3C2410 and compatible exported functions */ |
| 223 | |
| 224 | extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); |
| 225 | |
| 226 | extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, |
| 227 | struct s3c_iotimings *iot); |
| 228 | |
| 229 | extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, |
| 230 | struct s3c_iotimings *timings); |
| 231 | |
| 232 | extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, |
| 233 | struct s3c_iotimings *iot); |
| 234 | |
| 235 | extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); |
| 236 | |
Ben Dooks | 140780a | 2009-07-30 23:23:37 +0100 | [diff] [blame] | 237 | /* S3C2412 compatible routines */ |
| 238 | |
| 239 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, |
| 240 | struct s3c_iotimings *timings); |
| 241 | |
| 242 | extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, |
| 243 | struct s3c_iotimings *timings); |
| 244 | |
| 245 | extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, |
| 246 | struct s3c_iotimings *iot); |
| 247 | |
| 248 | extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, |
| 249 | struct s3c_iotimings *iot); |
| 250 | |
Ben Dooks | 2e4ea6e | 2009-07-30 23:23:21 +0100 | [diff] [blame] | 251 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG |
| 252 | #define s3c_freq_dbg(x...) printk(KERN_INFO x) |
| 253 | #else |
| 254 | #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) |
| 255 | #endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ |
| 256 | |
| 257 | #ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG |
| 258 | #define s3c_freq_iodbg(x...) printk(KERN_INFO x) |
| 259 | #else |
| 260 | #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) |
| 261 | #endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ |
| 262 | |
| 263 | static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, |
| 264 | int index, size_t table_size, |
| 265 | unsigned int freq) |
| 266 | { |
| 267 | if (index < 0) |
| 268 | return index; |
| 269 | |
| 270 | if (table) { |
| 271 | if (index >= table_size) |
| 272 | return -ENOMEM; |
| 273 | |
| 274 | s3c_freq_dbg("%s: { %d = %u kHz }\n", |
| 275 | __func__, index, freq); |
| 276 | |
| 277 | table[index].index = index; |
| 278 | table[index].frequency = freq; |
| 279 | } |
| 280 | |
| 281 | return index + 1; |
| 282 | } |