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AnilKumar Ch32bb00e2012-06-22 15:10:49 +05301/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Florian Vaussardeb33ef662013-06-03 16:12:22 +020010#include "am33xx.dtsi"
AnilKumar Ch32bb00e2012-06-22 15:10:49 +053011
12/ {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
AnilKumar Chefeedcf2012-08-31 15:07:20 +053016 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
AnilKumar Ch32bb00e2012-06-22 15:10:49 +053022 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
Vaibhav Hiremath53d91032012-08-15 16:53:25 +053026
AnilKumar Ch1b2a9702012-08-21 16:47:29 +053027 vbat: fixedregulator@0 {
28 compatible = "regulator-fixed";
29 regulator-name = "vbat";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 regulator-boot-on;
33 };
AnilKumar Ch492dd022012-09-20 02:49:29 +053034
35 lis3_reg: fixedregulator@1 {
36 compatible = "regulator-fixed";
37 regulator-name = "lis3_reg";
38 regulator-boot-on;
39 };
AnilKumar Ch2ca1d312012-11-06 19:18:30 +053040
41 matrix_keypad: matrix_keypad@0 {
42 compatible = "gpio-matrix-keypad";
43 debounce-delay-ms = <5>;
44 col-scan-delay-us = <2>;
45
Florian Vaussarde94233c2013-06-03 16:12:23 +020046 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
47 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
48 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
AnilKumar Ch2ca1d312012-11-06 19:18:30 +053049
Florian Vaussarde94233c2013-06-03 16:12:23 +020050 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
51 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
AnilKumar Ch2ca1d312012-11-06 19:18:30 +053052
53 linux,keymap = <0x0000008b /* MENU */
54 0x0100009e /* BACK */
55 0x02000069 /* LEFT */
56 0x0001006a /* RIGHT */
57 0x0101001c /* ENTER */
58 0x0201006c>; /* DOWN */
59 };
AnilKumar Ch822c9932012-11-06 19:18:32 +053060
61 gpio_keys: volume_keys@0 {
62 compatible = "gpio-keys";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 autorepeat;
66
67 switch@9 {
68 label = "volume-up";
69 linux,code = <115>;
Florian Vaussarde94233c2013-06-03 16:12:23 +020070 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
AnilKumar Ch822c9932012-11-06 19:18:32 +053071 gpio-key,wakeup;
72 };
73
74 switch@10 {
75 label = "volume-down";
76 linux,code = <114>;
Florian Vaussarde94233c2013-06-03 16:12:23 +020077 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
AnilKumar Ch822c9932012-11-06 19:18:32 +053078 gpio-key,wakeup;
79 };
80 };
Philip Avinash6993fd02013-06-06 15:52:38 +020081
82 backlight {
83 compatible = "pwm-backlight";
84 pwms = <&ecap0 0 50000 0>;
85 brightness-levels = <0 51 53 56 62 75 101 152 255>;
86 default-brightness-level = <8>;
87 };
AnilKumar Ch1b2a9702012-08-21 16:47:29 +053088};
89
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +020090&am33xx_pinmux {
91 pinctrl-names = "default";
92 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
93
94 matrix_keypad_s0: matrix_keypad_s0 {
95 pinctrl-single,pins = <
96 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
97 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
98 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
99 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
100 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
101 >;
102 };
103
104 volume_keys_s0: volume_keys_s0 {
105 pinctrl-single,pins = <
106 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
107 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
108 >;
109 };
110
111 i2c0_pins: pinmux_i2c0_pins {
112 pinctrl-single,pins = <
113 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
114 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
115 >;
116 };
117
118 i2c1_pins: pinmux_i2c1_pins {
119 pinctrl-single,pins = <
120 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
121 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
122 >;
123 };
124
125 uart0_pins: pinmux_uart0_pins {
126 pinctrl-single,pins = <
127 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
128 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
129 >;
130 };
131
132 clkout2_pin: pinmux_clkout2_pin {
133 pinctrl-single,pins = <
134 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
135 >;
136 };
137
138 nandflash_pins_s0: nandflash_pins_s0 {
139 pinctrl-single,pins = <
140 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
141 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
142 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
143 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
144 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
145 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
146 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
147 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
148 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
149 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
150 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
151 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
152 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
153 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
154 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
155 >;
156 };
157
158 ecap0_pins: backlight_pins {
159 pinctrl-single,pins = <
160 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
161 >;
162 };
163
164 cpsw_default: cpsw_default {
165 pinctrl-single,pins = <
166 /* Slave 1 */
167 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
168 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
169 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
170 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
171 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
172 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
173 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
174 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
175 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
176 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
177 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
178 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
179 >;
180 };
181
182 cpsw_sleep: cpsw_sleep {
183 pinctrl-single,pins = <
184 /* Slave 1 reset value */
185 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
188 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
189 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
190 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
193 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
194 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
195 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
196 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
197 >;
198 };
199
200 davinci_mdio_default: davinci_mdio_default {
201 pinctrl-single,pins = <
202 /* MDIO */
203 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
204 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
205 >;
206 };
207
208 davinci_mdio_sleep: davinci_mdio_sleep {
209 pinctrl-single,pins = <
210 /* MDIO reset value */
211 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
212 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
213 >;
214 };
215};
216
Javier Martinez Canillase0efaaf2013-09-20 17:42:19 +0200217&uart0 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&uart0_pins>;
220
221 status = "okay";
222};
223
224&i2c0 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&i2c0_pins>;
227
228 status = "okay";
229 clock-frequency = <400000>;
230
231 tps: tps@2d {
232 reg = <0x2d>;
233 };
234};
235
236&usb {
237 status = "okay";
238
239 control@44e10000 {
240 status = "okay";
241 };
242
243 usb-phy@47401300 {
244 status = "okay";
245 };
246
247 usb-phy@47401b00 {
248 status = "okay";
249 };
250
251 usb@47401000 {
252 status = "okay";
253 };
254
255 usb@47401800 {
256 status = "okay";
257 dr_mode = "host";
258 };
259
260 dma-controller@07402000 {
261 status = "okay";
262 };
263};
264
265&i2c1 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&i2c1_pins>;
268
269 status = "okay";
270 clock-frequency = <100000>;
271
272 lis331dlh: lis331dlh@18 {
273 compatible = "st,lis331dlh", "st,lis3lv02d";
274 reg = <0x18>;
275 Vdd-supply = <&lis3_reg>;
276 Vdd_IO-supply = <&lis3_reg>;
277
278 st,click-single-x;
279 st,click-single-y;
280 st,click-single-z;
281 st,click-thresh-x = <10>;
282 st,click-thresh-y = <10>;
283 st,click-thresh-z = <10>;
284 st,irq1-click;
285 st,irq2-click;
286 st,wakeup-x-lo;
287 st,wakeup-x-hi;
288 st,wakeup-y-lo;
289 st,wakeup-y-hi;
290 st,wakeup-z-lo;
291 st,wakeup-z-hi;
292 st,min-limit-x = <120>;
293 st,min-limit-y = <120>;
294 st,min-limit-z = <140>;
295 st,max-limit-x = <550>;
296 st,max-limit-y = <550>;
297 st,max-limit-z = <750>;
298 };
299
300 tsl2550: tsl2550@39 {
301 compatible = "taos,tsl2550";
302 reg = <0x39>;
303 };
304
305 tmp275: tmp275@48 {
306 compatible = "ti,tmp275";
307 reg = <0x48>;
308 };
309};
310
311&elm {
312 status = "okay";
313};
314
315&epwmss0 {
316 status = "okay";
317
318 ecap0: ecap@48300100 {
319 status = "okay";
320 pinctrl-names = "default";
321 pinctrl-0 = <&ecap0_pins>;
322 };
323};
324
325&gpmc {
326 status = "okay";
327 pinctrl-names = "default";
328 pinctrl-0 = <&nandflash_pins_s0>;
329 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
330 nand@0,0 {
331 reg = <0 0 0>; /* CS0, offset 0 */
332 nand-bus-width = <8>;
333 ti,nand-ecc-opt = "bch8";
334 gpmc,device-nand = "true";
335 gpmc,device-width = <1>;
336 gpmc,sync-clk-ps = <0>;
337 gpmc,cs-on-ns = <0>;
338 gpmc,cs-rd-off-ns = <44>;
339 gpmc,cs-wr-off-ns = <44>;
340 gpmc,adv-on-ns = <6>;
341 gpmc,adv-rd-off-ns = <34>;
342 gpmc,adv-wr-off-ns = <44>;
343 gpmc,we-on-ns = <0>;
344 gpmc,we-off-ns = <40>;
345 gpmc,oe-on-ns = <0>;
346 gpmc,oe-off-ns = <54>;
347 gpmc,access-ns = <64>;
348 gpmc,rd-cycle-ns = <82>;
349 gpmc,wr-cycle-ns = <82>;
350 gpmc,wait-on-read = "true";
351 gpmc,wait-on-write = "true";
352 gpmc,bus-turnaround-ns = <0>;
353 gpmc,cycle2cycle-delay-ns = <0>;
354 gpmc,clk-activation-ns = <0>;
355 gpmc,wait-monitoring-ns = <0>;
356 gpmc,wr-access-ns = <40>;
357 gpmc,wr-data-mux-bus-ns = <0>;
358
359 #address-cells = <1>;
360 #size-cells = <1>;
361 elm_id = <&elm>;
362
363 /* MTD partition table */
364 partition@0 {
365 label = "SPL1";
366 reg = <0x00000000 0x000020000>;
367 };
368
369 partition@1 {
370 label = "SPL2";
371 reg = <0x00020000 0x00020000>;
372 };
373
374 partition@2 {
375 label = "SPL3";
376 reg = <0x00040000 0x00020000>;
377 };
378
379 partition@3 {
380 label = "SPL4";
381 reg = <0x00060000 0x00020000>;
382 };
383
384 partition@4 {
385 label = "U-boot";
386 reg = <0x00080000 0x001e0000>;
387 };
388
389 partition@5 {
390 label = "environment";
391 reg = <0x00260000 0x00020000>;
392 };
393
394 partition@6 {
395 label = "Kernel";
396 reg = <0x00280000 0x00500000>;
397 };
398
399 partition@7 {
400 label = "File-System";
401 reg = <0x00780000 0x0F880000>;
402 };
403 };
404};
405
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200406#include "tps65910.dtsi"
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530407
408&tps {
409 vcc1-supply = <&vbat>;
410 vcc2-supply = <&vbat>;
411 vcc3-supply = <&vbat>;
412 vcc4-supply = <&vbat>;
413 vcc5-supply = <&vbat>;
414 vcc6-supply = <&vbat>;
415 vcc7-supply = <&vbat>;
416 vccio-supply = <&vbat>;
417
418 regulators {
419 vrtc_reg: regulator@0 {
420 regulator-always-on;
421 };
422
423 vio_reg: regulator@1 {
424 regulator-always-on;
425 };
426
427 vdd1_reg: regulator@2 {
428 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
429 regulator-name = "vdd_mpu";
430 regulator-min-microvolt = <912500>;
431 regulator-max-microvolt = <1312500>;
432 regulator-boot-on;
433 regulator-always-on;
434 };
435
436 vdd2_reg: regulator@3 {
437 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
438 regulator-name = "vdd_core";
439 regulator-min-microvolt = <912500>;
440 regulator-max-microvolt = <1150000>;
441 regulator-boot-on;
442 regulator-always-on;
443 };
444
445 vdd3_reg: regulator@4 {
446 regulator-always-on;
447 };
448
449 vdig1_reg: regulator@5 {
450 regulator-always-on;
451 };
452
453 vdig2_reg: regulator@6 {
454 regulator-always-on;
455 };
456
457 vpll_reg: regulator@7 {
458 regulator-always-on;
459 };
460
461 vdac_reg: regulator@8 {
462 regulator-always-on;
463 };
464
465 vaux1_reg: regulator@9 {
466 regulator-always-on;
467 };
468
469 vaux2_reg: regulator@10 {
470 regulator-always-on;
471 };
472
473 vaux33_reg: regulator@11 {
474 regulator-always-on;
475 };
476
477 vmmc_reg: regulator@12 {
Matt Porter55b44522013-09-10 14:24:39 -0500478 regulator-min-microvolt = <1800000>;
479 regulator-max-microvolt = <3300000>;
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530480 regulator-always-on;
481 };
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530482 };
AnilKumar Ch32bb00e2012-06-22 15:10:49 +0530483};
Mugunthan V N1a39a652012-11-14 09:08:00 +0000484
Mugunthan V N50c7d2b2013-06-07 17:02:54 +0530485&mac {
486 pinctrl-names = "default", "sleep";
487 pinctrl-0 = <&cpsw_default>;
488 pinctrl-1 = <&cpsw_sleep>;
489};
490
491&davinci_mdio {
492 pinctrl-names = "default", "sleep";
493 pinctrl-0 = <&davinci_mdio_default>;
494 pinctrl-1 = <&davinci_mdio_sleep>;
495};
496
Mugunthan V N1a39a652012-11-14 09:08:00 +0000497&cpsw_emac0 {
498 phy_id = <&davinci_mdio>, <0>;
Mugunthan V N6d75afe2013-06-03 20:10:11 +0000499 phy-mode = "rgmii-txid";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000500};
501
502&cpsw_emac1 {
503 phy_id = <&davinci_mdio>, <1>;
Mugunthan V N6d75afe2013-06-03 20:10:11 +0000504 phy-mode = "rgmii-txid";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000505};
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000506
507&tscadc {
508 status = "okay";
509 tsc {
510 ti,wires = <4>;
511 ti,x-plate-resistance = <200>;
512 ti,coordiante-readouts = <5>;
513 ti,wire-config = <0x00 0x11 0x22 0x33>;
514 };
515
516 adc {
Sebastian Andrzej Siewior18926ed2013-05-29 17:39:02 +0200517 ti,adc-channels = <4 5 6 7>;
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000518 };
519};
Matt Porter55b44522013-09-10 14:24:39 -0500520
521&mmc1 {
522 status = "okay";
523 vmmc-supply = <&vmmc_reg>;
524};