Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
Paul Walmsley | 8c810e7 | 2011-02-25 13:56:40 -0700 | [diff] [blame] | 2 | * OMAP2430 clock data |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 3 | * |
Paul Walmsley | 8c810e7 | 2011-02-25 13:56:40 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2011 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
Paul Walmsley | 8c810e7 | 2011-02-25 13:56:40 -0700 | [diff] [blame] | 7 | * Contacts: |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/clk.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 18 | #include <linux/list.h> |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 19 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 20 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 21 | #include "iomap.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 22 | #include "clock.h" |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 23 | #include "clock2xxx.h" |
| 24 | #include "opp2xxx.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 25 | #include "cm2xxx_3xxx.h" |
| 26 | #include "prm2xxx_3xxx.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 27 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 30 | #include "control.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 31 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 32 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR |
| 33 | |
| 34 | /* |
| 35 | * 2430 clock tree. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 36 | * |
Paul Walmsley | 8c810e7 | 2011-02-25 13:56:40 -0700 | [diff] [blame] | 37 | * NOTE:In many cases here we are assigning a 'default' parent. In |
| 38 | * many cases the parent is selectable. The set parent calls will |
| 39 | * also switch sources. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 40 | * |
| 41 | * Several sources are given initial rates which may be wrong, this will |
| 42 | * be fixed up in the init func. |
| 43 | * |
| 44 | * Things are broadly separated below by clock domains. It is |
Paul Walmsley | 8c810e7 | 2011-02-25 13:56:40 -0700 | [diff] [blame] | 45 | * noteworthy that most peripherals have dependencies on multiple clock |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 46 | * domains. Many get their interface clocks from the L4 domain, but get |
| 47 | * functional clocks from fixed sources or other core domain derived |
| 48 | * clocks. |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 49 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 50 | |
| 51 | /* Base external input clocks */ |
| 52 | static struct clk func_32k_ck = { |
| 53 | .name = "func_32k_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 54 | .ops = &clkops_null, |
Paul Walmsley | 3f9cfd3 | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 55 | .rate = 32768, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 56 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 57 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 58 | |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 59 | static struct clk secure_32k_ck = { |
| 60 | .name = "secure_32k_ck", |
| 61 | .ops = &clkops_null, |
| 62 | .rate = 32768, |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 63 | .clkdm_name = "wkup_clkdm", |
| 64 | }; |
| 65 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 66 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 67 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 68 | .name = "osc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 69 | .ops = &clkops_oscck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 70 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 71 | .recalc = &omap2_osc_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 72 | }; |
| 73 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 74 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 75 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 76 | .name = "sys_ck", /* ~ ref_clk also */ |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 77 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 78 | .parent = &osc_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 79 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 80 | .recalc = &omap2xxx_sys_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 81 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 82 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 83 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 84 | .name = "alt_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 85 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 86 | .rate = 54000000, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 87 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 88 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 89 | |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 90 | /* Optional external clock input for McBSP CLKS */ |
| 91 | static struct clk mcbsp_clks = { |
| 92 | .name = "mcbsp_clks", |
| 93 | .ops = &clkops_null, |
| 94 | }; |
| 95 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 96 | /* |
| 97 | * Analog domain root source clocks |
| 98 | */ |
| 99 | |
| 100 | /* dpll_ck, is broken out in to special cases through clksel */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 101 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
| 102 | * deal with this |
| 103 | */ |
| 104 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 105 | static struct dpll_data dpll_dd = { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 106 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 107 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 108 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 109 | .clk_bypass = &sys_ck, |
| 110 | .clk_ref = &sys_ck, |
| 111 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 112 | .enable_mask = OMAP24XX_EN_DPLL_MASK, |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 113 | .max_multiplier = 1023, |
Paul Walmsley | 95f538a | 2009-01-28 12:08:44 -0700 | [diff] [blame] | 114 | .min_divider = 1, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 115 | .max_divider = 16, |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 116 | }; |
| 117 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 118 | /* |
| 119 | * XXX Cannot add round_rate here yet, as this is still a composite clock, |
| 120 | * not just a DPLL |
| 121 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 122 | static struct clk dpll_ck = { |
| 123 | .name = "dpll_ck", |
Paul Walmsley | 0fd0c21 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 124 | .ops = &clkops_omap2xxx_dpll_ops, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 125 | .parent = &sys_ck, /* Can be func_32k also */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 126 | .dpll_data = &dpll_dd, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 127 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 128 | .recalc = &omap2_dpllcore_recalc, |
| 129 | .set_rate = &omap2_reprogram_dpllcore, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | static struct clk apll96_ck = { |
| 133 | .name = "apll96_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 134 | .ops = &clkops_apll96, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 135 | .parent = &sys_ck, |
| 136 | .rate = 96000000, |
Paul Walmsley | 51c1954 | 2010-02-22 22:09:26 -0700 | [diff] [blame] | 137 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 138 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 139 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 140 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | static struct clk apll54_ck = { |
| 144 | .name = "apll54_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 145 | .ops = &clkops_apll54, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 146 | .parent = &sys_ck, |
| 147 | .rate = 54000000, |
Paul Walmsley | 51c1954 | 2010-02-22 22:09:26 -0700 | [diff] [blame] | 148 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 149 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 150 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 151 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | /* |
| 155 | * PRCM digital base sources |
| 156 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 157 | |
| 158 | /* func_54m_ck */ |
| 159 | |
| 160 | static const struct clksel_rate func_54m_apll54_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 161 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 162 | { .div = 0 }, |
| 163 | }; |
| 164 | |
| 165 | static const struct clksel_rate func_54m_alt_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 166 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 167 | { .div = 0 }, |
| 168 | }; |
| 169 | |
| 170 | static const struct clksel func_54m_clksel[] = { |
| 171 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, |
| 172 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, |
| 173 | { .parent = NULL }, |
| 174 | }; |
| 175 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 176 | static struct clk func_54m_ck = { |
| 177 | .name = "func_54m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 178 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 179 | .parent = &apll54_ck, /* can also be alt_clk */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 180 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 181 | .init = &omap2_init_clksel_parent, |
| 182 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
Paul Walmsley | f38ca10 | 2010-05-20 12:31:04 -0600 | [diff] [blame] | 183 | .clksel_mask = OMAP24XX_54M_SOURCE_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 184 | .clksel = func_54m_clksel, |
| 185 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 186 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 187 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 188 | static struct clk core_ck = { |
| 189 | .name = "core_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 190 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 191 | .parent = &dpll_ck, /* can also be 32k */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 192 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 193 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 194 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 195 | |
| 196 | /* func_96m_ck */ |
| 197 | static const struct clksel_rate func_96m_apll96_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 198 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 199 | { .div = 0 }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 200 | }; |
| 201 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 202 | static const struct clksel_rate func_96m_alt_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 203 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 204 | { .div = 0 }, |
| 205 | }; |
| 206 | |
| 207 | static const struct clksel func_96m_clksel[] = { |
| 208 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, |
| 209 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, |
| 210 | { .parent = NULL } |
| 211 | }; |
| 212 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 213 | static struct clk func_96m_ck = { |
| 214 | .name = "func_96m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 215 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 216 | .parent = &apll96_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 217 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 218 | .init = &omap2_init_clksel_parent, |
| 219 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
Paul Walmsley | f38ca10 | 2010-05-20 12:31:04 -0600 | [diff] [blame] | 220 | .clksel_mask = OMAP2430_96M_SOURCE_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 221 | .clksel = func_96m_clksel, |
| 222 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 223 | }; |
| 224 | |
| 225 | /* func_48m_ck */ |
| 226 | |
| 227 | static const struct clksel_rate func_48m_apll96_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 228 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 229 | { .div = 0 }, |
| 230 | }; |
| 231 | |
| 232 | static const struct clksel_rate func_48m_alt_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 233 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 234 | { .div = 0 }, |
| 235 | }; |
| 236 | |
| 237 | static const struct clksel func_48m_clksel[] = { |
| 238 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, |
| 239 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, |
| 240 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | static struct clk func_48m_ck = { |
| 244 | .name = "func_48m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 245 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 246 | .parent = &apll96_ck, /* 96M or Alt */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 247 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 248 | .init = &omap2_init_clksel_parent, |
| 249 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
Paul Walmsley | f38ca10 | 2010-05-20 12:31:04 -0600 | [diff] [blame] | 250 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 251 | .clksel = func_48m_clksel, |
| 252 | .recalc = &omap2_clksel_recalc, |
| 253 | .round_rate = &omap2_clksel_round_rate, |
| 254 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | static struct clk func_12m_ck = { |
| 258 | .name = "func_12m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 259 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 260 | .parent = &func_48m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 261 | .fixed_div = 4, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 262 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 263 | .recalc = &omap_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | /* Secure timer, only available in secure mode */ |
| 267 | static struct clk wdt1_osc_ck = { |
| 268 | .name = "ck_wdt1_osc", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 269 | .ops = &clkops_null, /* RMK: missing? */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 270 | .parent = &osc_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 271 | .recalc = &followparent_recalc, |
| 272 | }; |
| 273 | |
| 274 | /* |
| 275 | * The common_clkout* clksel_rate structs are common to |
| 276 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. |
| 277 | * sys_clkout2_* are 2420-only, so the |
| 278 | * clksel_rate flags fields are inaccurate for those clocks. This is |
| 279 | * harmless since access to those clocks are gated by the struct clk |
| 280 | * flags fields, which mark them as 2420-only. |
| 281 | */ |
| 282 | static const struct clksel_rate common_clkout_src_core_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 283 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 284 | { .div = 0 } |
| 285 | }; |
| 286 | |
| 287 | static const struct clksel_rate common_clkout_src_sys_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 288 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 289 | { .div = 0 } |
| 290 | }; |
| 291 | |
| 292 | static const struct clksel_rate common_clkout_src_96m_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 293 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 294 | { .div = 0 } |
| 295 | }; |
| 296 | |
| 297 | static const struct clksel_rate common_clkout_src_54m_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 298 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 299 | { .div = 0 } |
| 300 | }; |
| 301 | |
| 302 | static const struct clksel common_clkout_src_clksel[] = { |
| 303 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, |
| 304 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, |
| 305 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, |
| 306 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, |
| 307 | { .parent = NULL } |
| 308 | }; |
| 309 | |
| 310 | static struct clk sys_clkout_src = { |
| 311 | .name = "sys_clkout_src", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 312 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 313 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 314 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 315 | .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 316 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| 317 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 318 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 319 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
| 320 | .clksel = common_clkout_src_clksel, |
| 321 | .recalc = &omap2_clksel_recalc, |
| 322 | .round_rate = &omap2_clksel_round_rate, |
| 323 | .set_rate = &omap2_clksel_set_rate |
| 324 | }; |
| 325 | |
| 326 | static const struct clksel_rate common_clkout_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 327 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 328 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
| 329 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, |
| 330 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, |
| 331 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, |
| 332 | { .div = 0 }, |
| 333 | }; |
| 334 | |
| 335 | static const struct clksel sys_clkout_clksel[] = { |
| 336 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, |
| 337 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 338 | }; |
| 339 | |
| 340 | static struct clk sys_clkout = { |
| 341 | .name = "sys_clkout", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 342 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 343 | .parent = &sys_clkout_src, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 344 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 345 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 346 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| 347 | .clksel = sys_clkout_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 348 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 349 | .round_rate = &omap2_clksel_round_rate, |
| 350 | .set_rate = &omap2_clksel_set_rate |
| 351 | }; |
| 352 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 353 | static struct clk emul_ck = { |
| 354 | .name = "emul_ck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 355 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 356 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 357 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 358 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 359 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| 360 | .recalc = &followparent_recalc, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 361 | |
| 362 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 363 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 364 | /* |
| 365 | * MPU clock domain |
| 366 | * Clocks: |
| 367 | * MPU_FCLK, MPU_ICLK |
| 368 | * INT_M_FCLK, INT_M_I_CLK |
| 369 | * |
| 370 | * - Individual clocks are hardware managed. |
| 371 | * - Base divider comes from: CM_CLKSEL_MPU |
| 372 | * |
| 373 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 374 | static const struct clksel_rate mpu_core_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 375 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 376 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 377 | { .div = 0 }, |
| 378 | }; |
| 379 | |
| 380 | static const struct clksel mpu_clksel[] = { |
| 381 | { .parent = &core_ck, .rates = mpu_core_rates }, |
| 382 | { .parent = NULL } |
| 383 | }; |
| 384 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 385 | static struct clk mpu_ck = { /* Control cpu */ |
| 386 | .name = "mpu_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 387 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 388 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 389 | .clkdm_name = "mpu_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 390 | .init = &omap2_init_clksel_parent, |
| 391 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| 392 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 393 | .clksel = mpu_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 394 | .recalc = &omap2_clksel_recalc, |
| 395 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 396 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 397 | /* |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 398 | * DSP (2430-IVA2.1) clock domain |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 399 | * Clocks: |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 400 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 401 | * |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 402 | * Won't be too specific here. The core clock comes into this block |
| 403 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| 404 | * controls. The other branch gets further divided by 2 then possibly |
| 405 | * routed into a synchronizer and out of clocks abc. |
| 406 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 407 | static const struct clksel_rate dsp_fck_core_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 408 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 409 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 410 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 411 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 412 | { .div = 0 }, |
| 413 | }; |
| 414 | |
| 415 | static const struct clksel dsp_fck_clksel[] = { |
| 416 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, |
| 417 | { .parent = NULL } |
| 418 | }; |
| 419 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 420 | static struct clk dsp_fck = { |
| 421 | .name = "dsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 422 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 423 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 424 | .clkdm_name = "dsp_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 425 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 426 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 427 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 428 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
| 429 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 430 | .recalc = &omap2_clksel_recalc, |
| 431 | }; |
| 432 | |
Paul Walmsley | 2241139 | 2011-02-25 15:52:04 -0700 | [diff] [blame] | 433 | static const struct clksel dsp_ick_clksel[] = { |
| 434 | { .parent = &dsp_fck, .rates = dsp_ick_rates }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 435 | { .parent = NULL } |
| 436 | }; |
| 437 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 438 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
| 439 | static struct clk iva2_1_ick = { |
| 440 | .name = "iva2_1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 441 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 2241139 | 2011-02-25 15:52:04 -0700 | [diff] [blame] | 442 | .parent = &dsp_fck, |
| 443 | .clkdm_name = "dsp_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 444 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 445 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
Paul Walmsley | 2241139 | 2011-02-25 15:52:04 -0700 | [diff] [blame] | 446 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 447 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 448 | .clksel = dsp_ick_clksel, |
| 449 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 450 | }; |
| 451 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 452 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 453 | * L3 clock domain |
| 454 | * L3 clocks are used for both interface and functional clocks to |
| 455 | * multiple entities. Some of these clocks are completely managed |
| 456 | * by hardware, and some others allow software control. Hardware |
| 457 | * managed ones general are based on directly CLK_REQ signals and |
| 458 | * various auto idle settings. The functional spec sets many of these |
| 459 | * as 'tie-high' for their enables. |
| 460 | * |
| 461 | * I-CLOCKS: |
| 462 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA |
| 463 | * CAM, HS-USB. |
| 464 | * F-CLOCK |
| 465 | * SSI. |
| 466 | * |
| 467 | * GPMC memories and SDRC have timing and clock sensitive registers which |
| 468 | * may very well need notification when the clock changes. Currently for low |
| 469 | * operating points, these are taken care of in sleep.S. |
| 470 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 471 | static const struct clksel_rate core_l3_core_rates[] = { |
| 472 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 473 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 474 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 475 | { .div = 0 } |
| 476 | }; |
| 477 | |
| 478 | static const struct clksel core_l3_clksel[] = { |
| 479 | { .parent = &core_ck, .rates = core_l3_core_rates }, |
| 480 | { .parent = NULL } |
| 481 | }; |
| 482 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 483 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 484 | .name = "core_l3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 485 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 486 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 487 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 488 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 489 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| 490 | .clksel = core_l3_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 491 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 492 | }; |
| 493 | |
| 494 | /* usb_l4_ick */ |
| 495 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { |
| 496 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 497 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 498 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 499 | { .div = 0 } |
| 500 | }; |
| 501 | |
| 502 | static const struct clksel usb_l4_ick_clksel[] = { |
| 503 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, |
| 504 | { .parent = NULL }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 505 | }; |
| 506 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 507 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 508 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 509 | .name = "usb_l4_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 510 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 511 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 512 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 514 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 515 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 516 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
| 517 | .clksel = usb_l4_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 518 | .recalc = &omap2_clksel_recalc, |
| 519 | }; |
| 520 | |
| 521 | /* |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 522 | * L4 clock management domain |
| 523 | * |
| 524 | * This domain contains lots of interface clocks from the L4 interface, some |
| 525 | * functional clocks. Fixed APLL functional source clocks are managed in |
| 526 | * this domain. |
| 527 | */ |
| 528 | static const struct clksel_rate l4_core_l3_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 529 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 530 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 531 | { .div = 0 } |
| 532 | }; |
| 533 | |
| 534 | static const struct clksel l4_clksel[] = { |
| 535 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, |
| 536 | { .parent = NULL } |
| 537 | }; |
| 538 | |
| 539 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 540 | .name = "l4_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 541 | .ops = &clkops_null, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 542 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 543 | .clkdm_name = "core_l4_clkdm", |
| 544 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 545 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| 546 | .clksel = l4_clksel, |
| 547 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 548 | }; |
| 549 | |
| 550 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 551 | * SSI is in L3 management domain, its direct parent is core not l3, |
| 552 | * many core power domain entities are grouped into the L3 clock |
| 553 | * domain. |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 554 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 555 | * |
| 556 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
| 557 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 558 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
| 559 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 560 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 561 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 562 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 563 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 564 | { .div = 0 } |
| 565 | }; |
| 566 | |
| 567 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { |
| 568 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, |
| 569 | { .parent = NULL } |
| 570 | }; |
| 571 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 572 | static struct clk ssi_ssr_sst_fck = { |
| 573 | .name = "ssi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 574 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 575 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 576 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 578 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 579 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 580 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
| 581 | .clksel = ssi_ssr_sst_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 582 | .recalc = &omap2_clksel_recalc, |
| 583 | }; |
| 584 | |
Paul Walmsley | 9299fd8 | 2009-01-27 19:12:54 -0700 | [diff] [blame] | 585 | /* |
| 586 | * Presumably this is the same as SSI_ICLK. |
| 587 | * TRM contradicts itself on what clockdomain SSI_ICLK is in |
| 588 | */ |
| 589 | static struct clk ssi_l4_ick = { |
| 590 | .name = "ssi_l4_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 591 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 9299fd8 | 2009-01-27 19:12:54 -0700 | [diff] [blame] | 592 | .parent = &l4_ck, |
| 593 | .clkdm_name = "core_l4_clkdm", |
| 594 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 595 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 596 | .recalc = &followparent_recalc, |
| 597 | }; |
| 598 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 599 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 600 | /* |
| 601 | * GFX clock domain |
| 602 | * Clocks: |
| 603 | * GFX_FCLK, GFX_ICLK |
| 604 | * GFX_CG1(2d), GFX_CG2(3d) |
| 605 | * |
| 606 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) |
| 607 | * The 2d and 3d clocks run at a hardware determined |
| 608 | * divided value of fclk. |
| 609 | * |
| 610 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 611 | |
| 612 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
| 613 | static const struct clksel gfx_fck_clksel[] = { |
| 614 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, |
| 615 | { .parent = NULL }, |
| 616 | }; |
| 617 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 618 | static struct clk gfx_3d_fck = { |
| 619 | .name = "gfx_3d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 620 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 621 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 622 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 623 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 624 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| 625 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 626 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 627 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 628 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 629 | .round_rate = &omap2_clksel_round_rate, |
| 630 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 631 | }; |
| 632 | |
| 633 | static struct clk gfx_2d_fck = { |
| 634 | .name = "gfx_2d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 635 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 636 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 637 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 638 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 639 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| 640 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 641 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 642 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 643 | .recalc = &omap2_clksel_recalc, |
| 644 | }; |
| 645 | |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 646 | /* This interface clock does not have a CM_AUTOIDLE bit */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 647 | static struct clk gfx_ick = { |
| 648 | .name = "gfx_ick", /* From l3 */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 649 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 650 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 651 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 652 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 653 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 654 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 655 | }; |
| 656 | |
| 657 | /* |
| 658 | * Modem clock domain (2430) |
| 659 | * CLOCKS: |
| 660 | * MDM_OSC_CLK |
| 661 | * MDM_ICLK |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 662 | * These clocks are usable in chassis mode only. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 663 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 664 | static const struct clksel_rate mdm_ick_core_rates[] = { |
| 665 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 666 | { .div = 4, .val = 4, .flags = RATE_IN_243X }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 667 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, |
| 668 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, |
| 669 | { .div = 0 } |
| 670 | }; |
| 671 | |
| 672 | static const struct clksel mdm_ick_clksel[] = { |
| 673 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, |
| 674 | { .parent = NULL } |
| 675 | }; |
| 676 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 677 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
| 678 | .name = "mdm_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 679 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 680 | .parent = &core_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 681 | .clkdm_name = "mdm_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 682 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
| 683 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
| 684 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), |
| 685 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, |
| 686 | .clksel = mdm_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 687 | .recalc = &omap2_clksel_recalc, |
| 688 | }; |
| 689 | |
| 690 | static struct clk mdm_osc_ck = { |
| 691 | .name = "mdm_osc_ck", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 692 | .ops = &clkops_omap2_mdmclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 693 | .parent = &osc_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 694 | .clkdm_name = "mdm_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 695 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
| 696 | .enable_bit = OMAP2430_EN_OSC_SHIFT, |
| 697 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 698 | }; |
| 699 | |
| 700 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 701 | * DSS clock domain |
| 702 | * CLOCKs: |
| 703 | * DSS_L4_ICLK, DSS_L3_ICLK, |
| 704 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK |
| 705 | * |
| 706 | * DSS is both initiator and target. |
| 707 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 708 | /* XXX Add RATE_NOT_VALIDATED */ |
| 709 | |
| 710 | static const struct clksel_rate dss1_fck_sys_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 711 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 712 | { .div = 0 } |
| 713 | }; |
| 714 | |
| 715 | static const struct clksel_rate dss1_fck_core_rates[] = { |
| 716 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 717 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 718 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 719 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 720 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, |
| 721 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 722 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, |
| 723 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, |
| 724 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 725 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 726 | { .div = 0 } |
| 727 | }; |
| 728 | |
| 729 | static const struct clksel dss1_fck_clksel[] = { |
| 730 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, |
| 731 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, |
| 732 | { .parent = NULL }, |
| 733 | }; |
| 734 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 735 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 736 | .name = "dss_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 737 | .ops = &clkops_omap2_iclk_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 738 | .parent = &l4_ck, /* really both l3 and l4 */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 739 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 740 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 741 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 742 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 743 | }; |
| 744 | |
| 745 | static struct clk dss1_fck = { |
| 746 | .name = "dss1_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 747 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 748 | .parent = &core_ck, /* Core or sys */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 749 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 750 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 751 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 752 | .init = &omap2_init_clksel_parent, |
| 753 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 754 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
| 755 | .clksel = dss1_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 756 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 757 | }; |
| 758 | |
| 759 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 760 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 761 | { .div = 0 } |
| 762 | }; |
| 763 | |
| 764 | static const struct clksel_rate dss2_fck_48m_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 765 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 766 | { .div = 0 } |
| 767 | }; |
| 768 | |
| 769 | static const struct clksel dss2_fck_clksel[] = { |
| 770 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, |
| 771 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, |
| 772 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 773 | }; |
| 774 | |
| 775 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 776 | .name = "dss2_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 777 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 778 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 779 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 780 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 781 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| 782 | .init = &omap2_init_clksel_parent, |
| 783 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 784 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 785 | .clksel = dss2_fck_clksel, |
Paul Walmsley | d4521f6 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 786 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 787 | }; |
| 788 | |
| 789 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 790 | .name = "dss_54m_fck", /* 54m tv clk */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 791 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 792 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 793 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 794 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 795 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| 796 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 797 | }; |
| 798 | |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 799 | static struct clk wu_l4_ick = { |
| 800 | .name = "wu_l4_ick", |
| 801 | .ops = &clkops_null, |
| 802 | .parent = &sys_ck, |
| 803 | .clkdm_name = "wkup_clkdm", |
| 804 | .recalc = &followparent_recalc, |
| 805 | }; |
| 806 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 807 | /* |
| 808 | * CORE power domain ICLK & FCLK defines. |
| 809 | * Many of the these can have more than one possible parent. Entries |
| 810 | * here will likely have an L4 interface parent, and may have multiple |
| 811 | * functional clock parents. |
| 812 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 813 | static const struct clksel_rate gpt_alt_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 814 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 815 | { .div = 0 } |
| 816 | }; |
| 817 | |
| 818 | static const struct clksel omap24xx_gpt_clksel[] = { |
| 819 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, |
| 820 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 821 | { .parent = &alt_ck, .rates = gpt_alt_rates }, |
| 822 | { .parent = NULL }, |
| 823 | }; |
| 824 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 825 | static struct clk gpt1_ick = { |
| 826 | .name = "gpt1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 827 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 828 | .parent = &wu_l4_ick, |
| 829 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 830 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 831 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 832 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 833 | }; |
| 834 | |
| 835 | static struct clk gpt1_fck = { |
| 836 | .name = "gpt1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 837 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 838 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 839 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 840 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 841 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 842 | .init = &omap2_init_clksel_parent, |
| 843 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), |
| 844 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, |
| 845 | .clksel = omap24xx_gpt_clksel, |
| 846 | .recalc = &omap2_clksel_recalc, |
| 847 | .round_rate = &omap2_clksel_round_rate, |
| 848 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 849 | }; |
| 850 | |
| 851 | static struct clk gpt2_ick = { |
| 852 | .name = "gpt2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 853 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 854 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 855 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 856 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 857 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 858 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 859 | }; |
| 860 | |
| 861 | static struct clk gpt2_fck = { |
| 862 | .name = "gpt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 863 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 864 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 865 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 866 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 867 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 868 | .init = &omap2_init_clksel_parent, |
| 869 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 870 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, |
| 871 | .clksel = omap24xx_gpt_clksel, |
| 872 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 873 | }; |
| 874 | |
| 875 | static struct clk gpt3_ick = { |
| 876 | .name = "gpt3_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 877 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 878 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 879 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 881 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 882 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 883 | }; |
| 884 | |
| 885 | static struct clk gpt3_fck = { |
| 886 | .name = "gpt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 887 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 888 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 889 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 890 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 891 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 892 | .init = &omap2_init_clksel_parent, |
| 893 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 894 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, |
| 895 | .clksel = omap24xx_gpt_clksel, |
| 896 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 897 | }; |
| 898 | |
| 899 | static struct clk gpt4_ick = { |
| 900 | .name = "gpt4_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 901 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 902 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 903 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 905 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 906 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 907 | }; |
| 908 | |
| 909 | static struct clk gpt4_fck = { |
| 910 | .name = "gpt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 911 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 912 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 913 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 914 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 915 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 916 | .init = &omap2_init_clksel_parent, |
| 917 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 918 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, |
| 919 | .clksel = omap24xx_gpt_clksel, |
| 920 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 921 | }; |
| 922 | |
| 923 | static struct clk gpt5_ick = { |
| 924 | .name = "gpt5_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 925 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 926 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 927 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 928 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 929 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 930 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 931 | }; |
| 932 | |
| 933 | static struct clk gpt5_fck = { |
| 934 | .name = "gpt5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 935 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 936 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 937 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 938 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 939 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 940 | .init = &omap2_init_clksel_parent, |
| 941 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 942 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, |
| 943 | .clksel = omap24xx_gpt_clksel, |
| 944 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 945 | }; |
| 946 | |
| 947 | static struct clk gpt6_ick = { |
| 948 | .name = "gpt6_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 949 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 950 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 951 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 953 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 954 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 955 | }; |
| 956 | |
| 957 | static struct clk gpt6_fck = { |
| 958 | .name = "gpt6_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 959 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 960 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 961 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 963 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 964 | .init = &omap2_init_clksel_parent, |
| 965 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 966 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, |
| 967 | .clksel = omap24xx_gpt_clksel, |
| 968 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 969 | }; |
| 970 | |
| 971 | static struct clk gpt7_ick = { |
| 972 | .name = "gpt7_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 973 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 974 | .parent = &l4_ck, |
Paul Walmsley | a4fc927 | 2011-02-25 14:53:40 -0700 | [diff] [blame] | 975 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 977 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 978 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 979 | }; |
| 980 | |
| 981 | static struct clk gpt7_fck = { |
| 982 | .name = "gpt7_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 983 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 984 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 985 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 986 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 987 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 988 | .init = &omap2_init_clksel_parent, |
| 989 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 990 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, |
| 991 | .clksel = omap24xx_gpt_clksel, |
| 992 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 993 | }; |
| 994 | |
| 995 | static struct clk gpt8_ick = { |
| 996 | .name = "gpt8_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 997 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 998 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 999 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1000 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1001 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1002 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1003 | }; |
| 1004 | |
| 1005 | static struct clk gpt8_fck = { |
| 1006 | .name = "gpt8_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1007 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1008 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1009 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1010 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1011 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1012 | .init = &omap2_init_clksel_parent, |
| 1013 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1014 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, |
| 1015 | .clksel = omap24xx_gpt_clksel, |
| 1016 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1017 | }; |
| 1018 | |
| 1019 | static struct clk gpt9_ick = { |
| 1020 | .name = "gpt9_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1021 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1022 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1023 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1024 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1025 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1026 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1027 | }; |
| 1028 | |
| 1029 | static struct clk gpt9_fck = { |
| 1030 | .name = "gpt9_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1031 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1032 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1033 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1034 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1035 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1036 | .init = &omap2_init_clksel_parent, |
| 1037 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1038 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, |
| 1039 | .clksel = omap24xx_gpt_clksel, |
| 1040 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1041 | }; |
| 1042 | |
| 1043 | static struct clk gpt10_ick = { |
| 1044 | .name = "gpt10_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1045 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1046 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1047 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1048 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1049 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1050 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1051 | }; |
| 1052 | |
| 1053 | static struct clk gpt10_fck = { |
| 1054 | .name = "gpt10_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1055 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1056 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1057 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1058 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1059 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1060 | .init = &omap2_init_clksel_parent, |
| 1061 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1062 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, |
| 1063 | .clksel = omap24xx_gpt_clksel, |
| 1064 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1065 | }; |
| 1066 | |
| 1067 | static struct clk gpt11_ick = { |
| 1068 | .name = "gpt11_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1069 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1070 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1071 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1072 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1073 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1074 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1075 | }; |
| 1076 | |
| 1077 | static struct clk gpt11_fck = { |
| 1078 | .name = "gpt11_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1079 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1080 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1081 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1082 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1083 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1084 | .init = &omap2_init_clksel_parent, |
| 1085 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1086 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, |
| 1087 | .clksel = omap24xx_gpt_clksel, |
| 1088 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1089 | }; |
| 1090 | |
| 1091 | static struct clk gpt12_ick = { |
| 1092 | .name = "gpt12_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1093 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1094 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1095 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1096 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1097 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1098 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1099 | }; |
| 1100 | |
| 1101 | static struct clk gpt12_fck = { |
| 1102 | .name = "gpt12_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1103 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 1104 | .parent = &secure_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1105 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1106 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1107 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1108 | .init = &omap2_init_clksel_parent, |
| 1109 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1110 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, |
| 1111 | .clksel = omap24xx_gpt_clksel, |
| 1112 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1113 | }; |
| 1114 | |
| 1115 | static struct clk mcbsp1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1116 | .name = "mcbsp1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1117 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1118 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1119 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1120 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1121 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1122 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1123 | }; |
| 1124 | |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1125 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
| 1126 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
| 1127 | { .div = 0 } |
| 1128 | }; |
| 1129 | |
| 1130 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
| 1131 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 1132 | { .div = 0 } |
| 1133 | }; |
| 1134 | |
| 1135 | static const struct clksel mcbsp_fck_clksel[] = { |
| 1136 | { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, |
| 1137 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 1138 | { .parent = NULL } |
| 1139 | }; |
| 1140 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1141 | static struct clk mcbsp1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1142 | .name = "mcbsp1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1143 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1144 | .parent = &func_96m_ck, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1145 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1146 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1147 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1148 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1149 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1150 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1151 | .clksel = mcbsp_fck_clksel, |
| 1152 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1153 | }; |
| 1154 | |
| 1155 | static struct clk mcbsp2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1156 | .name = "mcbsp2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1157 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1158 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1159 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1160 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1161 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1162 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1163 | }; |
| 1164 | |
| 1165 | static struct clk mcbsp2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1166 | .name = "mcbsp2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1167 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1168 | .parent = &func_96m_ck, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1169 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1170 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1171 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1172 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1173 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1174 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 1175 | .clksel = mcbsp_fck_clksel, |
| 1176 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1177 | }; |
| 1178 | |
| 1179 | static struct clk mcbsp3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1180 | .name = "mcbsp3_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1181 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1182 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1183 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1184 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1185 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| 1186 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1187 | }; |
| 1188 | |
| 1189 | static struct clk mcbsp3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1190 | .name = "mcbsp3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1191 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1192 | .parent = &func_96m_ck, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1193 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1194 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1195 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1196 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1197 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
| 1198 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 1199 | .clksel = mcbsp_fck_clksel, |
| 1200 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1201 | }; |
| 1202 | |
| 1203 | static struct clk mcbsp4_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1204 | .name = "mcbsp4_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1205 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1206 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1207 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1208 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1209 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| 1210 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1211 | }; |
| 1212 | |
| 1213 | static struct clk mcbsp4_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1214 | .name = "mcbsp4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1215 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1216 | .parent = &func_96m_ck, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1217 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1218 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1219 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1220 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1221 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
| 1222 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 1223 | .clksel = mcbsp_fck_clksel, |
| 1224 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1225 | }; |
| 1226 | |
| 1227 | static struct clk mcbsp5_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1228 | .name = "mcbsp5_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1229 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1230 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1231 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1232 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1233 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| 1234 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1235 | }; |
| 1236 | |
| 1237 | static struct clk mcbsp5_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1238 | .name = "mcbsp5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1239 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1240 | .parent = &func_96m_ck, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1241 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1242 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1244 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1245 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
| 1246 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1247 | .clksel = mcbsp_fck_clksel, |
| 1248 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1249 | }; |
| 1250 | |
| 1251 | static struct clk mcspi1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1252 | .name = "mcspi1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1253 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1254 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1255 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1257 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1258 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1259 | }; |
| 1260 | |
| 1261 | static struct clk mcspi1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1262 | .name = "mcspi1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1263 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1264 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1265 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1266 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1267 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1268 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1269 | }; |
| 1270 | |
| 1271 | static struct clk mcspi2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1272 | .name = "mcspi2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1273 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1274 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1275 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1276 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1277 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1278 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1279 | }; |
| 1280 | |
| 1281 | static struct clk mcspi2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1282 | .name = "mcspi2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1283 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1284 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1285 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1286 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1287 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1288 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1289 | }; |
| 1290 | |
| 1291 | static struct clk mcspi3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1292 | .name = "mcspi3_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1293 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1294 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1295 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1297 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| 1298 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1299 | }; |
| 1300 | |
| 1301 | static struct clk mcspi3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1302 | .name = "mcspi3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1303 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1304 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1305 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1306 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1307 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| 1308 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1309 | }; |
| 1310 | |
| 1311 | static struct clk uart1_ick = { |
| 1312 | .name = "uart1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1313 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1314 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1315 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1317 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1318 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1319 | }; |
| 1320 | |
| 1321 | static struct clk uart1_fck = { |
| 1322 | .name = "uart1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1323 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1324 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1325 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1326 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1327 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1328 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1329 | }; |
| 1330 | |
| 1331 | static struct clk uart2_ick = { |
| 1332 | .name = "uart2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1333 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1334 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1335 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1336 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1337 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1338 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1339 | }; |
| 1340 | |
| 1341 | static struct clk uart2_fck = { |
| 1342 | .name = "uart2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1343 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1344 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1345 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1346 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1347 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1348 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1349 | }; |
| 1350 | |
| 1351 | static struct clk uart3_ick = { |
| 1352 | .name = "uart3_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1353 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1354 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1355 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1356 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1357 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1358 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1359 | }; |
| 1360 | |
| 1361 | static struct clk uart3_fck = { |
| 1362 | .name = "uart3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1363 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1364 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1365 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1366 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1367 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1368 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1369 | }; |
| 1370 | |
| 1371 | static struct clk gpios_ick = { |
| 1372 | .name = "gpios_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1373 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1374 | .parent = &wu_l4_ick, |
| 1375 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1376 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1377 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1378 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1379 | }; |
| 1380 | |
| 1381 | static struct clk gpios_fck = { |
| 1382 | .name = "gpios_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1383 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1384 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1385 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1386 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1387 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1388 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1389 | }; |
| 1390 | |
| 1391 | static struct clk mpu_wdt_ick = { |
| 1392 | .name = "mpu_wdt_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1393 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1394 | .parent = &wu_l4_ick, |
| 1395 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1396 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1397 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1398 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1399 | }; |
| 1400 | |
| 1401 | static struct clk mpu_wdt_fck = { |
| 1402 | .name = "mpu_wdt_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1403 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1404 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1405 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1406 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1407 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1408 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1409 | }; |
| 1410 | |
| 1411 | static struct clk sync_32k_ick = { |
| 1412 | .name = "sync_32k_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1413 | .ops = &clkops_omap2_iclk_dflt_wait, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1414 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1415 | .parent = &wu_l4_ick, |
| 1416 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1417 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1418 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| 1419 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1420 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1421 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1422 | static struct clk wdt1_ick = { |
| 1423 | .name = "wdt1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1424 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1425 | .parent = &wu_l4_ick, |
| 1426 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1427 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1428 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| 1429 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1430 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1431 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1432 | static struct clk omapctrl_ick = { |
| 1433 | .name = "omapctrl_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1434 | .ops = &clkops_omap2_iclk_dflt_wait, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1435 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1436 | .parent = &wu_l4_ick, |
| 1437 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1438 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1439 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| 1440 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1441 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1442 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1443 | static struct clk icr_ick = { |
| 1444 | .name = "icr_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1445 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1446 | .parent = &wu_l4_ick, |
| 1447 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1448 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1449 | .enable_bit = OMAP2430_EN_ICR_SHIFT, |
| 1450 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1451 | }; |
| 1452 | |
| 1453 | static struct clk cam_ick = { |
| 1454 | .name = "cam_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1455 | .ops = &clkops_omap2_iclk_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1456 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1457 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1458 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1459 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1460 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1461 | }; |
| 1462 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1463 | /* |
| 1464 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be |
| 1465 | * split into two separate clocks, since the parent clocks are different |
| 1466 | * and the clockdomains are also different. |
| 1467 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1468 | static struct clk cam_fck = { |
| 1469 | .name = "cam_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1470 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1471 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1472 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1473 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1474 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1475 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1476 | }; |
| 1477 | |
| 1478 | static struct clk mailboxes_ick = { |
| 1479 | .name = "mailboxes_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1480 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1481 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1482 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1483 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1484 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 1485 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1486 | }; |
| 1487 | |
| 1488 | static struct clk wdt4_ick = { |
| 1489 | .name = "wdt4_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1490 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1491 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1492 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1493 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1494 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1495 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1496 | }; |
| 1497 | |
| 1498 | static struct clk wdt4_fck = { |
| 1499 | .name = "wdt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1500 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1501 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1502 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1503 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1504 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1505 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1506 | }; |
| 1507 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1508 | static struct clk mspro_ick = { |
| 1509 | .name = "mspro_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1510 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1511 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1512 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1514 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1515 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1516 | }; |
| 1517 | |
| 1518 | static struct clk mspro_fck = { |
| 1519 | .name = "mspro_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1520 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1521 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1522 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1523 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1524 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1525 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1526 | }; |
| 1527 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1528 | static struct clk fac_ick = { |
| 1529 | .name = "fac_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1530 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1531 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1532 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1533 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1534 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1535 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1536 | }; |
| 1537 | |
| 1538 | static struct clk fac_fck = { |
| 1539 | .name = "fac_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1540 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1541 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1542 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1543 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1544 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1545 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1546 | }; |
| 1547 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1548 | static struct clk hdq_ick = { |
| 1549 | .name = "hdq_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1550 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1551 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1552 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1553 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1554 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1555 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1556 | }; |
| 1557 | |
| 1558 | static struct clk hdq_fck = { |
| 1559 | .name = "hdq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1560 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1561 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1562 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1563 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1564 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1565 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1566 | }; |
| 1567 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1568 | /* |
| 1569 | * XXX This is marked as a 2420-only define, but it claims to be present |
| 1570 | * on 2430 also. Double-check. |
| 1571 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1572 | static struct clk i2c2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1573 | .name = "i2c2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1574 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1575 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1576 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1578 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1579 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1580 | }; |
| 1581 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1582 | static struct clk i2chs2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1583 | .name = "i2chs2_fck", |
Paul Walmsley | 3dc2197 | 2009-07-24 19:44:04 -0600 | [diff] [blame] | 1584 | .ops = &clkops_omap2430_i2chs_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1585 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1586 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1587 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1588 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, |
| 1589 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1590 | }; |
| 1591 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1592 | /* |
| 1593 | * XXX This is marked as a 2420-only define, but it claims to be present |
| 1594 | * on 2430 also. Double-check. |
| 1595 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1596 | static struct clk i2c1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1597 | .name = "i2c1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1598 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1599 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1600 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1601 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1602 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1603 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1604 | }; |
| 1605 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1606 | static struct clk i2chs1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1607 | .name = "i2chs1_fck", |
Paul Walmsley | 3dc2197 | 2009-07-24 19:44:04 -0600 | [diff] [blame] | 1608 | .ops = &clkops_omap2430_i2chs_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1609 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1610 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1611 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1612 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, |
| 1613 | .recalc = &followparent_recalc, |
| 1614 | }; |
| 1615 | |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1616 | /* |
| 1617 | * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE |
| 1618 | * accesses derived from this data. |
| 1619 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1620 | static struct clk gpmc_fck = { |
| 1621 | .name = "gpmc_fck", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1622 | .ops = &clkops_omap2_iclk_idle_only, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1623 | .parent = &core_l3_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1624 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1625 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1626 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1627 | .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1628 | .recalc = &followparent_recalc, |
| 1629 | }; |
| 1630 | |
| 1631 | static struct clk sdma_fck = { |
| 1632 | .name = "sdma_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1633 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1634 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1635 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1636 | .recalc = &followparent_recalc, |
| 1637 | }; |
| 1638 | |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1639 | /* |
| 1640 | * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE |
| 1641 | * accesses derived from this data. |
| 1642 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1643 | static struct clk sdma_ick = { |
| 1644 | .name = "sdma_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1645 | .ops = &clkops_omap2_iclk_idle_only, |
Paul Walmsley | a1fed57 | 2011-02-25 15:51:02 -0700 | [diff] [blame] | 1646 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1647 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1648 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1649 | .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1650 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1651 | }; |
| 1652 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1653 | static struct clk sdrc_ick = { |
| 1654 | .name = "sdrc_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1655 | .ops = &clkops_omap2_iclk_idle_only, |
Paul Walmsley | a1fed57 | 2011-02-25 15:51:02 -0700 | [diff] [blame] | 1656 | .parent = &core_l3_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1657 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | a1fed57 | 2011-02-25 15:51:02 -0700 | [diff] [blame] | 1658 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1660 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, |
| 1661 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1662 | }; |
| 1663 | |
| 1664 | static struct clk des_ick = { |
| 1665 | .name = "des_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1666 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1667 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1668 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1669 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1670 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| 1671 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1672 | }; |
| 1673 | |
| 1674 | static struct clk sha_ick = { |
| 1675 | .name = "sha_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1676 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1677 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1678 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1679 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1680 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| 1681 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1682 | }; |
| 1683 | |
| 1684 | static struct clk rng_ick = { |
| 1685 | .name = "rng_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1686 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1687 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1688 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1689 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1690 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| 1691 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1692 | }; |
| 1693 | |
| 1694 | static struct clk aes_ick = { |
| 1695 | .name = "aes_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1696 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1697 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1698 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1699 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1700 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| 1701 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1702 | }; |
| 1703 | |
| 1704 | static struct clk pka_ick = { |
| 1705 | .name = "pka_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1706 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1707 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1708 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1709 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1710 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| 1711 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1712 | }; |
| 1713 | |
| 1714 | static struct clk usb_fck = { |
| 1715 | .name = "usb_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1716 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1717 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1718 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1719 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1720 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 1721 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1722 | }; |
| 1723 | |
| 1724 | static struct clk usbhs_ick = { |
| 1725 | .name = "usbhs_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1726 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1727 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1728 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1729 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1730 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, |
| 1731 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1732 | }; |
| 1733 | |
| 1734 | static struct clk mmchs1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1735 | .name = "mmchs1_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1736 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1737 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1738 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1739 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1740 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| 1741 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1742 | }; |
| 1743 | |
| 1744 | static struct clk mmchs1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1745 | .name = "mmchs1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1746 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1747 | .parent = &func_96m_ck, |
Paul Walmsley | a4fc927 | 2011-02-25 14:53:40 -0700 | [diff] [blame] | 1748 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1749 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1750 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| 1751 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1752 | }; |
| 1753 | |
| 1754 | static struct clk mmchs2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1755 | .name = "mmchs2_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1756 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1757 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1758 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1759 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1760 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 1761 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1762 | }; |
| 1763 | |
| 1764 | static struct clk mmchs2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1765 | .name = "mmchs2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1766 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1767 | .parent = &func_96m_ck, |
Paul Walmsley | a4fc927 | 2011-02-25 14:53:40 -0700 | [diff] [blame] | 1768 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1769 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1770 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 1771 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1772 | }; |
| 1773 | |
| 1774 | static struct clk gpio5_ick = { |
| 1775 | .name = "gpio5_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1776 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1777 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1778 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1779 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1780 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| 1781 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1782 | }; |
| 1783 | |
| 1784 | static struct clk gpio5_fck = { |
| 1785 | .name = "gpio5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1786 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1787 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1788 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1790 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| 1791 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1792 | }; |
| 1793 | |
| 1794 | static struct clk mdm_intc_ick = { |
| 1795 | .name = "mdm_intc_ick", |
Paul Walmsley | a1d5562 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1796 | .ops = &clkops_omap2_iclk_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1797 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1798 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1799 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1800 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, |
| 1801 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1802 | }; |
| 1803 | |
| 1804 | static struct clk mmchsdb1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1805 | .name = "mmchsdb1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1806 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1807 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1808 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1809 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1810 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, |
| 1811 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1812 | }; |
| 1813 | |
| 1814 | static struct clk mmchsdb2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1815 | .name = "mmchsdb2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1816 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1817 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1818 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1820 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, |
| 1821 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1822 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1823 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1824 | /* |
| 1825 | * This clock is a composite clock which does entire set changes then |
| 1826 | * forces a rebalance. It keys on the MPU speed, but it really could |
| 1827 | * be any key speed part of a set in the rate table. |
| 1828 | * |
| 1829 | * to really change a set, you need memory table sets which get changed |
| 1830 | * in sram, pre-notifiers & post notifiers, changing the top set, without |
| 1831 | * having low level display recalc's won't work... this is why dpm notifiers |
| 1832 | * work, isr's off, walk a list of clocks already _off_ and not messing with |
| 1833 | * the bus. |
| 1834 | * |
| 1835 | * This clock should have no parent. It embodies the entire upper level |
| 1836 | * active set. A parent will mess up some of the init also. |
| 1837 | */ |
| 1838 | static struct clk virt_prcm_set = { |
| 1839 | .name = "virt_prcm_set", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1840 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1841 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1842 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1843 | .set_rate = &omap2_select_table_rate, |
| 1844 | .round_rate = &omap2_round_to_table_rate, |
| 1845 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1846 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1847 | |
| 1848 | /* |
| 1849 | * clkdev integration |
| 1850 | */ |
| 1851 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1852 | static struct omap_clk omap2430_clks[] = { |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1853 | /* external root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1854 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), |
| 1855 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), |
| 1856 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), |
Tony Lindgren | defa6be | 2012-09-17 16:26:10 -0700 | [diff] [blame] | 1857 | CLK("twl", "fck", &osc_ck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1858 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), |
| 1859 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), |
Paul Walmsley | b115b74 | 2010-10-08 11:40:18 -0600 | [diff] [blame] | 1860 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1861 | /* internal analog sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1862 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
| 1863 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), |
| 1864 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1865 | /* internal prcm root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1866 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
| 1867 | CLK(NULL, "core_ck", &core_ck, CK_243X), |
| 1868 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
| 1869 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), |
| 1870 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), |
| 1871 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), |
| 1872 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), |
| 1873 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), |
| 1874 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1875 | /* mpu domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1876 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1877 | /* dsp domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1878 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1879 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1880 | /* GFX domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1881 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), |
| 1882 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), |
| 1883 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1884 | /* Modem domain clocks */ |
| 1885 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), |
| 1886 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), |
| 1887 | /* DSS domain clocks */ |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 1888 | CLK("omapdss_dss", "ick", &dss_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1889 | CLK(NULL, "dss_ick", &dss_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1890 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), |
| 1891 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), |
| 1892 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1893 | /* L3 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1894 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), |
| 1895 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), |
| 1896 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1897 | /* L4 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1898 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), |
| 1899 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), |
Paul Walmsley | 19c1c0c | 2011-02-16 15:38:38 -0700 | [diff] [blame] | 1900 | CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1901 | /* virtual meta-group clock */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1902 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1903 | /* general l4 interface ck, multi-parent functional clk */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1904 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), |
| 1905 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), |
| 1906 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), |
| 1907 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), |
| 1908 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), |
| 1909 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), |
| 1910 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), |
| 1911 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), |
| 1912 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), |
| 1913 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), |
| 1914 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), |
| 1915 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), |
| 1916 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), |
| 1917 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), |
| 1918 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), |
| 1919 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), |
| 1920 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), |
| 1921 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), |
| 1922 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), |
| 1923 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), |
| 1924 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), |
| 1925 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), |
| 1926 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), |
| 1927 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), |
| 1928 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1929 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1930 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1931 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1932 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1933 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1934 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1935 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1936 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1937 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1938 | CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1939 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1940 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1941 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1942 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1943 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1944 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1945 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1946 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1947 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1948 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1949 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1950 | CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1951 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1952 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), |
| 1953 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), |
| 1954 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), |
| 1955 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), |
| 1956 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), |
| 1957 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), |
| 1958 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), |
| 1959 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), |
| 1960 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1961 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1962 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1963 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), |
| 1964 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), |
| 1965 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1966 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1967 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1968 | CLK(NULL, "cam_fck", &cam_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1969 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1970 | CLK(NULL, "cam_ick", &cam_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1971 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), |
| 1972 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), |
| 1973 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), |
| 1974 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), |
| 1975 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), |
| 1976 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), |
| 1977 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), |
| 1978 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1979 | CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1980 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1981 | CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 1982 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1983 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1984 | CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 1985 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1986 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 1987 | CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1988 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
| 1989 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), |
| 1990 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1991 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1992 | CLK(NULL, "des_ick", &des_ick, CK_243X), |
Dmitry Kasatkin | ee5500c | 2010-05-03 11:10:03 +0800 | [diff] [blame] | 1993 | CLK("omap-sham", "ick", &sha_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1994 | CLK("omap_rng", "ick", &rng_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 1995 | CLK(NULL, "rng_ick", &rng_ick, CK_243X), |
Dmitry Kasatkin | 82a0c14 | 2010-08-20 13:44:46 +0000 | [diff] [blame] | 1996 | CLK("omap-aes", "ick", &aes_ick, CK_243X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 1997 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), |
| 1998 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), |
Felipe Balbi | 0349176 | 2010-12-02 09:57:08 +0200 | [diff] [blame] | 1999 | CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 2000 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 2001 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 2002 | CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 2003 | CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 2004 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 2005 | CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 2006 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2007 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), |
| 2008 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), |
| 2009 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 2010 | CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 2011 | CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 2012 | CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 2013 | CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), |
Jon Hunter | c59b537 | 2012-06-05 12:35:00 -0500 | [diff] [blame] | 2014 | CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), |
| 2015 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), |
| 2016 | CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), |
Paul Walmsley | c810fde | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 2017 | CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2018 | }; |
| 2019 | |
| 2020 | /* |
| 2021 | * init code |
| 2022 | */ |
| 2023 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2024 | int __init omap2430_clk_init(void) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2025 | { |
| 2026 | const struct prcm_config *prcm; |
| 2027 | struct omap_clk *c; |
| 2028 | u32 clkrate; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2029 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2030 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; |
| 2031 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); |
| 2032 | cpu_mask = RATE_IN_243X; |
| 2033 | rate_table = omap2430_rate_table; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2034 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2035 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
| 2036 | c++) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2037 | clk_preinit(c->lk.clk); |
| 2038 | |
| 2039 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 2040 | propagate_rate(&osc_ck); |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 2041 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2042 | propagate_rate(&sys_ck); |
| 2043 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2044 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
| 2045 | c++) { |
| 2046 | clkdev_add(&c->lk); |
| 2047 | clk_register(c->lk.clk); |
| 2048 | omap2_init_clk_clkdm(c->lk.clk); |
| 2049 | } |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2050 | |
Paul Walmsley | c6461f5 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 2051 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
| 2052 | omap_clk_disable_autoidle_all(); |
| 2053 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2054 | /* Check the MPU rate set by bootloader */ |
| 2055 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 2056 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 2057 | if (!(prcm->flags & cpu_mask)) |
| 2058 | continue; |
| 2059 | if (prcm->xtal_speed != sys_ck.rate) |
| 2060 | continue; |
| 2061 | if (prcm->dpll_speed <= clkrate) |
| 2062 | break; |
| 2063 | } |
| 2064 | curr_prcm_set = prcm; |
| 2065 | |
| 2066 | recalculate_root_clocks(); |
| 2067 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame] | 2068 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 2069 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 2070 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 2071 | |
| 2072 | /* |
| 2073 | * Only enable those clocks we will need, let the drivers |
| 2074 | * enable other clocks as necessary |
| 2075 | */ |
| 2076 | clk_enable_init_clocks(); |
| 2077 | |
| 2078 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
| 2079 | vclk = clk_get(NULL, "virt_prcm_set"); |
| 2080 | sclk = clk_get(NULL, "sys_ck"); |
| 2081 | dclk = clk_get(NULL, "dpll_ck"); |
| 2082 | |
| 2083 | return 0; |
| 2084 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 2085 | |