Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 Clock data |
| 3 | * |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) |
| 8 | * Rajendra Nayak (rnayak@ti.com) |
| 9 | * Benoit Cousson (b-cousson@ti.com) |
| 10 | * |
| 11 | * This file is automatically generated from the OMAP hardware databases. |
| 12 | * We respectfully ask that any modifications to this file be coordinated |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 14 | * authors above to ensure that the autogeneration scripts are kept |
| 15 | * up-to-date with the file contents. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 20 | * |
| 21 | * XXX Some of the ES1 clocks have been removed/changed; once support |
| 22 | * is added for discriminating clocks by ES level, these should be added back |
| 23 | * in. |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include <linux/kernel.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 27 | #include <linux/list.h> |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 28 | #include <linux/clk.h> |
Rob Herring | 6f6f6a7 | 2012-03-10 10:30:31 -0600 | [diff] [blame] | 29 | #include <linux/io.h> |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 32 | #include "iomap.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 33 | #include "clock.h" |
| 34 | #include "clock44xx.h" |
Paul Walmsley | d198b51 | 2010-12-21 15:30:54 -0700 | [diff] [blame] | 35 | #include "cm1_44xx.h" |
| 36 | #include "cm2_44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 37 | #include "cm-regbits-44xx.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 38 | #include "prm44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 39 | #include "prm-regbits-44xx.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 40 | #include "control.h" |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 41 | #include "scrm44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 42 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 43 | /* OMAP4 modulemode control */ |
| 44 | #define OMAP4430_MODULEMODE_HWCTRL 0 |
| 45 | #define OMAP4430_MODULEMODE_SWCTRL 1 |
| 46 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 47 | /* Root clocks */ |
| 48 | |
| 49 | static struct clk extalt_clkin_ck = { |
| 50 | .name = "extalt_clkin_ck", |
| 51 | .rate = 59000000, |
| 52 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | static struct clk pad_clks_ck = { |
| 56 | .name = "pad_clks_ck", |
| 57 | .rate = 12000000, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 58 | .ops = &clkops_omap2_dflt, |
| 59 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, |
| 60 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static struct clk pad_slimbus_core_clks_ck = { |
| 64 | .name = "pad_slimbus_core_clks_ck", |
| 65 | .rate = 12000000, |
| 66 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static struct clk secure_32k_clk_src_ck = { |
| 70 | .name = "secure_32k_clk_src_ck", |
| 71 | .rate = 32768, |
| 72 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | static struct clk slimbus_clk = { |
| 76 | .name = "slimbus_clk", |
| 77 | .rate = 12000000, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 78 | .ops = &clkops_omap2_dflt, |
| 79 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, |
| 80 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | static struct clk sys_32k_ck = { |
| 84 | .name = "sys_32k_ck", |
Paul Walmsley | 9a47d32 | 2012-06-17 11:57:52 -0600 | [diff] [blame] | 85 | .clkdm_name = "prm_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 86 | .rate = 32768, |
| 87 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | static struct clk virt_12000000_ck = { |
| 91 | .name = "virt_12000000_ck", |
| 92 | .ops = &clkops_null, |
| 93 | .rate = 12000000, |
| 94 | }; |
| 95 | |
| 96 | static struct clk virt_13000000_ck = { |
| 97 | .name = "virt_13000000_ck", |
| 98 | .ops = &clkops_null, |
| 99 | .rate = 13000000, |
| 100 | }; |
| 101 | |
| 102 | static struct clk virt_16800000_ck = { |
| 103 | .name = "virt_16800000_ck", |
| 104 | .ops = &clkops_null, |
| 105 | .rate = 16800000, |
| 106 | }; |
| 107 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 108 | static struct clk virt_27000000_ck = { |
| 109 | .name = "virt_27000000_ck", |
| 110 | .ops = &clkops_null, |
| 111 | .rate = 27000000, |
| 112 | }; |
| 113 | |
| 114 | static struct clk virt_38400000_ck = { |
| 115 | .name = "virt_38400000_ck", |
| 116 | .ops = &clkops_null, |
| 117 | .rate = 38400000, |
| 118 | }; |
| 119 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 120 | static const struct clksel_rate div_1_5_rates[] = { |
| 121 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, |
| 122 | { .div = 0 }, |
| 123 | }; |
| 124 | |
| 125 | static const struct clksel_rate div_1_6_rates[] = { |
| 126 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, |
| 127 | { .div = 0 }, |
| 128 | }; |
| 129 | |
| 130 | static const struct clksel_rate div_1_7_rates[] = { |
| 131 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, |
| 132 | { .div = 0 }, |
| 133 | }; |
| 134 | |
| 135 | static const struct clksel sys_clkin_sel[] = { |
| 136 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, |
| 137 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, |
| 138 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, |
| 139 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, |
| 140 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, |
| 141 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, |
| 142 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, |
| 143 | { .parent = NULL }, |
| 144 | }; |
| 145 | |
| 146 | static struct clk sys_clkin_ck = { |
| 147 | .name = "sys_clkin_ck", |
| 148 | .rate = 38400000, |
| 149 | .clksel = sys_clkin_sel, |
| 150 | .init = &omap2_init_clksel_parent, |
| 151 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, |
| 152 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, |
| 153 | .ops = &clkops_null, |
| 154 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 155 | }; |
| 156 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 157 | static struct clk tie_low_clock_ck = { |
| 158 | .name = "tie_low_clock_ck", |
| 159 | .rate = 0, |
| 160 | .ops = &clkops_null, |
| 161 | }; |
| 162 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 163 | static struct clk utmi_phy_clkout_ck = { |
| 164 | .name = "utmi_phy_clkout_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 165 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 166 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 167 | }; |
| 168 | |
| 169 | static struct clk xclk60mhsp1_ck = { |
| 170 | .name = "xclk60mhsp1_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 171 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 172 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | static struct clk xclk60mhsp2_ck = { |
| 176 | .name = "xclk60mhsp2_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 177 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 178 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | static struct clk xclk60motg_ck = { |
| 182 | .name = "xclk60motg_ck", |
| 183 | .rate = 60000000, |
| 184 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | /* Module clocks and DPLL outputs */ |
| 188 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 189 | static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { |
| 190 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 191 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, |
| 192 | { .parent = NULL }, |
| 193 | }; |
| 194 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 195 | static struct clk abe_dpll_bypass_clk_mux_ck = { |
| 196 | .name = "abe_dpll_bypass_clk_mux_ck", |
| 197 | .parent = &sys_clkin_ck, |
| 198 | .ops = &clkops_null, |
| 199 | .recalc = &followparent_recalc, |
| 200 | }; |
| 201 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 202 | static struct clk abe_dpll_refclk_mux_ck = { |
| 203 | .name = "abe_dpll_refclk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 204 | .parent = &sys_clkin_ck, |
| 205 | .clksel = abe_dpll_bypass_clk_mux_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 206 | .init = &omap2_init_clksel_parent, |
| 207 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, |
| 208 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 209 | .ops = &clkops_null, |
| 210 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | /* DPLL_ABE */ |
| 214 | static struct dpll_data dpll_abe_dd = { |
| 215 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 216 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 217 | .clk_ref = &abe_dpll_refclk_mux_ck, |
| 218 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, |
| 219 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 220 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, |
| 221 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, |
| 222 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 223 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 224 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 225 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 226 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 227 | .max_multiplier = 2047, |
| 228 | .max_divider = 128, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 229 | .min_divider = 1, |
| 230 | }; |
| 231 | |
| 232 | |
| 233 | static struct clk dpll_abe_ck = { |
| 234 | .name = "dpll_abe_ck", |
| 235 | .parent = &abe_dpll_refclk_mux_ck, |
| 236 | .dpll_data = &dpll_abe_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 237 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 238 | .ops = &clkops_omap3_noncore_dpll_ops, |
Mike Turquette | a1900f2 | 2011-10-07 00:52:58 -0600 | [diff] [blame] | 239 | .recalc = &omap4_dpll_regm4xen_recalc, |
| 240 | .round_rate = &omap4_dpll_regm4xen_round_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 241 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 244 | static struct clk dpll_abe_x2_ck = { |
| 245 | .name = "dpll_abe_x2_ck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 246 | .parent = &dpll_abe_ck, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 247 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 248 | .flags = CLOCK_CLKOUTX2, |
| 249 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 250 | .recalc = &omap3_clkoutx2_recalc, |
| 251 | }; |
| 252 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 253 | static const struct clksel dpll_abe_m2x2_div[] = { |
| 254 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, |
| 255 | { .parent = NULL }, |
| 256 | }; |
| 257 | |
| 258 | static struct clk dpll_abe_m2x2_ck = { |
| 259 | .name = "dpll_abe_m2x2_ck", |
| 260 | .parent = &dpll_abe_x2_ck, |
| 261 | .clksel = dpll_abe_m2x2_div, |
| 262 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
| 263 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 264 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 265 | .recalc = &omap2_clksel_recalc, |
| 266 | .round_rate = &omap2_clksel_round_rate, |
| 267 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 268 | }; |
| 269 | |
| 270 | static struct clk abe_24m_fclk = { |
| 271 | .name = "abe_24m_fclk", |
| 272 | .parent = &dpll_abe_m2x2_ck, |
| 273 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 274 | .fixed_div = 8, |
| 275 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static const struct clksel_rate div3_1to4_rates[] = { |
| 279 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 280 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 281 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, |
| 282 | { .div = 0 }, |
| 283 | }; |
| 284 | |
| 285 | static const struct clksel abe_clk_div[] = { |
| 286 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, |
| 287 | { .parent = NULL }, |
| 288 | }; |
| 289 | |
| 290 | static struct clk abe_clk = { |
| 291 | .name = "abe_clk", |
| 292 | .parent = &dpll_abe_m2x2_ck, |
| 293 | .clksel = abe_clk_div, |
| 294 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, |
| 295 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, |
| 296 | .ops = &clkops_null, |
| 297 | .recalc = &omap2_clksel_recalc, |
| 298 | .round_rate = &omap2_clksel_round_rate, |
| 299 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 300 | }; |
| 301 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 302 | static const struct clksel_rate div2_1to2_rates[] = { |
| 303 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 304 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 305 | { .div = 0 }, |
| 306 | }; |
| 307 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 308 | static const struct clksel aess_fclk_div[] = { |
| 309 | { .parent = &abe_clk, .rates = div2_1to2_rates }, |
| 310 | { .parent = NULL }, |
| 311 | }; |
| 312 | |
| 313 | static struct clk aess_fclk = { |
| 314 | .name = "aess_fclk", |
| 315 | .parent = &abe_clk, |
| 316 | .clksel = aess_fclk_div, |
| 317 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 318 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, |
| 319 | .ops = &clkops_null, |
| 320 | .recalc = &omap2_clksel_recalc, |
| 321 | .round_rate = &omap2_clksel_round_rate, |
| 322 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 323 | }; |
| 324 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 325 | static struct clk dpll_abe_m3x2_ck = { |
| 326 | .name = "dpll_abe_m3x2_ck", |
| 327 | .parent = &dpll_abe_x2_ck, |
| 328 | .clksel = dpll_abe_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 329 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
| 330 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 331 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 332 | .recalc = &omap2_clksel_recalc, |
| 333 | .round_rate = &omap2_clksel_round_rate, |
| 334 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 338 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 339 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 340 | { .parent = NULL }, |
| 341 | }; |
| 342 | |
| 343 | static struct clk core_hsd_byp_clk_mux_ck = { |
| 344 | .name = "core_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 345 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 346 | .clksel = core_hsd_byp_clk_mux_sel, |
| 347 | .init = &omap2_init_clksel_parent, |
| 348 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, |
| 349 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 350 | .ops = &clkops_null, |
| 351 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | /* DPLL_CORE */ |
| 355 | static struct dpll_data dpll_core_dd = { |
| 356 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, |
| 357 | .clk_bypass = &core_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 358 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 359 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, |
| 360 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 361 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, |
| 362 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, |
| 363 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 364 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 365 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 366 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 367 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 368 | .max_multiplier = 2047, |
| 369 | .max_divider = 128, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 370 | .min_divider = 1, |
| 371 | }; |
| 372 | |
| 373 | |
| 374 | static struct clk dpll_core_ck = { |
| 375 | .name = "dpll_core_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 376 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 377 | .dpll_data = &dpll_core_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 378 | .init = &omap2_init_dpll_parent, |
Rajendra Nayak | 6c6f5a7 | 2011-02-25 15:49:00 -0700 | [diff] [blame] | 379 | .ops = &clkops_omap3_core_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 380 | .recalc = &omap3_dpll_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 381 | }; |
| 382 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 383 | static struct clk dpll_core_x2_ck = { |
| 384 | .name = "dpll_core_x2_ck", |
| 385 | .parent = &dpll_core_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 386 | .flags = CLOCK_CLKOUTX2, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 387 | .ops = &clkops_null, |
| 388 | .recalc = &omap3_clkoutx2_recalc, |
| 389 | }; |
| 390 | |
| 391 | static const struct clksel dpll_core_m6x2_div[] = { |
| 392 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 393 | { .parent = NULL }, |
| 394 | }; |
| 395 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 396 | static struct clk dpll_core_m6x2_ck = { |
| 397 | .name = "dpll_core_m6x2_ck", |
| 398 | .parent = &dpll_core_x2_ck, |
| 399 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 400 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
| 401 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 402 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 403 | .recalc = &omap2_clksel_recalc, |
| 404 | .round_rate = &omap2_clksel_round_rate, |
| 405 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 406 | }; |
| 407 | |
| 408 | static const struct clksel dbgclk_mux_sel[] = { |
| 409 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 410 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 411 | { .parent = NULL }, |
| 412 | }; |
| 413 | |
| 414 | static struct clk dbgclk_mux_ck = { |
| 415 | .name = "dbgclk_mux_ck", |
| 416 | .parent = &sys_clkin_ck, |
| 417 | .ops = &clkops_null, |
| 418 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 419 | }; |
| 420 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 421 | static const struct clksel dpll_core_m2_div[] = { |
| 422 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, |
| 423 | { .parent = NULL }, |
| 424 | }; |
| 425 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 426 | static struct clk dpll_core_m2_ck = { |
| 427 | .name = "dpll_core_m2_ck", |
| 428 | .parent = &dpll_core_ck, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 429 | .clksel = dpll_core_m2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 430 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
| 431 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 432 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 433 | .recalc = &omap2_clksel_recalc, |
| 434 | .round_rate = &omap2_clksel_round_rate, |
| 435 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | static struct clk ddrphy_ck = { |
| 439 | .name = "ddrphy_ck", |
| 440 | .parent = &dpll_core_m2_ck, |
| 441 | .ops = &clkops_null, |
Paul Walmsley | 9a47d32 | 2012-06-17 11:57:52 -0600 | [diff] [blame] | 442 | .clkdm_name = "l3_emif_clkdm", |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 443 | .fixed_div = 2, |
| 444 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 445 | }; |
| 446 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 447 | static struct clk dpll_core_m5x2_ck = { |
| 448 | .name = "dpll_core_m5x2_ck", |
| 449 | .parent = &dpll_core_x2_ck, |
| 450 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 451 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
| 452 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 453 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 454 | .recalc = &omap2_clksel_recalc, |
| 455 | .round_rate = &omap2_clksel_round_rate, |
| 456 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | static const struct clksel div_core_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 460 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 461 | { .parent = NULL }, |
| 462 | }; |
| 463 | |
| 464 | static struct clk div_core_ck = { |
| 465 | .name = "div_core_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 466 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 467 | .clksel = div_core_div, |
| 468 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 469 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, |
| 470 | .ops = &clkops_null, |
| 471 | .recalc = &omap2_clksel_recalc, |
| 472 | .round_rate = &omap2_clksel_round_rate, |
| 473 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 474 | }; |
| 475 | |
| 476 | static const struct clksel_rate div4_1to8_rates[] = { |
| 477 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 478 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 479 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, |
| 480 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, |
| 481 | { .div = 0 }, |
| 482 | }; |
| 483 | |
| 484 | static const struct clksel div_iva_hs_clk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 485 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 486 | { .parent = NULL }, |
| 487 | }; |
| 488 | |
| 489 | static struct clk div_iva_hs_clk = { |
| 490 | .name = "div_iva_hs_clk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 491 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 492 | .clksel = div_iva_hs_clk_div, |
| 493 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, |
| 494 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| 495 | .ops = &clkops_null, |
| 496 | .recalc = &omap2_clksel_recalc, |
| 497 | .round_rate = &omap2_clksel_round_rate, |
| 498 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 499 | }; |
| 500 | |
| 501 | static struct clk div_mpu_hs_clk = { |
| 502 | .name = "div_mpu_hs_clk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 503 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 504 | .clksel = div_iva_hs_clk_div, |
| 505 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, |
| 506 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| 507 | .ops = &clkops_null, |
| 508 | .recalc = &omap2_clksel_recalc, |
| 509 | .round_rate = &omap2_clksel_round_rate, |
| 510 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 511 | }; |
| 512 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 513 | static struct clk dpll_core_m4x2_ck = { |
| 514 | .name = "dpll_core_m4x2_ck", |
| 515 | .parent = &dpll_core_x2_ck, |
| 516 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 517 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
| 518 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 519 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 520 | .recalc = &omap2_clksel_recalc, |
| 521 | .round_rate = &omap2_clksel_round_rate, |
| 522 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 523 | }; |
| 524 | |
| 525 | static struct clk dll_clk_div_ck = { |
| 526 | .name = "dll_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 527 | .parent = &dpll_core_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 528 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 529 | .fixed_div = 2, |
| 530 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 531 | }; |
| 532 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 533 | static const struct clksel dpll_abe_m2_div[] = { |
| 534 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, |
| 535 | { .parent = NULL }, |
| 536 | }; |
| 537 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 538 | static struct clk dpll_abe_m2_ck = { |
| 539 | .name = "dpll_abe_m2_ck", |
| 540 | .parent = &dpll_abe_ck, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 541 | .clksel = dpll_abe_m2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 542 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
| 543 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 544 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 545 | .recalc = &omap2_clksel_recalc, |
| 546 | .round_rate = &omap2_clksel_round_rate, |
| 547 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 548 | }; |
| 549 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 550 | static struct clk dpll_core_m3x2_ck = { |
| 551 | .name = "dpll_core_m3x2_ck", |
| 552 | .parent = &dpll_core_x2_ck, |
| 553 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 554 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
| 555 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | cb13459 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 556 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 557 | .recalc = &omap2_clksel_recalc, |
| 558 | .round_rate = &omap2_clksel_round_rate, |
| 559 | .set_rate = &omap2_clksel_set_rate, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 560 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
| 561 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 562 | }; |
| 563 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 564 | static struct clk dpll_core_m7x2_ck = { |
| 565 | .name = "dpll_core_m7x2_ck", |
| 566 | .parent = &dpll_core_x2_ck, |
| 567 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 568 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
| 569 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 570 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 571 | .recalc = &omap2_clksel_recalc, |
| 572 | .round_rate = &omap2_clksel_round_rate, |
| 573 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 574 | }; |
| 575 | |
| 576 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 577 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 578 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, |
| 579 | { .parent = NULL }, |
| 580 | }; |
| 581 | |
| 582 | static struct clk iva_hsd_byp_clk_mux_ck = { |
| 583 | .name = "iva_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 584 | .parent = &sys_clkin_ck, |
Jonathan Bergsagel | 768ab94 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 585 | .clksel = iva_hsd_byp_clk_mux_sel, |
| 586 | .init = &omap2_init_clksel_parent, |
| 587 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, |
| 588 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 589 | .ops = &clkops_null, |
Jonathan Bergsagel | 768ab94 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 590 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 591 | }; |
| 592 | |
| 593 | /* DPLL_IVA */ |
| 594 | static struct dpll_data dpll_iva_dd = { |
| 595 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, |
| 596 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 597 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 598 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, |
| 599 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 600 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, |
| 601 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, |
| 602 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 603 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 604 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 605 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 606 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 607 | .max_multiplier = 2047, |
| 608 | .max_divider = 128, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 609 | .min_divider = 1, |
| 610 | }; |
| 611 | |
| 612 | |
| 613 | static struct clk dpll_iva_ck = { |
| 614 | .name = "dpll_iva_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 615 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 616 | .dpll_data = &dpll_iva_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 617 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 618 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 619 | .recalc = &omap3_dpll_recalc, |
| 620 | .round_rate = &omap2_dpll_round_rate, |
| 621 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 622 | }; |
| 623 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 624 | static struct clk dpll_iva_x2_ck = { |
| 625 | .name = "dpll_iva_x2_ck", |
| 626 | .parent = &dpll_iva_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 627 | .flags = CLOCK_CLKOUTX2, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 628 | .ops = &clkops_null, |
| 629 | .recalc = &omap3_clkoutx2_recalc, |
| 630 | }; |
| 631 | |
| 632 | static const struct clksel dpll_iva_m4x2_div[] = { |
| 633 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 634 | { .parent = NULL }, |
| 635 | }; |
| 636 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 637 | static struct clk dpll_iva_m4x2_ck = { |
| 638 | .name = "dpll_iva_m4x2_ck", |
| 639 | .parent = &dpll_iva_x2_ck, |
| 640 | .clksel = dpll_iva_m4x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 641 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
| 642 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 643 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 644 | .recalc = &omap2_clksel_recalc, |
| 645 | .round_rate = &omap2_clksel_round_rate, |
| 646 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 647 | }; |
| 648 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 649 | static struct clk dpll_iva_m5x2_ck = { |
| 650 | .name = "dpll_iva_m5x2_ck", |
| 651 | .parent = &dpll_iva_x2_ck, |
| 652 | .clksel = dpll_iva_m4x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 653 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
| 654 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 655 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 656 | .recalc = &omap2_clksel_recalc, |
| 657 | .round_rate = &omap2_clksel_round_rate, |
| 658 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
| 661 | /* DPLL_MPU */ |
| 662 | static struct dpll_data dpll_mpu_dd = { |
| 663 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, |
| 664 | .clk_bypass = &div_mpu_hs_clk, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 665 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 666 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, |
| 667 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 668 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, |
| 669 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, |
| 670 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 671 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 672 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 673 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 674 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 675 | .max_multiplier = 2047, |
| 676 | .max_divider = 128, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 677 | .min_divider = 1, |
| 678 | }; |
| 679 | |
| 680 | |
| 681 | static struct clk dpll_mpu_ck = { |
| 682 | .name = "dpll_mpu_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 683 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 684 | .dpll_data = &dpll_mpu_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 685 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 686 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 687 | .recalc = &omap3_dpll_recalc, |
| 688 | .round_rate = &omap2_dpll_round_rate, |
| 689 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 690 | }; |
| 691 | |
| 692 | static const struct clksel dpll_mpu_m2_div[] = { |
| 693 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, |
| 694 | { .parent = NULL }, |
| 695 | }; |
| 696 | |
| 697 | static struct clk dpll_mpu_m2_ck = { |
| 698 | .name = "dpll_mpu_m2_ck", |
| 699 | .parent = &dpll_mpu_ck, |
Paul Walmsley | 9a47d32 | 2012-06-17 11:57:52 -0600 | [diff] [blame] | 700 | .clkdm_name = "cm_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 701 | .clksel = dpll_mpu_m2_div, |
| 702 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, |
| 703 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 704 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 705 | .recalc = &omap2_clksel_recalc, |
| 706 | .round_rate = &omap2_clksel_round_rate, |
| 707 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 708 | }; |
| 709 | |
| 710 | static struct clk per_hs_clk_div_ck = { |
| 711 | .name = "per_hs_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 712 | .parent = &dpll_abe_m3x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 713 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 714 | .fixed_div = 2, |
| 715 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 716 | }; |
| 717 | |
| 718 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 719 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 720 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, |
| 721 | { .parent = NULL }, |
| 722 | }; |
| 723 | |
| 724 | static struct clk per_hsd_byp_clk_mux_ck = { |
| 725 | .name = "per_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 726 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 727 | .clksel = per_hsd_byp_clk_mux_sel, |
| 728 | .init = &omap2_init_clksel_parent, |
| 729 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, |
| 730 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 731 | .ops = &clkops_null, |
| 732 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 733 | }; |
| 734 | |
| 735 | /* DPLL_PER */ |
| 736 | static struct dpll_data dpll_per_dd = { |
| 737 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, |
| 738 | .clk_bypass = &per_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 739 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 740 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, |
| 741 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 742 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, |
| 743 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, |
| 744 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 745 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 746 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 747 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 748 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 749 | .max_multiplier = 2047, |
| 750 | .max_divider = 128, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 751 | .min_divider = 1, |
| 752 | }; |
| 753 | |
| 754 | |
| 755 | static struct clk dpll_per_ck = { |
| 756 | .name = "dpll_per_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 757 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 758 | .dpll_data = &dpll_per_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 759 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 760 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 761 | .recalc = &omap3_dpll_recalc, |
| 762 | .round_rate = &omap2_dpll_round_rate, |
| 763 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 764 | }; |
| 765 | |
| 766 | static const struct clksel dpll_per_m2_div[] = { |
| 767 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, |
| 768 | { .parent = NULL }, |
| 769 | }; |
| 770 | |
| 771 | static struct clk dpll_per_m2_ck = { |
| 772 | .name = "dpll_per_m2_ck", |
| 773 | .parent = &dpll_per_ck, |
| 774 | .clksel = dpll_per_m2_div, |
| 775 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
| 776 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 777 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 778 | .recalc = &omap2_clksel_recalc, |
| 779 | .round_rate = &omap2_clksel_round_rate, |
| 780 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 781 | }; |
| 782 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 783 | static struct clk dpll_per_x2_ck = { |
| 784 | .name = "dpll_per_x2_ck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 785 | .parent = &dpll_per_ck, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 786 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 787 | .flags = CLOCK_CLKOUTX2, |
| 788 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 789 | .recalc = &omap3_clkoutx2_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 790 | }; |
| 791 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 792 | static const struct clksel dpll_per_m2x2_div[] = { |
| 793 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, |
| 794 | { .parent = NULL }, |
| 795 | }; |
| 796 | |
| 797 | static struct clk dpll_per_m2x2_ck = { |
| 798 | .name = "dpll_per_m2x2_ck", |
| 799 | .parent = &dpll_per_x2_ck, |
| 800 | .clksel = dpll_per_m2x2_div, |
| 801 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
| 802 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 803 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 804 | .recalc = &omap2_clksel_recalc, |
| 805 | .round_rate = &omap2_clksel_round_rate, |
| 806 | .set_rate = &omap2_clksel_set_rate, |
| 807 | }; |
| 808 | |
| 809 | static struct clk dpll_per_m3x2_ck = { |
| 810 | .name = "dpll_per_m3x2_ck", |
| 811 | .parent = &dpll_per_x2_ck, |
| 812 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 813 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
| 814 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | cb13459 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 815 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 816 | .recalc = &omap2_clksel_recalc, |
| 817 | .round_rate = &omap2_clksel_round_rate, |
| 818 | .set_rate = &omap2_clksel_set_rate, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 819 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
| 820 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 821 | }; |
| 822 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 823 | static struct clk dpll_per_m4x2_ck = { |
| 824 | .name = "dpll_per_m4x2_ck", |
| 825 | .parent = &dpll_per_x2_ck, |
| 826 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 827 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
| 828 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 829 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 830 | .recalc = &omap2_clksel_recalc, |
| 831 | .round_rate = &omap2_clksel_round_rate, |
| 832 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 833 | }; |
| 834 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 835 | static struct clk dpll_per_m5x2_ck = { |
| 836 | .name = "dpll_per_m5x2_ck", |
| 837 | .parent = &dpll_per_x2_ck, |
| 838 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 839 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
| 840 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 841 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 842 | .recalc = &omap2_clksel_recalc, |
| 843 | .round_rate = &omap2_clksel_round_rate, |
| 844 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 845 | }; |
| 846 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 847 | static struct clk dpll_per_m6x2_ck = { |
| 848 | .name = "dpll_per_m6x2_ck", |
| 849 | .parent = &dpll_per_x2_ck, |
| 850 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 851 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
| 852 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 853 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 854 | .recalc = &omap2_clksel_recalc, |
| 855 | .round_rate = &omap2_clksel_round_rate, |
| 856 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 857 | }; |
| 858 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 859 | static struct clk dpll_per_m7x2_ck = { |
| 860 | .name = "dpll_per_m7x2_ck", |
| 861 | .parent = &dpll_per_x2_ck, |
| 862 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 863 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
| 864 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 865 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 866 | .recalc = &omap2_clksel_recalc, |
| 867 | .round_rate = &omap2_clksel_round_rate, |
| 868 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 869 | }; |
| 870 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 871 | static struct clk usb_hs_clk_div_ck = { |
| 872 | .name = "usb_hs_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 873 | .parent = &dpll_abe_m3x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 874 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 875 | .fixed_div = 3, |
| 876 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 877 | }; |
| 878 | |
| 879 | /* DPLL_USB */ |
| 880 | static struct dpll_data dpll_usb_dd = { |
| 881 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, |
| 882 | .clk_bypass = &usb_hs_clk_div_ck, |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 883 | .flags = DPLL_J_TYPE, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 884 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 885 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
| 886 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 887 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, |
| 888 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, |
Ameya Palande | 91a290c | 2012-04-04 10:19:31 -0600 | [diff] [blame] | 889 | .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, |
| 890 | .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 891 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 892 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 893 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Benoit Cousson | 962519e | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 894 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, |
Benoit Cousson | 628479a | 2011-07-09 19:14:46 -0600 | [diff] [blame] | 895 | .max_multiplier = 4095, |
| 896 | .max_divider = 256, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 897 | .min_divider = 1, |
| 898 | }; |
| 899 | |
| 900 | |
| 901 | static struct clk dpll_usb_ck = { |
| 902 | .name = "dpll_usb_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 903 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 904 | .dpll_data = &dpll_usb_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 905 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 906 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 907 | .recalc = &omap3_dpll_recalc, |
| 908 | .round_rate = &omap2_dpll_round_rate, |
| 909 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 6c4a057 | 2012-04-04 10:20:01 -0600 | [diff] [blame] | 910 | .clkdm_name = "l3_init_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 911 | }; |
| 912 | |
| 913 | static struct clk dpll_usb_clkdcoldo_ck = { |
| 914 | .name = "dpll_usb_clkdcoldo_ck", |
| 915 | .parent = &dpll_usb_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 916 | .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 917 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 918 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 919 | }; |
| 920 | |
| 921 | static const struct clksel dpll_usb_m2_div[] = { |
| 922 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, |
| 923 | { .parent = NULL }, |
| 924 | }; |
| 925 | |
| 926 | static struct clk dpll_usb_m2_ck = { |
| 927 | .name = "dpll_usb_m2_ck", |
| 928 | .parent = &dpll_usb_ck, |
| 929 | .clksel = dpll_usb_m2_div, |
| 930 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, |
| 931 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 932 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 933 | .recalc = &omap2_clksel_recalc, |
| 934 | .round_rate = &omap2_clksel_round_rate, |
| 935 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 936 | }; |
| 937 | |
| 938 | static const struct clksel ducati_clk_mux_sel[] = { |
| 939 | { .parent = &div_core_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 940 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 941 | { .parent = NULL }, |
| 942 | }; |
| 943 | |
| 944 | static struct clk ducati_clk_mux_ck = { |
| 945 | .name = "ducati_clk_mux_ck", |
| 946 | .parent = &div_core_ck, |
| 947 | .clksel = ducati_clk_mux_sel, |
| 948 | .init = &omap2_init_clksel_parent, |
| 949 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, |
| 950 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 951 | .ops = &clkops_null, |
| 952 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 953 | }; |
| 954 | |
| 955 | static struct clk func_12m_fclk = { |
| 956 | .name = "func_12m_fclk", |
| 957 | .parent = &dpll_per_m2x2_ck, |
| 958 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 959 | .fixed_div = 16, |
| 960 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 961 | }; |
| 962 | |
| 963 | static struct clk func_24m_clk = { |
| 964 | .name = "func_24m_clk", |
| 965 | .parent = &dpll_per_m2_ck, |
| 966 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 967 | .fixed_div = 4, |
| 968 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 969 | }; |
| 970 | |
| 971 | static struct clk func_24mc_fclk = { |
| 972 | .name = "func_24mc_fclk", |
| 973 | .parent = &dpll_per_m2x2_ck, |
| 974 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 975 | .fixed_div = 8, |
| 976 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 977 | }; |
| 978 | |
| 979 | static const struct clksel_rate div2_4to8_rates[] = { |
| 980 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, |
| 981 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, |
| 982 | { .div = 0 }, |
| 983 | }; |
| 984 | |
| 985 | static const struct clksel func_48m_fclk_div[] = { |
| 986 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, |
| 987 | { .parent = NULL }, |
| 988 | }; |
| 989 | |
| 990 | static struct clk func_48m_fclk = { |
| 991 | .name = "func_48m_fclk", |
| 992 | .parent = &dpll_per_m2x2_ck, |
| 993 | .clksel = func_48m_fclk_div, |
| 994 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 995 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 996 | .ops = &clkops_null, |
| 997 | .recalc = &omap2_clksel_recalc, |
| 998 | .round_rate = &omap2_clksel_round_rate, |
| 999 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1000 | }; |
| 1001 | |
| 1002 | static struct clk func_48mc_fclk = { |
| 1003 | .name = "func_48mc_fclk", |
| 1004 | .parent = &dpll_per_m2x2_ck, |
| 1005 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1006 | .fixed_div = 4, |
| 1007 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1008 | }; |
| 1009 | |
| 1010 | static const struct clksel_rate div2_2to4_rates[] = { |
| 1011 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, |
| 1012 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, |
| 1013 | { .div = 0 }, |
| 1014 | }; |
| 1015 | |
| 1016 | static const struct clksel func_64m_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1017 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1018 | { .parent = NULL }, |
| 1019 | }; |
| 1020 | |
| 1021 | static struct clk func_64m_fclk = { |
| 1022 | .name = "func_64m_fclk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1023 | .parent = &dpll_per_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1024 | .clksel = func_64m_fclk_div, |
| 1025 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1026 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1027 | .ops = &clkops_null, |
| 1028 | .recalc = &omap2_clksel_recalc, |
| 1029 | .round_rate = &omap2_clksel_round_rate, |
| 1030 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1031 | }; |
| 1032 | |
| 1033 | static const struct clksel func_96m_fclk_div[] = { |
| 1034 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, |
| 1035 | { .parent = NULL }, |
| 1036 | }; |
| 1037 | |
| 1038 | static struct clk func_96m_fclk = { |
| 1039 | .name = "func_96m_fclk", |
| 1040 | .parent = &dpll_per_m2x2_ck, |
| 1041 | .clksel = func_96m_fclk_div, |
| 1042 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1043 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1044 | .ops = &clkops_null, |
| 1045 | .recalc = &omap2_clksel_recalc, |
| 1046 | .round_rate = &omap2_clksel_round_rate, |
| 1047 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1048 | }; |
| 1049 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1050 | static const struct clksel_rate div2_1to8_rates[] = { |
| 1051 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 1052 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, |
| 1053 | { .div = 0 }, |
| 1054 | }; |
| 1055 | |
| 1056 | static const struct clksel init_60m_fclk_div[] = { |
| 1057 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, |
| 1058 | { .parent = NULL }, |
| 1059 | }; |
| 1060 | |
| 1061 | static struct clk init_60m_fclk = { |
| 1062 | .name = "init_60m_fclk", |
| 1063 | .parent = &dpll_usb_m2_ck, |
| 1064 | .clksel = init_60m_fclk_div, |
| 1065 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, |
| 1066 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1067 | .ops = &clkops_null, |
| 1068 | .recalc = &omap2_clksel_recalc, |
| 1069 | .round_rate = &omap2_clksel_round_rate, |
| 1070 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1071 | }; |
| 1072 | |
| 1073 | static const struct clksel l3_div_div[] = { |
| 1074 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, |
| 1075 | { .parent = NULL }, |
| 1076 | }; |
| 1077 | |
| 1078 | static struct clk l3_div_ck = { |
| 1079 | .name = "l3_div_ck", |
| 1080 | .parent = &div_core_ck, |
Paul Walmsley | 9a47d32 | 2012-06-17 11:57:52 -0600 | [diff] [blame] | 1081 | .clkdm_name = "cm_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1082 | .clksel = l3_div_div, |
| 1083 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 1084 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, |
| 1085 | .ops = &clkops_null, |
| 1086 | .recalc = &omap2_clksel_recalc, |
| 1087 | .round_rate = &omap2_clksel_round_rate, |
| 1088 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1089 | }; |
| 1090 | |
| 1091 | static const struct clksel l4_div_div[] = { |
| 1092 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, |
| 1093 | { .parent = NULL }, |
| 1094 | }; |
| 1095 | |
| 1096 | static struct clk l4_div_ck = { |
| 1097 | .name = "l4_div_ck", |
| 1098 | .parent = &l3_div_ck, |
| 1099 | .clksel = l4_div_div, |
| 1100 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 1101 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, |
| 1102 | .ops = &clkops_null, |
| 1103 | .recalc = &omap2_clksel_recalc, |
| 1104 | .round_rate = &omap2_clksel_round_rate, |
| 1105 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1106 | }; |
| 1107 | |
| 1108 | static struct clk lp_clk_div_ck = { |
| 1109 | .name = "lp_clk_div_ck", |
| 1110 | .parent = &dpll_abe_m2x2_ck, |
| 1111 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1112 | .fixed_div = 16, |
| 1113 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1114 | }; |
| 1115 | |
| 1116 | static const struct clksel l4_wkup_clk_mux_sel[] = { |
| 1117 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 1118 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, |
| 1119 | { .parent = NULL }, |
| 1120 | }; |
| 1121 | |
| 1122 | static struct clk l4_wkup_clk_mux_ck = { |
| 1123 | .name = "l4_wkup_clk_mux_ck", |
| 1124 | .parent = &sys_clkin_ck, |
| 1125 | .clksel = l4_wkup_clk_mux_sel, |
| 1126 | .init = &omap2_init_clksel_parent, |
| 1127 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, |
| 1128 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1129 | .ops = &clkops_null, |
| 1130 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1131 | }; |
| 1132 | |
Jon Hunter | cf2a82d | 2011-10-07 00:53:09 -0600 | [diff] [blame] | 1133 | static const struct clksel_rate div2_2to1_rates[] = { |
| 1134 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, |
| 1135 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, |
| 1136 | { .div = 0 }, |
| 1137 | }; |
| 1138 | |
| 1139 | static const struct clksel ocp_abe_iclk_div[] = { |
| 1140 | { .parent = &aess_fclk, .rates = div2_2to1_rates }, |
| 1141 | { .parent = NULL }, |
| 1142 | }; |
| 1143 | |
Santosh Shilimkar | 30c9569 | 2011-12-16 16:09:12 -0800 | [diff] [blame] | 1144 | static struct clk mpu_periphclk = { |
| 1145 | .name = "mpu_periphclk", |
| 1146 | .parent = &dpll_mpu_ck, |
| 1147 | .ops = &clkops_null, |
| 1148 | .fixed_div = 2, |
| 1149 | .recalc = &omap_fixed_divisor_recalc, |
| 1150 | }; |
| 1151 | |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1152 | static struct clk ocp_abe_iclk = { |
| 1153 | .name = "ocp_abe_iclk", |
| 1154 | .parent = &aess_fclk, |
Jon Hunter | cf2a82d | 2011-10-07 00:53:09 -0600 | [diff] [blame] | 1155 | .clksel = ocp_abe_iclk_div, |
| 1156 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 1157 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1158 | .ops = &clkops_null, |
Jon Hunter | cf2a82d | 2011-10-07 00:53:09 -0600 | [diff] [blame] | 1159 | .recalc = &omap2_clksel_recalc, |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1160 | }; |
| 1161 | |
| 1162 | static struct clk per_abe_24m_fclk = { |
| 1163 | .name = "per_abe_24m_fclk", |
| 1164 | .parent = &dpll_abe_m2_ck, |
| 1165 | .ops = &clkops_null, |
| 1166 | .fixed_div = 4, |
| 1167 | .recalc = &omap_fixed_divisor_recalc, |
| 1168 | }; |
| 1169 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1170 | static const struct clksel per_abe_nc_fclk_div[] = { |
| 1171 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, |
| 1172 | { .parent = NULL }, |
| 1173 | }; |
| 1174 | |
| 1175 | static struct clk per_abe_nc_fclk = { |
| 1176 | .name = "per_abe_nc_fclk", |
| 1177 | .parent = &dpll_abe_m2_ck, |
| 1178 | .clksel = per_abe_nc_fclk_div, |
| 1179 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1180 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1181 | .ops = &clkops_null, |
| 1182 | .recalc = &omap2_clksel_recalc, |
| 1183 | .round_rate = &omap2_clksel_round_rate, |
| 1184 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1185 | }; |
| 1186 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1187 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
| 1188 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1189 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1190 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1191 | { .parent = NULL }, |
| 1192 | }; |
| 1193 | |
| 1194 | static struct clk pmd_stm_clock_mux_ck = { |
| 1195 | .name = "pmd_stm_clock_mux_ck", |
| 1196 | .parent = &sys_clkin_ck, |
| 1197 | .ops = &clkops_null, |
| 1198 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1199 | }; |
| 1200 | |
| 1201 | static struct clk pmd_trace_clk_mux_ck = { |
| 1202 | .name = "pmd_trace_clk_mux_ck", |
| 1203 | .parent = &sys_clkin_ck, |
| 1204 | .ops = &clkops_null, |
| 1205 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1206 | }; |
| 1207 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1208 | static const struct clksel syc_clk_div_div[] = { |
| 1209 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, |
| 1210 | { .parent = NULL }, |
| 1211 | }; |
| 1212 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1213 | static struct clk syc_clk_div_ck = { |
| 1214 | .name = "syc_clk_div_ck", |
| 1215 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1216 | .clksel = syc_clk_div_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1217 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, |
| 1218 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1219 | .ops = &clkops_null, |
| 1220 | .recalc = &omap2_clksel_recalc, |
| 1221 | .round_rate = &omap2_clksel_round_rate, |
| 1222 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1223 | }; |
| 1224 | |
| 1225 | /* Leaf clocks controlled by modules */ |
| 1226 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1227 | static struct clk aes1_fck = { |
| 1228 | .name = "aes1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1229 | .ops = &clkops_omap2_dflt, |
| 1230 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, |
| 1231 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1232 | .clkdm_name = "l4_secure_clkdm", |
| 1233 | .parent = &l3_div_ck, |
| 1234 | .recalc = &followparent_recalc, |
| 1235 | }; |
| 1236 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1237 | static struct clk aes2_fck = { |
| 1238 | .name = "aes2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1239 | .ops = &clkops_omap2_dflt, |
| 1240 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, |
| 1241 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1242 | .clkdm_name = "l4_secure_clkdm", |
| 1243 | .parent = &l3_div_ck, |
| 1244 | .recalc = &followparent_recalc, |
| 1245 | }; |
| 1246 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1247 | static struct clk aess_fck = { |
| 1248 | .name = "aess_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1249 | .ops = &clkops_omap2_dflt, |
| 1250 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 1251 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1252 | .clkdm_name = "abe_clkdm", |
| 1253 | .parent = &aess_fclk, |
| 1254 | .recalc = &followparent_recalc, |
| 1255 | }; |
| 1256 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1257 | static struct clk bandgap_fclk = { |
| 1258 | .name = "bandgap_fclk", |
| 1259 | .ops = &clkops_omap2_dflt, |
| 1260 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, |
| 1261 | .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, |
| 1262 | .clkdm_name = "l4_wkup_clkdm", |
| 1263 | .parent = &sys_32k_ck, |
| 1264 | .recalc = &followparent_recalc, |
| 1265 | }; |
| 1266 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1267 | static struct clk des3des_fck = { |
| 1268 | .name = "des3des_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1269 | .ops = &clkops_omap2_dflt, |
| 1270 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, |
| 1271 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1272 | .clkdm_name = "l4_secure_clkdm", |
| 1273 | .parent = &l4_div_ck, |
| 1274 | .recalc = &followparent_recalc, |
| 1275 | }; |
| 1276 | |
| 1277 | static const struct clksel dmic_sync_mux_sel[] = { |
| 1278 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, |
| 1279 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, |
| 1280 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, |
| 1281 | { .parent = NULL }, |
| 1282 | }; |
| 1283 | |
| 1284 | static struct clk dmic_sync_mux_ck = { |
| 1285 | .name = "dmic_sync_mux_ck", |
| 1286 | .parent = &abe_24m_fclk, |
| 1287 | .clksel = dmic_sync_mux_sel, |
| 1288 | .init = &omap2_init_clksel_parent, |
| 1289 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1290 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1291 | .ops = &clkops_null, |
| 1292 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1293 | }; |
| 1294 | |
| 1295 | static const struct clksel func_dmic_abe_gfclk_sel[] = { |
| 1296 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, |
| 1297 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1298 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1299 | { .parent = NULL }, |
| 1300 | }; |
| 1301 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1302 | /* Merged func_dmic_abe_gfclk into dmic */ |
| 1303 | static struct clk dmic_fck = { |
| 1304 | .name = "dmic_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1305 | .parent = &dmic_sync_mux_ck, |
| 1306 | .clksel = func_dmic_abe_gfclk_sel, |
| 1307 | .init = &omap2_init_clksel_parent, |
| 1308 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1309 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1310 | .ops = &clkops_omap2_dflt, |
| 1311 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1312 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1313 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1314 | .clkdm_name = "abe_clkdm", |
| 1315 | }; |
| 1316 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1317 | static struct clk dsp_fck = { |
| 1318 | .name = "dsp_fck", |
| 1319 | .ops = &clkops_omap2_dflt, |
| 1320 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, |
| 1321 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1322 | .clkdm_name = "tesla_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1323 | .parent = &dpll_iva_m4x2_ck, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1324 | .recalc = &followparent_recalc, |
| 1325 | }; |
| 1326 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1327 | static struct clk dss_sys_clk = { |
| 1328 | .name = "dss_sys_clk", |
| 1329 | .ops = &clkops_omap2_dflt, |
| 1330 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1331 | .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, |
| 1332 | .clkdm_name = "l3_dss_clkdm", |
| 1333 | .parent = &syc_clk_div_ck, |
| 1334 | .recalc = &followparent_recalc, |
| 1335 | }; |
| 1336 | |
| 1337 | static struct clk dss_tv_clk = { |
| 1338 | .name = "dss_tv_clk", |
| 1339 | .ops = &clkops_omap2_dflt, |
| 1340 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1341 | .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, |
| 1342 | .clkdm_name = "l3_dss_clkdm", |
| 1343 | .parent = &extalt_clkin_ck, |
| 1344 | .recalc = &followparent_recalc, |
| 1345 | }; |
| 1346 | |
| 1347 | static struct clk dss_dss_clk = { |
| 1348 | .name = "dss_dss_clk", |
| 1349 | .ops = &clkops_omap2_dflt, |
| 1350 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1351 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, |
| 1352 | .clkdm_name = "l3_dss_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1353 | .parent = &dpll_per_m5x2_ck, |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1354 | .recalc = &followparent_recalc, |
| 1355 | }; |
| 1356 | |
Rajendra Nayak | 257d643 | 2011-07-02 08:00:24 +0530 | [diff] [blame] | 1357 | static const struct clksel_rate div3_8to32_rates[] = { |
Paul Walmsley | 52a3a4d | 2011-10-07 00:53:08 -0600 | [diff] [blame] | 1358 | { .div = 8, .val = 0, .flags = RATE_IN_4460 }, |
| 1359 | { .div = 16, .val = 1, .flags = RATE_IN_4460 }, |
| 1360 | { .div = 32, .val = 2, .flags = RATE_IN_4460 }, |
Rajendra Nayak | 257d643 | 2011-07-02 08:00:24 +0530 | [diff] [blame] | 1361 | { .div = 0 }, |
| 1362 | }; |
| 1363 | |
| 1364 | static const struct clksel div_ts_div[] = { |
| 1365 | { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, |
| 1366 | { .parent = NULL }, |
| 1367 | }; |
| 1368 | |
| 1369 | static struct clk div_ts_ck = { |
| 1370 | .name = "div_ts_ck", |
| 1371 | .parent = &l4_wkup_clk_mux_ck, |
| 1372 | .clksel = div_ts_div, |
| 1373 | .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, |
| 1374 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, |
| 1375 | .ops = &clkops_null, |
| 1376 | .recalc = &omap2_clksel_recalc, |
| 1377 | .round_rate = &omap2_clksel_round_rate, |
| 1378 | .set_rate = &omap2_clksel_set_rate, |
| 1379 | }; |
| 1380 | |
| 1381 | static struct clk bandgap_ts_fclk = { |
| 1382 | .name = "bandgap_ts_fclk", |
| 1383 | .ops = &clkops_omap2_dflt, |
| 1384 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, |
| 1385 | .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, |
| 1386 | .clkdm_name = "l4_wkup_clkdm", |
| 1387 | .parent = &div_ts_ck, |
| 1388 | .recalc = &followparent_recalc, |
| 1389 | }; |
| 1390 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1391 | static struct clk dss_48mhz_clk = { |
| 1392 | .name = "dss_48mhz_clk", |
| 1393 | .ops = &clkops_omap2_dflt, |
| 1394 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1395 | .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, |
| 1396 | .clkdm_name = "l3_dss_clkdm", |
| 1397 | .parent = &func_48mc_fclk, |
| 1398 | .recalc = &followparent_recalc, |
| 1399 | }; |
| 1400 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1401 | static struct clk dss_fck = { |
| 1402 | .name = "dss_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1403 | .ops = &clkops_omap2_dflt, |
| 1404 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1405 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1406 | .clkdm_name = "l3_dss_clkdm", |
| 1407 | .parent = &l3_div_ck, |
| 1408 | .recalc = &followparent_recalc, |
| 1409 | }; |
| 1410 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1411 | static struct clk efuse_ctrl_cust_fck = { |
| 1412 | .name = "efuse_ctrl_cust_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1413 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1414 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
| 1415 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1416 | .clkdm_name = "l4_cefuse_clkdm", |
| 1417 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1418 | .recalc = &followparent_recalc, |
| 1419 | }; |
| 1420 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1421 | static struct clk emif1_fck = { |
| 1422 | .name = "emif1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1423 | .ops = &clkops_omap2_dflt, |
| 1424 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, |
| 1425 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 090830b | 2010-06-16 19:01:33 +0300 | [diff] [blame] | 1426 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1427 | .clkdm_name = "l3_emif_clkdm", |
| 1428 | .parent = &ddrphy_ck, |
| 1429 | .recalc = &followparent_recalc, |
| 1430 | }; |
| 1431 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1432 | static struct clk emif2_fck = { |
| 1433 | .name = "emif2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1434 | .ops = &clkops_omap2_dflt, |
| 1435 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, |
| 1436 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 090830b | 2010-06-16 19:01:33 +0300 | [diff] [blame] | 1437 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1438 | .clkdm_name = "l3_emif_clkdm", |
| 1439 | .parent = &ddrphy_ck, |
| 1440 | .recalc = &followparent_recalc, |
| 1441 | }; |
| 1442 | |
| 1443 | static const struct clksel fdif_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1444 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1445 | { .parent = NULL }, |
| 1446 | }; |
| 1447 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1448 | /* Merged fdif_fclk into fdif */ |
| 1449 | static struct clk fdif_fck = { |
| 1450 | .name = "fdif_fck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1451 | .parent = &dpll_per_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1452 | .clksel = fdif_fclk_div, |
| 1453 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1454 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, |
| 1455 | .ops = &clkops_omap2_dflt, |
| 1456 | .recalc = &omap2_clksel_recalc, |
| 1457 | .round_rate = &omap2_clksel_round_rate, |
| 1458 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1459 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1460 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1461 | .clkdm_name = "iss_clkdm", |
| 1462 | }; |
| 1463 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1464 | static struct clk fpka_fck = { |
| 1465 | .name = "fpka_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1466 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1467 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1468 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1469 | .clkdm_name = "l4_secure_clkdm", |
| 1470 | .parent = &l4_div_ck, |
| 1471 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1472 | }; |
| 1473 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1474 | static struct clk gpio1_dbclk = { |
| 1475 | .name = "gpio1_dbclk", |
| 1476 | .ops = &clkops_omap2_dflt, |
| 1477 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
| 1478 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1479 | .clkdm_name = "l4_wkup_clkdm", |
| 1480 | .parent = &sys_32k_ck, |
| 1481 | .recalc = &followparent_recalc, |
| 1482 | }; |
| 1483 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1484 | static struct clk gpio1_ick = { |
| 1485 | .name = "gpio1_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1486 | .ops = &clkops_omap2_dflt, |
| 1487 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
| 1488 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1489 | .clkdm_name = "l4_wkup_clkdm", |
| 1490 | .parent = &l4_wkup_clk_mux_ck, |
| 1491 | .recalc = &followparent_recalc, |
| 1492 | }; |
| 1493 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1494 | static struct clk gpio2_dbclk = { |
| 1495 | .name = "gpio2_dbclk", |
| 1496 | .ops = &clkops_omap2_dflt, |
| 1497 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
| 1498 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1499 | .clkdm_name = "l4_per_clkdm", |
| 1500 | .parent = &sys_32k_ck, |
| 1501 | .recalc = &followparent_recalc, |
| 1502 | }; |
| 1503 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1504 | static struct clk gpio2_ick = { |
| 1505 | .name = "gpio2_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1506 | .ops = &clkops_omap2_dflt, |
| 1507 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
| 1508 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1509 | .clkdm_name = "l4_per_clkdm", |
| 1510 | .parent = &l4_div_ck, |
| 1511 | .recalc = &followparent_recalc, |
| 1512 | }; |
| 1513 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1514 | static struct clk gpio3_dbclk = { |
| 1515 | .name = "gpio3_dbclk", |
| 1516 | .ops = &clkops_omap2_dflt, |
| 1517 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
| 1518 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1519 | .clkdm_name = "l4_per_clkdm", |
| 1520 | .parent = &sys_32k_ck, |
| 1521 | .recalc = &followparent_recalc, |
| 1522 | }; |
| 1523 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1524 | static struct clk gpio3_ick = { |
| 1525 | .name = "gpio3_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1526 | .ops = &clkops_omap2_dflt, |
| 1527 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
| 1528 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1529 | .clkdm_name = "l4_per_clkdm", |
| 1530 | .parent = &l4_div_ck, |
| 1531 | .recalc = &followparent_recalc, |
| 1532 | }; |
| 1533 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1534 | static struct clk gpio4_dbclk = { |
| 1535 | .name = "gpio4_dbclk", |
| 1536 | .ops = &clkops_omap2_dflt, |
| 1537 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
| 1538 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1539 | .clkdm_name = "l4_per_clkdm", |
| 1540 | .parent = &sys_32k_ck, |
| 1541 | .recalc = &followparent_recalc, |
| 1542 | }; |
| 1543 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1544 | static struct clk gpio4_ick = { |
| 1545 | .name = "gpio4_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1546 | .ops = &clkops_omap2_dflt, |
| 1547 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
| 1548 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1549 | .clkdm_name = "l4_per_clkdm", |
| 1550 | .parent = &l4_div_ck, |
| 1551 | .recalc = &followparent_recalc, |
| 1552 | }; |
| 1553 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1554 | static struct clk gpio5_dbclk = { |
| 1555 | .name = "gpio5_dbclk", |
| 1556 | .ops = &clkops_omap2_dflt, |
| 1557 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
| 1558 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1559 | .clkdm_name = "l4_per_clkdm", |
| 1560 | .parent = &sys_32k_ck, |
| 1561 | .recalc = &followparent_recalc, |
| 1562 | }; |
| 1563 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1564 | static struct clk gpio5_ick = { |
| 1565 | .name = "gpio5_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1566 | .ops = &clkops_omap2_dflt, |
| 1567 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
| 1568 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1569 | .clkdm_name = "l4_per_clkdm", |
| 1570 | .parent = &l4_div_ck, |
| 1571 | .recalc = &followparent_recalc, |
| 1572 | }; |
| 1573 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1574 | static struct clk gpio6_dbclk = { |
| 1575 | .name = "gpio6_dbclk", |
| 1576 | .ops = &clkops_omap2_dflt, |
| 1577 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
| 1578 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1579 | .clkdm_name = "l4_per_clkdm", |
| 1580 | .parent = &sys_32k_ck, |
| 1581 | .recalc = &followparent_recalc, |
| 1582 | }; |
| 1583 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1584 | static struct clk gpio6_ick = { |
| 1585 | .name = "gpio6_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1586 | .ops = &clkops_omap2_dflt, |
| 1587 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
| 1588 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1589 | .clkdm_name = "l4_per_clkdm", |
| 1590 | .parent = &l4_div_ck, |
| 1591 | .recalc = &followparent_recalc, |
| 1592 | }; |
| 1593 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1594 | static struct clk gpmc_ick = { |
| 1595 | .name = "gpmc_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1596 | .ops = &clkops_omap2_dflt, |
| 1597 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, |
| 1598 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 93cac2a | 2011-07-09 20:42:59 -0600 | [diff] [blame] | 1599 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1600 | .clkdm_name = "l3_2_clkdm", |
| 1601 | .parent = &l3_div_ck, |
| 1602 | .recalc = &followparent_recalc, |
| 1603 | }; |
| 1604 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1605 | static const struct clksel sgx_clk_mux_sel[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1606 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
| 1607 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1608 | { .parent = NULL }, |
| 1609 | }; |
| 1610 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1611 | /* Merged sgx_clk_mux into gpu */ |
| 1612 | static struct clk gpu_fck = { |
| 1613 | .name = "gpu_fck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1614 | .parent = &dpll_core_m7x2_ck, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1615 | .clksel = sgx_clk_mux_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1616 | .init = &omap2_init_clksel_parent, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1617 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
| 1618 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1619 | .ops = &clkops_omap2_dflt, |
| 1620 | .recalc = &omap2_clksel_recalc, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1621 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1622 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1623 | .clkdm_name = "l3_gfx_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1624 | }; |
| 1625 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1626 | static struct clk hdq1w_fck = { |
| 1627 | .name = "hdq1w_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1628 | .ops = &clkops_omap2_dflt, |
| 1629 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, |
| 1630 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1631 | .clkdm_name = "l4_per_clkdm", |
| 1632 | .parent = &func_12m_fclk, |
| 1633 | .recalc = &followparent_recalc, |
| 1634 | }; |
| 1635 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1636 | static const struct clksel hsi_fclk_div[] = { |
| 1637 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, |
| 1638 | { .parent = NULL }, |
| 1639 | }; |
| 1640 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1641 | /* Merged hsi_fclk into hsi */ |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1642 | static struct clk hsi_fck = { |
| 1643 | .name = "hsi_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1644 | .parent = &dpll_per_m2x2_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1645 | .clksel = hsi_fclk_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1646 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| 1647 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, |
| 1648 | .ops = &clkops_omap2_dflt, |
| 1649 | .recalc = &omap2_clksel_recalc, |
| 1650 | .round_rate = &omap2_clksel_round_rate, |
| 1651 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1652 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| 1653 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1654 | .clkdm_name = "l3_init_clkdm", |
| 1655 | }; |
| 1656 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1657 | static struct clk i2c1_fck = { |
| 1658 | .name = "i2c1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1659 | .ops = &clkops_omap2_dflt, |
| 1660 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
| 1661 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1662 | .clkdm_name = "l4_per_clkdm", |
| 1663 | .parent = &func_96m_fclk, |
| 1664 | .recalc = &followparent_recalc, |
| 1665 | }; |
| 1666 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1667 | static struct clk i2c2_fck = { |
| 1668 | .name = "i2c2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1669 | .ops = &clkops_omap2_dflt, |
| 1670 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
| 1671 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1672 | .clkdm_name = "l4_per_clkdm", |
| 1673 | .parent = &func_96m_fclk, |
| 1674 | .recalc = &followparent_recalc, |
| 1675 | }; |
| 1676 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1677 | static struct clk i2c3_fck = { |
| 1678 | .name = "i2c3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1679 | .ops = &clkops_omap2_dflt, |
| 1680 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
| 1681 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1682 | .clkdm_name = "l4_per_clkdm", |
| 1683 | .parent = &func_96m_fclk, |
| 1684 | .recalc = &followparent_recalc, |
| 1685 | }; |
| 1686 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1687 | static struct clk i2c4_fck = { |
| 1688 | .name = "i2c4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1689 | .ops = &clkops_omap2_dflt, |
| 1690 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
| 1691 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1692 | .clkdm_name = "l4_per_clkdm", |
| 1693 | .parent = &func_96m_fclk, |
| 1694 | .recalc = &followparent_recalc, |
| 1695 | }; |
| 1696 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1697 | static struct clk ipu_fck = { |
| 1698 | .name = "ipu_fck", |
| 1699 | .ops = &clkops_omap2_dflt, |
| 1700 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, |
| 1701 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1702 | .clkdm_name = "ducati_clkdm", |
| 1703 | .parent = &ducati_clk_mux_ck, |
| 1704 | .recalc = &followparent_recalc, |
| 1705 | }; |
| 1706 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1707 | static struct clk iss_ctrlclk = { |
| 1708 | .name = "iss_ctrlclk", |
| 1709 | .ops = &clkops_omap2_dflt, |
| 1710 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
| 1711 | .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, |
| 1712 | .clkdm_name = "iss_clkdm", |
| 1713 | .parent = &func_96m_fclk, |
| 1714 | .recalc = &followparent_recalc, |
| 1715 | }; |
| 1716 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1717 | static struct clk iss_fck = { |
| 1718 | .name = "iss_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1719 | .ops = &clkops_omap2_dflt, |
| 1720 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
| 1721 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1722 | .clkdm_name = "iss_clkdm", |
| 1723 | .parent = &ducati_clk_mux_ck, |
| 1724 | .recalc = &followparent_recalc, |
| 1725 | }; |
| 1726 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1727 | static struct clk iva_fck = { |
| 1728 | .name = "iva_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1729 | .ops = &clkops_omap2_dflt, |
| 1730 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, |
| 1731 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1732 | .clkdm_name = "ivahd_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1733 | .parent = &dpll_iva_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1734 | .recalc = &followparent_recalc, |
| 1735 | }; |
| 1736 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1737 | static struct clk kbd_fck = { |
| 1738 | .name = "kbd_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1739 | .ops = &clkops_omap2_dflt, |
| 1740 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, |
| 1741 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1742 | .clkdm_name = "l4_wkup_clkdm", |
| 1743 | .parent = &sys_32k_ck, |
| 1744 | .recalc = &followparent_recalc, |
| 1745 | }; |
| 1746 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1747 | static struct clk l3_instr_ick = { |
| 1748 | .name = "l3_instr_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1749 | .ops = &clkops_omap2_dflt, |
| 1750 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, |
| 1751 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 1752 | .flags = ENABLE_ON_INIT, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 1753 | .clkdm_name = "l3_instr_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1754 | .parent = &l3_div_ck, |
| 1755 | .recalc = &followparent_recalc, |
| 1756 | }; |
| 1757 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1758 | static struct clk l3_main_3_ick = { |
| 1759 | .name = "l3_main_3_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1760 | .ops = &clkops_omap2_dflt, |
| 1761 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, |
| 1762 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 1763 | .flags = ENABLE_ON_INIT, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 1764 | .clkdm_name = "l3_instr_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1765 | .parent = &l3_div_ck, |
| 1766 | .recalc = &followparent_recalc, |
| 1767 | }; |
| 1768 | |
| 1769 | static struct clk mcasp_sync_mux_ck = { |
| 1770 | .name = "mcasp_sync_mux_ck", |
| 1771 | .parent = &abe_24m_fclk, |
| 1772 | .clksel = dmic_sync_mux_sel, |
| 1773 | .init = &omap2_init_clksel_parent, |
| 1774 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1775 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1776 | .ops = &clkops_null, |
| 1777 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1778 | }; |
| 1779 | |
| 1780 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { |
| 1781 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, |
| 1782 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1783 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1784 | { .parent = NULL }, |
| 1785 | }; |
| 1786 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1787 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
| 1788 | static struct clk mcasp_fck = { |
| 1789 | .name = "mcasp_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1790 | .parent = &mcasp_sync_mux_ck, |
| 1791 | .clksel = func_mcasp_abe_gfclk_sel, |
| 1792 | .init = &omap2_init_clksel_parent, |
| 1793 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1794 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1795 | .ops = &clkops_omap2_dflt, |
| 1796 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1797 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1798 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1799 | .clkdm_name = "abe_clkdm", |
| 1800 | }; |
| 1801 | |
| 1802 | static struct clk mcbsp1_sync_mux_ck = { |
| 1803 | .name = "mcbsp1_sync_mux_ck", |
| 1804 | .parent = &abe_24m_fclk, |
| 1805 | .clksel = dmic_sync_mux_sel, |
| 1806 | .init = &omap2_init_clksel_parent, |
| 1807 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1808 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1809 | .ops = &clkops_null, |
| 1810 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1811 | }; |
| 1812 | |
| 1813 | static const struct clksel func_mcbsp1_gfclk_sel[] = { |
| 1814 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, |
| 1815 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1816 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1817 | { .parent = NULL }, |
| 1818 | }; |
| 1819 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1820 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
| 1821 | static struct clk mcbsp1_fck = { |
| 1822 | .name = "mcbsp1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1823 | .parent = &mcbsp1_sync_mux_ck, |
| 1824 | .clksel = func_mcbsp1_gfclk_sel, |
| 1825 | .init = &omap2_init_clksel_parent, |
| 1826 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1827 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1828 | .ops = &clkops_omap2_dflt, |
| 1829 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1830 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1831 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1832 | .clkdm_name = "abe_clkdm", |
| 1833 | }; |
| 1834 | |
| 1835 | static struct clk mcbsp2_sync_mux_ck = { |
| 1836 | .name = "mcbsp2_sync_mux_ck", |
| 1837 | .parent = &abe_24m_fclk, |
| 1838 | .clksel = dmic_sync_mux_sel, |
| 1839 | .init = &omap2_init_clksel_parent, |
| 1840 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1841 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1842 | .ops = &clkops_null, |
| 1843 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1844 | }; |
| 1845 | |
| 1846 | static const struct clksel func_mcbsp2_gfclk_sel[] = { |
| 1847 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, |
| 1848 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1849 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1850 | { .parent = NULL }, |
| 1851 | }; |
| 1852 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1853 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
| 1854 | static struct clk mcbsp2_fck = { |
| 1855 | .name = "mcbsp2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1856 | .parent = &mcbsp2_sync_mux_ck, |
| 1857 | .clksel = func_mcbsp2_gfclk_sel, |
| 1858 | .init = &omap2_init_clksel_parent, |
| 1859 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1860 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1861 | .ops = &clkops_omap2_dflt, |
| 1862 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1863 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1864 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1865 | .clkdm_name = "abe_clkdm", |
| 1866 | }; |
| 1867 | |
| 1868 | static struct clk mcbsp3_sync_mux_ck = { |
| 1869 | .name = "mcbsp3_sync_mux_ck", |
| 1870 | .parent = &abe_24m_fclk, |
| 1871 | .clksel = dmic_sync_mux_sel, |
| 1872 | .init = &omap2_init_clksel_parent, |
| 1873 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1874 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1875 | .ops = &clkops_null, |
| 1876 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1877 | }; |
| 1878 | |
| 1879 | static const struct clksel func_mcbsp3_gfclk_sel[] = { |
| 1880 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, |
| 1881 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1882 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1883 | { .parent = NULL }, |
| 1884 | }; |
| 1885 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1886 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
| 1887 | static struct clk mcbsp3_fck = { |
| 1888 | .name = "mcbsp3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1889 | .parent = &mcbsp3_sync_mux_ck, |
| 1890 | .clksel = func_mcbsp3_gfclk_sel, |
| 1891 | .init = &omap2_init_clksel_parent, |
| 1892 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1893 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1894 | .ops = &clkops_omap2_dflt, |
| 1895 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1896 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1897 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1898 | .clkdm_name = "abe_clkdm", |
| 1899 | }; |
| 1900 | |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1901 | static const struct clksel mcbsp4_sync_mux_sel[] = { |
| 1902 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, |
| 1903 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, |
| 1904 | { .parent = NULL }, |
| 1905 | }; |
| 1906 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1907 | static struct clk mcbsp4_sync_mux_ck = { |
| 1908 | .name = "mcbsp4_sync_mux_ck", |
| 1909 | .parent = &func_96m_fclk, |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1910 | .clksel = mcbsp4_sync_mux_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1911 | .init = &omap2_init_clksel_parent, |
| 1912 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 1913 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1914 | .ops = &clkops_null, |
| 1915 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1916 | }; |
| 1917 | |
| 1918 | static const struct clksel per_mcbsp4_gfclk_sel[] = { |
| 1919 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, |
| 1920 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1921 | { .parent = NULL }, |
| 1922 | }; |
| 1923 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1924 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
| 1925 | static struct clk mcbsp4_fck = { |
| 1926 | .name = "mcbsp4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1927 | .parent = &mcbsp4_sync_mux_ck, |
| 1928 | .clksel = per_mcbsp4_gfclk_sel, |
| 1929 | .init = &omap2_init_clksel_parent, |
| 1930 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 1931 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, |
| 1932 | .ops = &clkops_omap2_dflt, |
| 1933 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1934 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 1935 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1936 | .clkdm_name = "l4_per_clkdm", |
| 1937 | }; |
| 1938 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1939 | static struct clk mcpdm_fck = { |
| 1940 | .name = "mcpdm_fck", |
| 1941 | .ops = &clkops_omap2_dflt, |
| 1942 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, |
| 1943 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1944 | .clkdm_name = "abe_clkdm", |
| 1945 | .parent = &pad_clks_ck, |
| 1946 | .recalc = &followparent_recalc, |
| 1947 | }; |
| 1948 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1949 | static struct clk mcspi1_fck = { |
| 1950 | .name = "mcspi1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1951 | .ops = &clkops_omap2_dflt, |
| 1952 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, |
| 1953 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1954 | .clkdm_name = "l4_per_clkdm", |
| 1955 | .parent = &func_48m_fclk, |
| 1956 | .recalc = &followparent_recalc, |
| 1957 | }; |
| 1958 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1959 | static struct clk mcspi2_fck = { |
| 1960 | .name = "mcspi2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1961 | .ops = &clkops_omap2_dflt, |
| 1962 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, |
| 1963 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1964 | .clkdm_name = "l4_per_clkdm", |
| 1965 | .parent = &func_48m_fclk, |
| 1966 | .recalc = &followparent_recalc, |
| 1967 | }; |
| 1968 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1969 | static struct clk mcspi3_fck = { |
| 1970 | .name = "mcspi3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1971 | .ops = &clkops_omap2_dflt, |
| 1972 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, |
| 1973 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1974 | .clkdm_name = "l4_per_clkdm", |
| 1975 | .parent = &func_48m_fclk, |
| 1976 | .recalc = &followparent_recalc, |
| 1977 | }; |
| 1978 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1979 | static struct clk mcspi4_fck = { |
| 1980 | .name = "mcspi4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1981 | .ops = &clkops_omap2_dflt, |
| 1982 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, |
| 1983 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1984 | .clkdm_name = "l4_per_clkdm", |
| 1985 | .parent = &func_48m_fclk, |
| 1986 | .recalc = &followparent_recalc, |
| 1987 | }; |
| 1988 | |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1989 | static const struct clksel hsmmc1_fclk_sel[] = { |
| 1990 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, |
| 1991 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, |
| 1992 | { .parent = NULL }, |
| 1993 | }; |
| 1994 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1995 | /* Merged hsmmc1_fclk into mmc1 */ |
| 1996 | static struct clk mmc1_fck = { |
| 1997 | .name = "mmc1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1998 | .parent = &func_64m_fclk, |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 1999 | .clksel = hsmmc1_fclk_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2000 | .init = &omap2_init_clksel_parent, |
| 2001 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
| 2002 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2003 | .ops = &clkops_omap2_dflt, |
| 2004 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2005 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
| 2006 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2007 | .clkdm_name = "l3_init_clkdm", |
| 2008 | }; |
| 2009 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2010 | /* Merged hsmmc2_fclk into mmc2 */ |
| 2011 | static struct clk mmc2_fck = { |
| 2012 | .name = "mmc2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2013 | .parent = &func_64m_fclk, |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 2014 | .clksel = hsmmc1_fclk_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2015 | .init = &omap2_init_clksel_parent, |
| 2016 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
| 2017 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2018 | .ops = &clkops_omap2_dflt, |
| 2019 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2020 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
| 2021 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2022 | .clkdm_name = "l3_init_clkdm", |
| 2023 | }; |
| 2024 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2025 | static struct clk mmc3_fck = { |
| 2026 | .name = "mmc3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2027 | .ops = &clkops_omap2_dflt, |
| 2028 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, |
| 2029 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2030 | .clkdm_name = "l4_per_clkdm", |
| 2031 | .parent = &func_48m_fclk, |
| 2032 | .recalc = &followparent_recalc, |
| 2033 | }; |
| 2034 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2035 | static struct clk mmc4_fck = { |
| 2036 | .name = "mmc4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2037 | .ops = &clkops_omap2_dflt, |
| 2038 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, |
| 2039 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2040 | .clkdm_name = "l4_per_clkdm", |
| 2041 | .parent = &func_48m_fclk, |
| 2042 | .recalc = &followparent_recalc, |
| 2043 | }; |
| 2044 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2045 | static struct clk mmc5_fck = { |
| 2046 | .name = "mmc5_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2047 | .ops = &clkops_omap2_dflt, |
| 2048 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, |
| 2049 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2050 | .clkdm_name = "l4_per_clkdm", |
| 2051 | .parent = &func_48m_fclk, |
| 2052 | .recalc = &followparent_recalc, |
| 2053 | }; |
| 2054 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2055 | static struct clk ocp2scp_usb_phy_phy_48m = { |
| 2056 | .name = "ocp2scp_usb_phy_phy_48m", |
| 2057 | .ops = &clkops_omap2_dflt, |
| 2058 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| 2059 | .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, |
| 2060 | .clkdm_name = "l3_init_clkdm", |
| 2061 | .parent = &func_48m_fclk, |
| 2062 | .recalc = &followparent_recalc, |
| 2063 | }; |
| 2064 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2065 | static struct clk ocp2scp_usb_phy_ick = { |
| 2066 | .name = "ocp2scp_usb_phy_ick", |
| 2067 | .ops = &clkops_omap2_dflt, |
| 2068 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| 2069 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2070 | .clkdm_name = "l3_init_clkdm", |
| 2071 | .parent = &l4_div_ck, |
| 2072 | .recalc = &followparent_recalc, |
| 2073 | }; |
| 2074 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2075 | static struct clk ocp_wp_noc_ick = { |
| 2076 | .name = "ocp_wp_noc_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2077 | .ops = &clkops_omap2_dflt, |
| 2078 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 2079 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 2080 | .flags = ENABLE_ON_INIT, |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 2081 | .clkdm_name = "l3_instr_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2082 | .parent = &l3_div_ck, |
| 2083 | .recalc = &followparent_recalc, |
| 2084 | }; |
| 2085 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2086 | static struct clk rng_ick = { |
| 2087 | .name = "rng_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2088 | .ops = &clkops_omap2_dflt, |
| 2089 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, |
| 2090 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2091 | .clkdm_name = "l4_secure_clkdm", |
| 2092 | .parent = &l4_div_ck, |
| 2093 | .recalc = &followparent_recalc, |
| 2094 | }; |
| 2095 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2096 | static struct clk sha2md5_fck = { |
| 2097 | .name = "sha2md5_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2098 | .ops = &clkops_omap2_dflt, |
| 2099 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, |
| 2100 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2101 | .clkdm_name = "l4_secure_clkdm", |
| 2102 | .parent = &l3_div_ck, |
| 2103 | .recalc = &followparent_recalc, |
| 2104 | }; |
| 2105 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2106 | static struct clk sl2if_ick = { |
| 2107 | .name = "sl2if_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2108 | .ops = &clkops_omap2_dflt, |
| 2109 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, |
| 2110 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2111 | .clkdm_name = "ivahd_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2112 | .parent = &dpll_iva_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2113 | .recalc = &followparent_recalc, |
| 2114 | }; |
| 2115 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2116 | static struct clk slimbus1_fclk_1 = { |
| 2117 | .name = "slimbus1_fclk_1", |
| 2118 | .ops = &clkops_omap2_dflt, |
| 2119 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2120 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, |
| 2121 | .clkdm_name = "abe_clkdm", |
| 2122 | .parent = &func_24m_clk, |
| 2123 | .recalc = &followparent_recalc, |
| 2124 | }; |
| 2125 | |
| 2126 | static struct clk slimbus1_fclk_0 = { |
| 2127 | .name = "slimbus1_fclk_0", |
| 2128 | .ops = &clkops_omap2_dflt, |
| 2129 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2130 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, |
| 2131 | .clkdm_name = "abe_clkdm", |
| 2132 | .parent = &abe_24m_fclk, |
| 2133 | .recalc = &followparent_recalc, |
| 2134 | }; |
| 2135 | |
| 2136 | static struct clk slimbus1_fclk_2 = { |
| 2137 | .name = "slimbus1_fclk_2", |
| 2138 | .ops = &clkops_omap2_dflt, |
| 2139 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2140 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, |
| 2141 | .clkdm_name = "abe_clkdm", |
| 2142 | .parent = &pad_clks_ck, |
| 2143 | .recalc = &followparent_recalc, |
| 2144 | }; |
| 2145 | |
| 2146 | static struct clk slimbus1_slimbus_clk = { |
| 2147 | .name = "slimbus1_slimbus_clk", |
| 2148 | .ops = &clkops_omap2_dflt, |
| 2149 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2150 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, |
| 2151 | .clkdm_name = "abe_clkdm", |
| 2152 | .parent = &slimbus_clk, |
| 2153 | .recalc = &followparent_recalc, |
| 2154 | }; |
| 2155 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2156 | static struct clk slimbus1_fck = { |
| 2157 | .name = "slimbus1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2158 | .ops = &clkops_omap2_dflt, |
| 2159 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2160 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2161 | .clkdm_name = "abe_clkdm", |
| 2162 | .parent = &ocp_abe_iclk, |
| 2163 | .recalc = &followparent_recalc, |
| 2164 | }; |
| 2165 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2166 | static struct clk slimbus2_fclk_1 = { |
| 2167 | .name = "slimbus2_fclk_1", |
| 2168 | .ops = &clkops_omap2_dflt, |
| 2169 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2170 | .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, |
| 2171 | .clkdm_name = "l4_per_clkdm", |
| 2172 | .parent = &per_abe_24m_fclk, |
| 2173 | .recalc = &followparent_recalc, |
| 2174 | }; |
| 2175 | |
| 2176 | static struct clk slimbus2_fclk_0 = { |
| 2177 | .name = "slimbus2_fclk_0", |
| 2178 | .ops = &clkops_omap2_dflt, |
| 2179 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2180 | .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, |
| 2181 | .clkdm_name = "l4_per_clkdm", |
| 2182 | .parent = &func_24mc_fclk, |
| 2183 | .recalc = &followparent_recalc, |
| 2184 | }; |
| 2185 | |
| 2186 | static struct clk slimbus2_slimbus_clk = { |
| 2187 | .name = "slimbus2_slimbus_clk", |
| 2188 | .ops = &clkops_omap2_dflt, |
| 2189 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2190 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, |
| 2191 | .clkdm_name = "l4_per_clkdm", |
| 2192 | .parent = &pad_slimbus_core_clks_ck, |
| 2193 | .recalc = &followparent_recalc, |
| 2194 | }; |
| 2195 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2196 | static struct clk slimbus2_fck = { |
| 2197 | .name = "slimbus2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2198 | .ops = &clkops_omap2_dflt, |
| 2199 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2200 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2201 | .clkdm_name = "l4_per_clkdm", |
| 2202 | .parent = &l4_div_ck, |
| 2203 | .recalc = &followparent_recalc, |
| 2204 | }; |
| 2205 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2206 | static struct clk smartreflex_core_fck = { |
| 2207 | .name = "smartreflex_core_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2208 | .ops = &clkops_omap2_dflt, |
| 2209 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, |
| 2210 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2211 | .clkdm_name = "l4_ao_clkdm", |
| 2212 | .parent = &l4_wkup_clk_mux_ck, |
| 2213 | .recalc = &followparent_recalc, |
| 2214 | }; |
| 2215 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2216 | static struct clk smartreflex_iva_fck = { |
| 2217 | .name = "smartreflex_iva_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2218 | .ops = &clkops_omap2_dflt, |
| 2219 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, |
| 2220 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2221 | .clkdm_name = "l4_ao_clkdm", |
| 2222 | .parent = &l4_wkup_clk_mux_ck, |
| 2223 | .recalc = &followparent_recalc, |
| 2224 | }; |
| 2225 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2226 | static struct clk smartreflex_mpu_fck = { |
| 2227 | .name = "smartreflex_mpu_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2228 | .ops = &clkops_omap2_dflt, |
| 2229 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, |
| 2230 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2231 | .clkdm_name = "l4_ao_clkdm", |
| 2232 | .parent = &l4_wkup_clk_mux_ck, |
| 2233 | .recalc = &followparent_recalc, |
| 2234 | }; |
| 2235 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2236 | /* Merged dmt1_clk_mux into timer1 */ |
| 2237 | static struct clk timer1_fck = { |
| 2238 | .name = "timer1_fck", |
| 2239 | .parent = &sys_clkin_ck, |
| 2240 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2241 | .init = &omap2_init_clksel_parent, |
| 2242 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
| 2243 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2244 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2245 | .recalc = &omap2_clksel_recalc, |
| 2246 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
| 2247 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2248 | .clkdm_name = "l4_wkup_clkdm", |
| 2249 | }; |
| 2250 | |
| 2251 | /* Merged cm2_dm10_mux into timer10 */ |
| 2252 | static struct clk timer10_fck = { |
| 2253 | .name = "timer10_fck", |
| 2254 | .parent = &sys_clkin_ck, |
| 2255 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2256 | .init = &omap2_init_clksel_parent, |
| 2257 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
| 2258 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2259 | .ops = &clkops_omap2_dflt, |
| 2260 | .recalc = &omap2_clksel_recalc, |
| 2261 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
| 2262 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2263 | .clkdm_name = "l4_per_clkdm", |
| 2264 | }; |
| 2265 | |
| 2266 | /* Merged cm2_dm11_mux into timer11 */ |
| 2267 | static struct clk timer11_fck = { |
| 2268 | .name = "timer11_fck", |
| 2269 | .parent = &sys_clkin_ck, |
| 2270 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2271 | .init = &omap2_init_clksel_parent, |
| 2272 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
| 2273 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2274 | .ops = &clkops_omap2_dflt, |
| 2275 | .recalc = &omap2_clksel_recalc, |
| 2276 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
| 2277 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2278 | .clkdm_name = "l4_per_clkdm", |
| 2279 | }; |
| 2280 | |
| 2281 | /* Merged cm2_dm2_mux into timer2 */ |
| 2282 | static struct clk timer2_fck = { |
| 2283 | .name = "timer2_fck", |
| 2284 | .parent = &sys_clkin_ck, |
| 2285 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2286 | .init = &omap2_init_clksel_parent, |
| 2287 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
| 2288 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2289 | .ops = &clkops_omap2_dflt, |
| 2290 | .recalc = &omap2_clksel_recalc, |
| 2291 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
| 2292 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2293 | .clkdm_name = "l4_per_clkdm", |
| 2294 | }; |
| 2295 | |
| 2296 | /* Merged cm2_dm3_mux into timer3 */ |
| 2297 | static struct clk timer3_fck = { |
| 2298 | .name = "timer3_fck", |
| 2299 | .parent = &sys_clkin_ck, |
| 2300 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2301 | .init = &omap2_init_clksel_parent, |
| 2302 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
| 2303 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2304 | .ops = &clkops_omap2_dflt, |
| 2305 | .recalc = &omap2_clksel_recalc, |
| 2306 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
| 2307 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2308 | .clkdm_name = "l4_per_clkdm", |
| 2309 | }; |
| 2310 | |
| 2311 | /* Merged cm2_dm4_mux into timer4 */ |
| 2312 | static struct clk timer4_fck = { |
| 2313 | .name = "timer4_fck", |
| 2314 | .parent = &sys_clkin_ck, |
| 2315 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2316 | .init = &omap2_init_clksel_parent, |
| 2317 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
| 2318 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2319 | .ops = &clkops_omap2_dflt, |
| 2320 | .recalc = &omap2_clksel_recalc, |
| 2321 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
| 2322 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2323 | .clkdm_name = "l4_per_clkdm", |
| 2324 | }; |
| 2325 | |
| 2326 | static const struct clksel timer5_sync_mux_sel[] = { |
| 2327 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, |
| 2328 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, |
| 2329 | { .parent = NULL }, |
| 2330 | }; |
| 2331 | |
| 2332 | /* Merged timer5_sync_mux into timer5 */ |
| 2333 | static struct clk timer5_fck = { |
| 2334 | .name = "timer5_fck", |
| 2335 | .parent = &syc_clk_div_ck, |
| 2336 | .clksel = timer5_sync_mux_sel, |
| 2337 | .init = &omap2_init_clksel_parent, |
| 2338 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
| 2339 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2340 | .ops = &clkops_omap2_dflt, |
| 2341 | .recalc = &omap2_clksel_recalc, |
| 2342 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
| 2343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2344 | .clkdm_name = "abe_clkdm", |
| 2345 | }; |
| 2346 | |
| 2347 | /* Merged timer6_sync_mux into timer6 */ |
| 2348 | static struct clk timer6_fck = { |
| 2349 | .name = "timer6_fck", |
| 2350 | .parent = &syc_clk_div_ck, |
| 2351 | .clksel = timer5_sync_mux_sel, |
| 2352 | .init = &omap2_init_clksel_parent, |
| 2353 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
| 2354 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2355 | .ops = &clkops_omap2_dflt, |
| 2356 | .recalc = &omap2_clksel_recalc, |
| 2357 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
| 2358 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2359 | .clkdm_name = "abe_clkdm", |
| 2360 | }; |
| 2361 | |
| 2362 | /* Merged timer7_sync_mux into timer7 */ |
| 2363 | static struct clk timer7_fck = { |
| 2364 | .name = "timer7_fck", |
| 2365 | .parent = &syc_clk_div_ck, |
| 2366 | .clksel = timer5_sync_mux_sel, |
| 2367 | .init = &omap2_init_clksel_parent, |
| 2368 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
| 2369 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2370 | .ops = &clkops_omap2_dflt, |
| 2371 | .recalc = &omap2_clksel_recalc, |
| 2372 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
| 2373 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2374 | .clkdm_name = "abe_clkdm", |
| 2375 | }; |
| 2376 | |
| 2377 | /* Merged timer8_sync_mux into timer8 */ |
| 2378 | static struct clk timer8_fck = { |
| 2379 | .name = "timer8_fck", |
| 2380 | .parent = &syc_clk_div_ck, |
| 2381 | .clksel = timer5_sync_mux_sel, |
| 2382 | .init = &omap2_init_clksel_parent, |
| 2383 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
| 2384 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2385 | .ops = &clkops_omap2_dflt, |
| 2386 | .recalc = &omap2_clksel_recalc, |
| 2387 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
| 2388 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2389 | .clkdm_name = "abe_clkdm", |
| 2390 | }; |
| 2391 | |
| 2392 | /* Merged cm2_dm9_mux into timer9 */ |
| 2393 | static struct clk timer9_fck = { |
| 2394 | .name = "timer9_fck", |
| 2395 | .parent = &sys_clkin_ck, |
| 2396 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2397 | .init = &omap2_init_clksel_parent, |
| 2398 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
| 2399 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2400 | .ops = &clkops_omap2_dflt, |
| 2401 | .recalc = &omap2_clksel_recalc, |
| 2402 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
| 2403 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2404 | .clkdm_name = "l4_per_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2405 | }; |
| 2406 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2407 | static struct clk uart1_fck = { |
| 2408 | .name = "uart1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2409 | .ops = &clkops_omap2_dflt, |
| 2410 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
| 2411 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2412 | .clkdm_name = "l4_per_clkdm", |
| 2413 | .parent = &func_48m_fclk, |
| 2414 | .recalc = &followparent_recalc, |
| 2415 | }; |
| 2416 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2417 | static struct clk uart2_fck = { |
| 2418 | .name = "uart2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2419 | .ops = &clkops_omap2_dflt, |
| 2420 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
| 2421 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2422 | .clkdm_name = "l4_per_clkdm", |
| 2423 | .parent = &func_48m_fclk, |
| 2424 | .recalc = &followparent_recalc, |
| 2425 | }; |
| 2426 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2427 | static struct clk uart3_fck = { |
| 2428 | .name = "uart3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2429 | .ops = &clkops_omap2_dflt, |
| 2430 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
| 2431 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2432 | .clkdm_name = "l4_per_clkdm", |
| 2433 | .parent = &func_48m_fclk, |
| 2434 | .recalc = &followparent_recalc, |
| 2435 | }; |
| 2436 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2437 | static struct clk uart4_fck = { |
| 2438 | .name = "uart4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2439 | .ops = &clkops_omap2_dflt, |
| 2440 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
| 2441 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2442 | .clkdm_name = "l4_per_clkdm", |
| 2443 | .parent = &func_48m_fclk, |
| 2444 | .recalc = &followparent_recalc, |
| 2445 | }; |
| 2446 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2447 | static struct clk usb_host_fs_fck = { |
| 2448 | .name = "usb_host_fs_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2449 | .ops = &clkops_omap2_dflt, |
| 2450 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| 2451 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2452 | .clkdm_name = "l3_init_clkdm", |
| 2453 | .parent = &func_48mc_fclk, |
| 2454 | .recalc = &followparent_recalc, |
| 2455 | }; |
| 2456 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2457 | static const struct clksel utmi_p1_gfclk_sel[] = { |
| 2458 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, |
| 2459 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, |
| 2460 | { .parent = NULL }, |
| 2461 | }; |
| 2462 | |
| 2463 | static struct clk utmi_p1_gfclk = { |
| 2464 | .name = "utmi_p1_gfclk", |
| 2465 | .parent = &init_60m_fclk, |
| 2466 | .clksel = utmi_p1_gfclk_sel, |
| 2467 | .init = &omap2_init_clksel_parent, |
| 2468 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2469 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, |
| 2470 | .ops = &clkops_null, |
| 2471 | .recalc = &omap2_clksel_recalc, |
| 2472 | }; |
| 2473 | |
| 2474 | static struct clk usb_host_hs_utmi_p1_clk = { |
| 2475 | .name = "usb_host_hs_utmi_p1_clk", |
| 2476 | .ops = &clkops_omap2_dflt, |
| 2477 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2478 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, |
| 2479 | .clkdm_name = "l3_init_clkdm", |
| 2480 | .parent = &utmi_p1_gfclk, |
| 2481 | .recalc = &followparent_recalc, |
| 2482 | }; |
| 2483 | |
| 2484 | static const struct clksel utmi_p2_gfclk_sel[] = { |
| 2485 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, |
| 2486 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, |
| 2487 | { .parent = NULL }, |
| 2488 | }; |
| 2489 | |
| 2490 | static struct clk utmi_p2_gfclk = { |
| 2491 | .name = "utmi_p2_gfclk", |
| 2492 | .parent = &init_60m_fclk, |
| 2493 | .clksel = utmi_p2_gfclk_sel, |
| 2494 | .init = &omap2_init_clksel_parent, |
| 2495 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2496 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, |
| 2497 | .ops = &clkops_null, |
| 2498 | .recalc = &omap2_clksel_recalc, |
| 2499 | }; |
| 2500 | |
| 2501 | static struct clk usb_host_hs_utmi_p2_clk = { |
| 2502 | .name = "usb_host_hs_utmi_p2_clk", |
| 2503 | .ops = &clkops_omap2_dflt, |
| 2504 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2505 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, |
| 2506 | .clkdm_name = "l3_init_clkdm", |
| 2507 | .parent = &utmi_p2_gfclk, |
| 2508 | .recalc = &followparent_recalc, |
| 2509 | }; |
| 2510 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2511 | static struct clk usb_host_hs_utmi_p3_clk = { |
| 2512 | .name = "usb_host_hs_utmi_p3_clk", |
| 2513 | .ops = &clkops_omap2_dflt, |
| 2514 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2515 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, |
| 2516 | .clkdm_name = "l3_init_clkdm", |
| 2517 | .parent = &init_60m_fclk, |
| 2518 | .recalc = &followparent_recalc, |
| 2519 | }; |
| 2520 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2521 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
| 2522 | .name = "usb_host_hs_hsic480m_p1_clk", |
| 2523 | .ops = &clkops_omap2_dflt, |
| 2524 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2525 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, |
| 2526 | .clkdm_name = "l3_init_clkdm", |
| 2527 | .parent = &dpll_usb_m2_ck, |
| 2528 | .recalc = &followparent_recalc, |
| 2529 | }; |
| 2530 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2531 | static struct clk usb_host_hs_hsic60m_p1_clk = { |
| 2532 | .name = "usb_host_hs_hsic60m_p1_clk", |
| 2533 | .ops = &clkops_omap2_dflt, |
| 2534 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2535 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, |
| 2536 | .clkdm_name = "l3_init_clkdm", |
| 2537 | .parent = &init_60m_fclk, |
| 2538 | .recalc = &followparent_recalc, |
| 2539 | }; |
| 2540 | |
| 2541 | static struct clk usb_host_hs_hsic60m_p2_clk = { |
| 2542 | .name = "usb_host_hs_hsic60m_p2_clk", |
| 2543 | .ops = &clkops_omap2_dflt, |
| 2544 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2545 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, |
| 2546 | .clkdm_name = "l3_init_clkdm", |
| 2547 | .parent = &init_60m_fclk, |
| 2548 | .recalc = &followparent_recalc, |
| 2549 | }; |
| 2550 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2551 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
| 2552 | .name = "usb_host_hs_hsic480m_p2_clk", |
| 2553 | .ops = &clkops_omap2_dflt, |
| 2554 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2555 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, |
| 2556 | .clkdm_name = "l3_init_clkdm", |
| 2557 | .parent = &dpll_usb_m2_ck, |
| 2558 | .recalc = &followparent_recalc, |
| 2559 | }; |
| 2560 | |
| 2561 | static struct clk usb_host_hs_func48mclk = { |
| 2562 | .name = "usb_host_hs_func48mclk", |
| 2563 | .ops = &clkops_omap2_dflt, |
| 2564 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2565 | .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, |
| 2566 | .clkdm_name = "l3_init_clkdm", |
| 2567 | .parent = &func_48mc_fclk, |
| 2568 | .recalc = &followparent_recalc, |
| 2569 | }; |
| 2570 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2571 | static struct clk usb_host_hs_fck = { |
| 2572 | .name = "usb_host_hs_fck", |
| 2573 | .ops = &clkops_omap2_dflt, |
| 2574 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2575 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2576 | .clkdm_name = "l3_init_clkdm", |
| 2577 | .parent = &init_60m_fclk, |
| 2578 | .recalc = &followparent_recalc, |
| 2579 | }; |
| 2580 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2581 | static const struct clksel otg_60m_gfclk_sel[] = { |
| 2582 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, |
| 2583 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, |
| 2584 | { .parent = NULL }, |
| 2585 | }; |
| 2586 | |
| 2587 | static struct clk otg_60m_gfclk = { |
| 2588 | .name = "otg_60m_gfclk", |
| 2589 | .parent = &utmi_phy_clkout_ck, |
| 2590 | .clksel = otg_60m_gfclk_sel, |
| 2591 | .init = &omap2_init_clksel_parent, |
| 2592 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2593 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, |
| 2594 | .ops = &clkops_null, |
| 2595 | .recalc = &omap2_clksel_recalc, |
| 2596 | }; |
| 2597 | |
| 2598 | static struct clk usb_otg_hs_xclk = { |
| 2599 | .name = "usb_otg_hs_xclk", |
| 2600 | .ops = &clkops_omap2_dflt, |
| 2601 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2602 | .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, |
| 2603 | .clkdm_name = "l3_init_clkdm", |
| 2604 | .parent = &otg_60m_gfclk, |
| 2605 | .recalc = &followparent_recalc, |
| 2606 | }; |
| 2607 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2608 | static struct clk usb_otg_hs_ick = { |
| 2609 | .name = "usb_otg_hs_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2610 | .ops = &clkops_omap2_dflt, |
| 2611 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2612 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2613 | .clkdm_name = "l3_init_clkdm", |
| 2614 | .parent = &l3_div_ck, |
| 2615 | .recalc = &followparent_recalc, |
| 2616 | }; |
| 2617 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2618 | static struct clk usb_phy_cm_clk32k = { |
| 2619 | .name = "usb_phy_cm_clk32k", |
| 2620 | .ops = &clkops_omap2_dflt, |
| 2621 | .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, |
| 2622 | .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, |
| 2623 | .clkdm_name = "l4_ao_clkdm", |
| 2624 | .parent = &sys_32k_ck, |
| 2625 | .recalc = &followparent_recalc, |
| 2626 | }; |
| 2627 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2628 | static struct clk usb_tll_hs_usb_ch2_clk = { |
| 2629 | .name = "usb_tll_hs_usb_ch2_clk", |
| 2630 | .ops = &clkops_omap2_dflt, |
| 2631 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2632 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, |
| 2633 | .clkdm_name = "l3_init_clkdm", |
| 2634 | .parent = &init_60m_fclk, |
| 2635 | .recalc = &followparent_recalc, |
| 2636 | }; |
| 2637 | |
| 2638 | static struct clk usb_tll_hs_usb_ch0_clk = { |
| 2639 | .name = "usb_tll_hs_usb_ch0_clk", |
| 2640 | .ops = &clkops_omap2_dflt, |
| 2641 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2642 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, |
| 2643 | .clkdm_name = "l3_init_clkdm", |
| 2644 | .parent = &init_60m_fclk, |
| 2645 | .recalc = &followparent_recalc, |
| 2646 | }; |
| 2647 | |
| 2648 | static struct clk usb_tll_hs_usb_ch1_clk = { |
| 2649 | .name = "usb_tll_hs_usb_ch1_clk", |
| 2650 | .ops = &clkops_omap2_dflt, |
| 2651 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2652 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, |
| 2653 | .clkdm_name = "l3_init_clkdm", |
| 2654 | .parent = &init_60m_fclk, |
| 2655 | .recalc = &followparent_recalc, |
| 2656 | }; |
| 2657 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2658 | static struct clk usb_tll_hs_ick = { |
| 2659 | .name = "usb_tll_hs_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2660 | .ops = &clkops_omap2_dflt, |
| 2661 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2662 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2663 | .clkdm_name = "l3_init_clkdm", |
| 2664 | .parent = &l4_div_ck, |
| 2665 | .recalc = &followparent_recalc, |
| 2666 | }; |
| 2667 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2668 | static const struct clksel_rate div2_14to18_rates[] = { |
| 2669 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, |
| 2670 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, |
| 2671 | { .div = 0 }, |
| 2672 | }; |
| 2673 | |
| 2674 | static const struct clksel usim_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2675 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2676 | { .parent = NULL }, |
| 2677 | }; |
| 2678 | |
| 2679 | static struct clk usim_ck = { |
| 2680 | .name = "usim_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2681 | .parent = &dpll_per_m4x2_ck, |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2682 | .clksel = usim_fclk_div, |
| 2683 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2684 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, |
| 2685 | .ops = &clkops_null, |
| 2686 | .recalc = &omap2_clksel_recalc, |
| 2687 | .round_rate = &omap2_clksel_round_rate, |
| 2688 | .set_rate = &omap2_clksel_set_rate, |
| 2689 | }; |
| 2690 | |
| 2691 | static struct clk usim_fclk = { |
| 2692 | .name = "usim_fclk", |
| 2693 | .ops = &clkops_omap2_dflt, |
| 2694 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2695 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, |
| 2696 | .clkdm_name = "l4_wkup_clkdm", |
| 2697 | .parent = &usim_ck, |
| 2698 | .recalc = &followparent_recalc, |
| 2699 | }; |
| 2700 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2701 | static struct clk usim_fck = { |
| 2702 | .name = "usim_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2703 | .ops = &clkops_omap2_dflt, |
| 2704 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2705 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2706 | .clkdm_name = "l4_wkup_clkdm", |
| 2707 | .parent = &sys_32k_ck, |
| 2708 | .recalc = &followparent_recalc, |
| 2709 | }; |
| 2710 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2711 | static struct clk wd_timer2_fck = { |
| 2712 | .name = "wd_timer2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2713 | .ops = &clkops_omap2_dflt, |
| 2714 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
| 2715 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2716 | .clkdm_name = "l4_wkup_clkdm", |
| 2717 | .parent = &sys_32k_ck, |
| 2718 | .recalc = &followparent_recalc, |
| 2719 | }; |
| 2720 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2721 | static struct clk wd_timer3_fck = { |
| 2722 | .name = "wd_timer3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2723 | .ops = &clkops_omap2_dflt, |
| 2724 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
| 2725 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2726 | .clkdm_name = "abe_clkdm", |
| 2727 | .parent = &sys_32k_ck, |
| 2728 | .recalc = &followparent_recalc, |
| 2729 | }; |
| 2730 | |
| 2731 | /* Remaining optional clocks */ |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2732 | static const struct clksel stm_clk_div_div[] = { |
| 2733 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, |
| 2734 | { .parent = NULL }, |
| 2735 | }; |
| 2736 | |
| 2737 | static struct clk stm_clk_div_ck = { |
| 2738 | .name = "stm_clk_div_ck", |
| 2739 | .parent = &pmd_stm_clock_mux_ck, |
| 2740 | .clksel = stm_clk_div_div, |
| 2741 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, |
| 2742 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, |
| 2743 | .ops = &clkops_null, |
| 2744 | .recalc = &omap2_clksel_recalc, |
| 2745 | .round_rate = &omap2_clksel_round_rate, |
| 2746 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2747 | }; |
| 2748 | |
| 2749 | static const struct clksel trace_clk_div_div[] = { |
| 2750 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, |
| 2751 | { .parent = NULL }, |
| 2752 | }; |
| 2753 | |
| 2754 | static struct clk trace_clk_div_ck = { |
| 2755 | .name = "trace_clk_div_ck", |
| 2756 | .parent = &pmd_trace_clk_mux_ck, |
Paul Walmsley | 9a47d32 | 2012-06-17 11:57:52 -0600 | [diff] [blame] | 2757 | .clkdm_name = "emu_sys_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2758 | .clksel = trace_clk_div_div, |
| 2759 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, |
| 2760 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, |
| 2761 | .ops = &clkops_null, |
| 2762 | .recalc = &omap2_clksel_recalc, |
| 2763 | .round_rate = &omap2_clksel_round_rate, |
| 2764 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2765 | }; |
| 2766 | |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2767 | /* SCRM aux clk nodes */ |
| 2768 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2769 | static const struct clksel auxclk_src_sel[] = { |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2770 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 2771 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, |
| 2772 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, |
| 2773 | { .parent = NULL }, |
| 2774 | }; |
| 2775 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2776 | static const struct clksel_rate div16_1to16_rates[] = { |
| 2777 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 2778 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 2779 | { .div = 3, .val = 2, .flags = RATE_IN_4430 }, |
| 2780 | { .div = 4, .val = 3, .flags = RATE_IN_4430 }, |
| 2781 | { .div = 5, .val = 4, .flags = RATE_IN_4430 }, |
| 2782 | { .div = 6, .val = 5, .flags = RATE_IN_4430 }, |
| 2783 | { .div = 7, .val = 6, .flags = RATE_IN_4430 }, |
| 2784 | { .div = 8, .val = 7, .flags = RATE_IN_4430 }, |
| 2785 | { .div = 9, .val = 8, .flags = RATE_IN_4430 }, |
| 2786 | { .div = 10, .val = 9, .flags = RATE_IN_4430 }, |
| 2787 | { .div = 11, .val = 10, .flags = RATE_IN_4430 }, |
| 2788 | { .div = 12, .val = 11, .flags = RATE_IN_4430 }, |
| 2789 | { .div = 13, .val = 12, .flags = RATE_IN_4430 }, |
| 2790 | { .div = 14, .val = 13, .flags = RATE_IN_4430 }, |
| 2791 | { .div = 15, .val = 14, .flags = RATE_IN_4430 }, |
| 2792 | { .div = 16, .val = 15, .flags = RATE_IN_4430 }, |
| 2793 | { .div = 0 }, |
| 2794 | }; |
| 2795 | |
| 2796 | static struct clk auxclk0_src_ck = { |
| 2797 | .name = "auxclk0_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2798 | .parent = &sys_clkin_ck, |
| 2799 | .init = &omap2_init_clksel_parent, |
| 2800 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2801 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2802 | .clksel_reg = OMAP4_SCRM_AUXCLK0, |
| 2803 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2804 | .recalc = &omap2_clksel_recalc, |
| 2805 | .enable_reg = OMAP4_SCRM_AUXCLK0, |
| 2806 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2807 | }; |
| 2808 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2809 | static const struct clksel auxclk0_sel[] = { |
| 2810 | { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, |
| 2811 | { .parent = NULL }, |
| 2812 | }; |
| 2813 | |
| 2814 | static struct clk auxclk0_ck = { |
| 2815 | .name = "auxclk0_ck", |
| 2816 | .parent = &auxclk0_src_ck, |
| 2817 | .clksel = auxclk0_sel, |
| 2818 | .clksel_reg = OMAP4_SCRM_AUXCLK0, |
| 2819 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2820 | .ops = &clkops_null, |
| 2821 | .recalc = &omap2_clksel_recalc, |
| 2822 | .round_rate = &omap2_clksel_round_rate, |
| 2823 | .set_rate = &omap2_clksel_set_rate, |
| 2824 | }; |
| 2825 | |
| 2826 | static struct clk auxclk1_src_ck = { |
| 2827 | .name = "auxclk1_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2828 | .parent = &sys_clkin_ck, |
| 2829 | .init = &omap2_init_clksel_parent, |
| 2830 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2831 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2832 | .clksel_reg = OMAP4_SCRM_AUXCLK1, |
| 2833 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2834 | .recalc = &omap2_clksel_recalc, |
| 2835 | .enable_reg = OMAP4_SCRM_AUXCLK1, |
| 2836 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2837 | }; |
| 2838 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2839 | static const struct clksel auxclk1_sel[] = { |
| 2840 | { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, |
| 2841 | { .parent = NULL }, |
| 2842 | }; |
| 2843 | |
| 2844 | static struct clk auxclk1_ck = { |
| 2845 | .name = "auxclk1_ck", |
| 2846 | .parent = &auxclk1_src_ck, |
| 2847 | .clksel = auxclk1_sel, |
| 2848 | .clksel_reg = OMAP4_SCRM_AUXCLK1, |
| 2849 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2850 | .ops = &clkops_null, |
| 2851 | .recalc = &omap2_clksel_recalc, |
| 2852 | .round_rate = &omap2_clksel_round_rate, |
| 2853 | .set_rate = &omap2_clksel_set_rate, |
| 2854 | }; |
| 2855 | |
| 2856 | static struct clk auxclk2_src_ck = { |
| 2857 | .name = "auxclk2_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2858 | .parent = &sys_clkin_ck, |
| 2859 | .init = &omap2_init_clksel_parent, |
| 2860 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2861 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2862 | .clksel_reg = OMAP4_SCRM_AUXCLK2, |
| 2863 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2864 | .recalc = &omap2_clksel_recalc, |
| 2865 | .enable_reg = OMAP4_SCRM_AUXCLK2, |
| 2866 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2867 | }; |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 2868 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2869 | static const struct clksel auxclk2_sel[] = { |
| 2870 | { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, |
| 2871 | { .parent = NULL }, |
| 2872 | }; |
| 2873 | |
| 2874 | static struct clk auxclk2_ck = { |
| 2875 | .name = "auxclk2_ck", |
| 2876 | .parent = &auxclk2_src_ck, |
| 2877 | .clksel = auxclk2_sel, |
| 2878 | .clksel_reg = OMAP4_SCRM_AUXCLK2, |
| 2879 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2880 | .ops = &clkops_null, |
| 2881 | .recalc = &omap2_clksel_recalc, |
| 2882 | .round_rate = &omap2_clksel_round_rate, |
| 2883 | .set_rate = &omap2_clksel_set_rate, |
| 2884 | }; |
| 2885 | |
| 2886 | static struct clk auxclk3_src_ck = { |
| 2887 | .name = "auxclk3_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2888 | .parent = &sys_clkin_ck, |
| 2889 | .init = &omap2_init_clksel_parent, |
| 2890 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2891 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2892 | .clksel_reg = OMAP4_SCRM_AUXCLK3, |
| 2893 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2894 | .recalc = &omap2_clksel_recalc, |
| 2895 | .enable_reg = OMAP4_SCRM_AUXCLK3, |
| 2896 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2897 | }; |
| 2898 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2899 | static const struct clksel auxclk3_sel[] = { |
| 2900 | { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, |
| 2901 | { .parent = NULL }, |
| 2902 | }; |
| 2903 | |
| 2904 | static struct clk auxclk3_ck = { |
| 2905 | .name = "auxclk3_ck", |
| 2906 | .parent = &auxclk3_src_ck, |
| 2907 | .clksel = auxclk3_sel, |
| 2908 | .clksel_reg = OMAP4_SCRM_AUXCLK3, |
| 2909 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2910 | .ops = &clkops_null, |
| 2911 | .recalc = &omap2_clksel_recalc, |
| 2912 | .round_rate = &omap2_clksel_round_rate, |
| 2913 | .set_rate = &omap2_clksel_set_rate, |
| 2914 | }; |
| 2915 | |
| 2916 | static struct clk auxclk4_src_ck = { |
| 2917 | .name = "auxclk4_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2918 | .parent = &sys_clkin_ck, |
| 2919 | .init = &omap2_init_clksel_parent, |
| 2920 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2921 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2922 | .clksel_reg = OMAP4_SCRM_AUXCLK4, |
| 2923 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2924 | .recalc = &omap2_clksel_recalc, |
| 2925 | .enable_reg = OMAP4_SCRM_AUXCLK4, |
| 2926 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2927 | }; |
| 2928 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2929 | static const struct clksel auxclk4_sel[] = { |
| 2930 | { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, |
| 2931 | { .parent = NULL }, |
| 2932 | }; |
| 2933 | |
| 2934 | static struct clk auxclk4_ck = { |
| 2935 | .name = "auxclk4_ck", |
| 2936 | .parent = &auxclk4_src_ck, |
| 2937 | .clksel = auxclk4_sel, |
| 2938 | .clksel_reg = OMAP4_SCRM_AUXCLK4, |
| 2939 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2940 | .ops = &clkops_null, |
| 2941 | .recalc = &omap2_clksel_recalc, |
| 2942 | .round_rate = &omap2_clksel_round_rate, |
| 2943 | .set_rate = &omap2_clksel_set_rate, |
| 2944 | }; |
| 2945 | |
| 2946 | static struct clk auxclk5_src_ck = { |
| 2947 | .name = "auxclk5_src_ck", |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2948 | .parent = &sys_clkin_ck, |
| 2949 | .init = &omap2_init_clksel_parent, |
| 2950 | .ops = &clkops_omap2_dflt, |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2951 | .clksel = auxclk_src_sel, |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2952 | .clksel_reg = OMAP4_SCRM_AUXCLK5, |
| 2953 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2954 | .recalc = &omap2_clksel_recalc, |
| 2955 | .enable_reg = OMAP4_SCRM_AUXCLK5, |
| 2956 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2957 | }; |
| 2958 | |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 2959 | static const struct clksel auxclk5_sel[] = { |
| 2960 | { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates }, |
| 2961 | { .parent = NULL }, |
| 2962 | }; |
| 2963 | |
| 2964 | static struct clk auxclk5_ck = { |
| 2965 | .name = "auxclk5_ck", |
| 2966 | .parent = &auxclk5_src_ck, |
| 2967 | .clksel = auxclk5_sel, |
| 2968 | .clksel_reg = OMAP4_SCRM_AUXCLK5, |
| 2969 | .clksel_mask = OMAP4_CLKDIV_MASK, |
| 2970 | .ops = &clkops_null, |
| 2971 | .recalc = &omap2_clksel_recalc, |
| 2972 | .round_rate = &omap2_clksel_round_rate, |
| 2973 | .set_rate = &omap2_clksel_set_rate, |
| 2974 | }; |
| 2975 | |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2976 | static const struct clksel auxclkreq_sel[] = { |
| 2977 | { .parent = &auxclk0_ck, .rates = div_1_0_rates }, |
| 2978 | { .parent = &auxclk1_ck, .rates = div_1_1_rates }, |
| 2979 | { .parent = &auxclk2_ck, .rates = div_1_2_rates }, |
| 2980 | { .parent = &auxclk3_ck, .rates = div_1_3_rates }, |
| 2981 | { .parent = &auxclk4_ck, .rates = div_1_4_rates }, |
| 2982 | { .parent = &auxclk5_ck, .rates = div_1_5_rates }, |
| 2983 | { .parent = NULL }, |
| 2984 | }; |
| 2985 | |
| 2986 | static struct clk auxclkreq0_ck = { |
| 2987 | .name = "auxclkreq0_ck", |
| 2988 | .parent = &auxclk0_ck, |
| 2989 | .init = &omap2_init_clksel_parent, |
| 2990 | .ops = &clkops_null, |
| 2991 | .clksel = auxclkreq_sel, |
| 2992 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, |
| 2993 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2994 | .recalc = &omap2_clksel_recalc, |
| 2995 | }; |
| 2996 | |
| 2997 | static struct clk auxclkreq1_ck = { |
| 2998 | .name = "auxclkreq1_ck", |
| 2999 | .parent = &auxclk1_ck, |
| 3000 | .init = &omap2_init_clksel_parent, |
| 3001 | .ops = &clkops_null, |
| 3002 | .clksel = auxclkreq_sel, |
| 3003 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, |
| 3004 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3005 | .recalc = &omap2_clksel_recalc, |
| 3006 | }; |
| 3007 | |
| 3008 | static struct clk auxclkreq2_ck = { |
| 3009 | .name = "auxclkreq2_ck", |
| 3010 | .parent = &auxclk2_ck, |
| 3011 | .init = &omap2_init_clksel_parent, |
| 3012 | .ops = &clkops_null, |
| 3013 | .clksel = auxclkreq_sel, |
| 3014 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, |
| 3015 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3016 | .recalc = &omap2_clksel_recalc, |
| 3017 | }; |
| 3018 | |
| 3019 | static struct clk auxclkreq3_ck = { |
| 3020 | .name = "auxclkreq3_ck", |
| 3021 | .parent = &auxclk3_ck, |
| 3022 | .init = &omap2_init_clksel_parent, |
| 3023 | .ops = &clkops_null, |
| 3024 | .clksel = auxclkreq_sel, |
| 3025 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, |
| 3026 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3027 | .recalc = &omap2_clksel_recalc, |
| 3028 | }; |
| 3029 | |
| 3030 | static struct clk auxclkreq4_ck = { |
| 3031 | .name = "auxclkreq4_ck", |
| 3032 | .parent = &auxclk4_ck, |
| 3033 | .init = &omap2_init_clksel_parent, |
| 3034 | .ops = &clkops_null, |
| 3035 | .clksel = auxclkreq_sel, |
| 3036 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, |
| 3037 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3038 | .recalc = &omap2_clksel_recalc, |
| 3039 | }; |
| 3040 | |
| 3041 | static struct clk auxclkreq5_ck = { |
| 3042 | .name = "auxclkreq5_ck", |
| 3043 | .parent = &auxclk5_ck, |
| 3044 | .init = &omap2_init_clksel_parent, |
| 3045 | .ops = &clkops_null, |
| 3046 | .clksel = auxclkreq_sel, |
| 3047 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, |
| 3048 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3049 | .recalc = &omap2_clksel_recalc, |
| 3050 | }; |
| 3051 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3052 | /* |
| 3053 | * clkdev |
| 3054 | */ |
| 3055 | |
| 3056 | static struct omap_clk omap44xx_clks[] = { |
| 3057 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), |
| 3058 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), |
| 3059 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), |
| 3060 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), |
| 3061 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), |
| 3062 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), |
| 3063 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), |
| 3064 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), |
| 3065 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), |
| 3066 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), |
| 3067 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), |
| 3068 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), |
| 3069 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), |
| 3070 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3071 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3072 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), |
| 3073 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), |
| 3074 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), |
| 3075 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3076 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3077 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
| 3078 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3079 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3080 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
| 3081 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), |
| 3082 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), |
| 3083 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3084 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3085 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
| 3086 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3087 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
| 3088 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3089 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
| 3090 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), |
| 3091 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3092 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3093 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
| 3094 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), |
| 3095 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3096 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3097 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
| 3098 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3099 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
| 3100 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3101 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
| 3102 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3103 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
| 3104 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), |
| 3105 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3106 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
| 3107 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), |
| 3108 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), |
| 3109 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), |
| 3110 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), |
| 3111 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3112 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3113 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3114 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
| 3115 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), |
| 3116 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), |
| 3117 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), |
| 3118 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3119 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), |
| 3120 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), |
| 3121 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), |
| 3122 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), |
| 3123 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), |
| 3124 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), |
| 3125 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), |
| 3126 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), |
| 3127 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), |
| 3128 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), |
| 3129 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), |
| 3130 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3131 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), |
| 3132 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), |
| 3133 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), |
| 3134 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), |
| 3135 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), |
Santosh Shilimkar | 30c9569 | 2011-12-16 16:09:12 -0800 | [diff] [blame] | 3136 | CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3137 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), |
| 3138 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), |
Jon Hunter | de47453 | 2011-07-09 19:14:47 -0600 | [diff] [blame] | 3139 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3140 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), |
| 3141 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), |
| 3142 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3143 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
| 3144 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), |
| 3145 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3146 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), |
Rajendra Nayak | 257d643 | 2011-07-02 08:00:24 +0530 | [diff] [blame] | 3147 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3148 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
Rajendra Nayak | 257d643 | 2011-07-02 08:00:24 +0530 | [diff] [blame] | 3149 | CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3150 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3151 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3152 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 3153 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), |
| 3154 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), |
| 3155 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), |
| 3156 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3157 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
Tomi Valkeinen | 2df122f | 2011-04-04 09:26:19 +0300 | [diff] [blame] | 3158 | CLK("omapdss_dss", "ick", &dss_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3159 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), |
| 3160 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), |
| 3161 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3162 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3163 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3164 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3165 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3166 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3167 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3168 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3169 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3170 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3171 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3172 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3173 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3174 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3175 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
| 3176 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3177 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3178 | CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3179 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3180 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), |
| 3181 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), |
| 3182 | CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), |
| 3183 | CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3184 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3185 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3186 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3187 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), |
| 3188 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), |
| 3189 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), |
| 3190 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3191 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3192 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3193 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3194 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3195 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3196 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3197 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3198 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3199 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3200 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3201 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3202 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), |
| 3203 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), |
| 3204 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), |
| 3205 | CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), |
| 3206 | CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), |
| 3207 | CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), |
| 3208 | CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), |
| 3209 | CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), |
| 3210 | CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3211 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3212 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3213 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3214 | CLK(NULL, "rng_ick", &rng_ick, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3215 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3216 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
| 3217 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3218 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
| 3219 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), |
| 3220 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), |
| 3221 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3222 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3223 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), |
| 3224 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), |
| 3225 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3226 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3227 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), |
| 3228 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), |
| 3229 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), |
Tarun Kanti DebBarma | ae6df41 | 2012-07-05 18:10:59 +0530 | [diff] [blame] | 3230 | CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), |
| 3231 | CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), |
| 3232 | CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), |
| 3233 | CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), |
| 3234 | CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), |
| 3235 | CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), |
| 3236 | CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), |
| 3237 | CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), |
| 3238 | CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), |
| 3239 | CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), |
| 3240 | CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3241 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
| 3242 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), |
| 3243 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), |
| 3244 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3245 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3246 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3247 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
| 3248 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), |
| 3249 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), |
| 3250 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3251 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3252 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3253 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), |
| 3254 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3255 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
| 3256 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3257 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3258 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3259 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
| 3260 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3261 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), |
Felipe Balbi | 0349176 | 2010-12-02 09:57:08 +0200 | [diff] [blame] | 3262 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3263 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3264 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
| 3265 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), |
| 3266 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3267 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3268 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), |
Paul Walmsley | 8fde3af | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3269 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3270 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
| 3271 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3272 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3273 | CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3274 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3275 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
| 3276 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3277 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3278 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3279 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3280 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), |
| 3281 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3282 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3283 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), |
| 3284 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3285 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3286 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), |
| 3287 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3288 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3289 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), |
| 3290 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3291 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), |
Rajendra Nayak | ad03f1c | 2011-07-10 05:56:14 -0600 | [diff] [blame] | 3292 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), |
| 3293 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3294 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3295 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 3296 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
| 3297 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), |
| 3298 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), |
| 3299 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), |
Benoit Cousson | 7ecd422 | 2011-07-09 19:14:45 -0600 | [diff] [blame] | 3300 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 3301 | CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), |
| 3302 | CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), |
| 3303 | CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), |
| 3304 | CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), |
| 3305 | CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3306 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), |
| 3307 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), |
| 3308 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), |
| 3309 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3310 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), |
| 3311 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), |
| 3312 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), |
| 3313 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3314 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), |
| 3315 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), |
| 3316 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), |
| 3317 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3318 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), |
| 3319 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), |
Paul Walmsley | 8fde3af | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3320 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3321 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), |
Jon Hunter | c59b537 | 2012-06-05 12:35:00 -0500 | [diff] [blame] | 3322 | CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), |
Jon Hunter | fabcf41 | 2012-09-22 02:24:15 -0600 | [diff] [blame] | 3323 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ |
Jon Hunter | c59b537 | 2012-06-05 12:35:00 -0500 | [diff] [blame] | 3324 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3325 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3326 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3327 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3328 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3329 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3330 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3331 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3332 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3333 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3334 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
Jon Hunter | fabcf41 | 2012-09-22 02:24:15 -0600 | [diff] [blame] | 3335 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3336 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3337 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3338 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3339 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3340 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3341 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
| 3342 | CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3343 | CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3344 | CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
| 3345 | CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
Paul Walmsley | c810fde | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3346 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3347 | }; |
| 3348 | |
Paul Walmsley | e80a972 | 2010-01-26 20:13:12 -0700 | [diff] [blame] | 3349 | int __init omap4xxx_clk_init(void) |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3350 | { |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3351 | struct omap_clk *c; |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3352 | u32 cpu_clkflg; |
| 3353 | |
Paul Walmsley | 52a3a4d | 2011-10-07 00:53:08 -0600 | [diff] [blame] | 3354 | if (cpu_is_omap443x()) { |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3355 | cpu_mask = RATE_IN_4430; |
| 3356 | cpu_clkflg = CK_443X; |
Jon Hunter | e90b833 | 2012-06-25 12:38:23 -0500 | [diff] [blame] | 3357 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { |
Paul Walmsley | 52a3a4d | 2011-10-07 00:53:08 -0600 | [diff] [blame] | 3358 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; |
| 3359 | cpu_clkflg = CK_446X | CK_443X; |
Jon Hunter | e90b833 | 2012-06-25 12:38:23 -0500 | [diff] [blame] | 3360 | |
| 3361 | if (cpu_is_omap447x()) |
| 3362 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); |
Paul Walmsley | 450a37d | 2011-08-21 00:28:56 -0600 | [diff] [blame] | 3363 | } else { |
| 3364 | return 0; |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3365 | } |
| 3366 | |
Paul Walmsley | 9c5f560 | 2011-08-19 16:59:56 -0600 | [diff] [blame] | 3367 | /* |
| 3368 | * Must stay commented until all OMAP SoC drivers are |
| 3369 | * converted to runtime PM, or drivers may start crashing |
| 3370 | * |
| 3371 | * omap2_clk_disable_clkdm_control(); |
| 3372 | */ |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3373 | |
| 3374 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); |
| 3375 | c++) |
| 3376 | clk_preinit(c->lk.clk); |
| 3377 | |
| 3378 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); |
| 3379 | c++) |
| 3380 | if (c->cpu & cpu_clkflg) { |
| 3381 | clkdev_add(&c->lk); |
| 3382 | clk_register(c->lk.clk); |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3383 | omap2_init_clk_clkdm(c->lk.clk); |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3384 | } |
| 3385 | |
Paul Walmsley | c6461f5 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 3386 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
| 3387 | omap_clk_disable_autoidle_all(); |
| 3388 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3389 | recalculate_root_clocks(); |
| 3390 | |
| 3391 | /* |
| 3392 | * Only enable those clocks we will need, let the drivers |
| 3393 | * enable other clocks as necessary |
| 3394 | */ |
| 3395 | clk_enable_init_clocks(); |
| 3396 | |
| 3397 | return 0; |
| 3398 | } |