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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070031#include <linux/platform_data/gpio-omap.h>
32
Jean Pihet5e7c58d2011-03-03 11:25:43 +010033#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070034
Russell King2c74a0c2011-06-22 17:41:48 +010035#include <asm/suspend.h>
David Howells9f97da72012-03-28 18:30:01 +010036#include <asm/system_misc.h>
Russell King2c74a0c2011-06-22 17:41:48 +010037
Paul Walmsley1540f2142010-12-21 21:05:15 -070038#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070039#include "powerdomain.h"
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053040#include <plat/prcm.h>
Lokesh Vutla2b6c4e72012-10-15 14:04:53 -070041#include <plat-omap/dma-omap.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070042
Tony Lindgren622297f2012-10-02 14:19:52 -070043#include "../plat-omap/sram.h"
44
Tony Lindgren4e653312011-11-10 22:45:17 +010045#include "common.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070046#include "cm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070047#include "cm-regbits-34xx.h"
Tony Lindgren99f0b8d2012-10-17 11:07:18 -070048#include "gpmc.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070049#include "prm-regbits-34xx.h"
50
Paul Walmsley59fb6592010-12-21 15:30:55 -070051#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070052#include "pm.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030053#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060054#include "control.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030055
Nishanth Menon8cdfd832010-12-20 14:05:05 -060056/* pm34xx errata defined in pm.h */
57u16 pm34xx_errata;
58
Kevin Hilman8bd22942009-05-28 10:56:16 -070059struct power_state {
60 struct powerdomain *pwrdm;
61 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070062#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070063 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070064#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070065 struct list_head node;
66};
67
68static LIST_HEAD(pwrst_list);
69
Tero Kristo27d59a42008-10-13 13:15:00 +030070static int (*_omap_save_secure_sram)(u32 *addr);
Jean Pihet46e130d2011-06-29 18:40:23 +020071void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030072
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053073static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
74static struct powerdomain *core_pwrdm, *per_pwrdm;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020075
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053076static void omap3_core_save_context(void)
77{
Paul Walmsley596efe42010-12-21 21:05:16 -070078 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +020079
80 /*
81 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +010082 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +020083 */
84 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
85 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
86
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053087 /* Save the Interrupt controller context */
88 omap_intc_save_context();
89 /* Save the GPMC context */
90 omap3_gpmc_save_context();
91 /* Save the system control module context, padconf already save above*/
92 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +000093 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053094}
95
96static void omap3_core_restore_context(void)
97{
98 /* Restore the control module context, padconf restored by h/w */
99 omap3_control_restore_context();
100 /* Restore the GPMC context */
101 omap3_gpmc_restore_context();
102 /* Restore the interrupt controller context */
103 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000104 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530105}
106
Tero Kristo9d971402008-12-12 11:20:05 +0200107/*
108 * FIXME: This function should be called before entering off-mode after
109 * OMAP3 secure services have been accessed. Currently it is only called
110 * once during boot sequence, but this works as we are not using secure
111 * services.
112 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800113static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300114{
115 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800116 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300117
118 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300119 /*
120 * MPU next state must be set to POWER_ON temporarily,
121 * otherwise the WFI executed inside the ROM code
122 * will hang the system.
123 */
124 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
125 ret = _omap_save_secure_sram((u32 *)
126 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800127 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300128 /* Following is for error tracking, it should not happen */
129 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700130 pr_err("save_secure_sram() returns %08x\n", ret);
Tero Kristo27d59a42008-10-13 13:15:00 +0300131 while (1)
132 ;
133 }
134 }
135}
136
Jon Hunter77da2d92009-06-27 00:07:25 -0500137/*
138 * PRCM Interrupt Handler Helper Function
139 *
140 * The purpose of this function is to clear any wake-up events latched
141 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
142 * may occur whilst attempting to clear a PM_WKST_x register and thus
143 * set another bit in this register. A while loop is used to ensure
144 * that any peripheral wake-up events occurring while attempting to
145 * clear the PM_WKST_x are detected and cleared.
146 */
Tero Kristo22f51372011-12-16 14:36:59 -0700147static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
Jon Hunter77da2d92009-06-27 00:07:25 -0500148{
Vikram Pandita71a80772009-07-17 19:33:09 -0500149 u32 wkst, fclk, iclk, clken;
Jon Hunter77da2d92009-06-27 00:07:25 -0500150 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
151 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
152 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
Paul Walmsley5d805972009-07-22 10:18:07 -0700153 u16 grpsel_off = (regs == 3) ?
154 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700155 int c = 0;
Jon Hunter77da2d92009-06-27 00:07:25 -0500156
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700157 wkst = omap2_prm_read_mod_reg(module, wkst_off);
158 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700159 wkst &= ~ignore_bits;
Jon Hunter77da2d92009-06-27 00:07:25 -0500160 if (wkst) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700161 iclk = omap2_cm_read_mod_reg(module, iclk_off);
162 fclk = omap2_cm_read_mod_reg(module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500163 while (wkst) {
Vikram Pandita71a80772009-07-17 19:33:09 -0500164 clken = wkst;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700165 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
Vikram Pandita71a80772009-07-17 19:33:09 -0500166 /*
167 * For USBHOST, we don't know whether HOST1 or
168 * HOST2 woke us up, so enable both f-clocks
169 */
170 if (module == OMAP3430ES2_USBHOST_MOD)
171 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700172 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
173 omap2_prm_write_mod_reg(wkst, module, wkst_off);
174 wkst = omap2_prm_read_mod_reg(module, wkst_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700175 wkst &= ~ignore_bits;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700176 c++;
Jon Hunter77da2d92009-06-27 00:07:25 -0500177 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700178 omap2_cm_write_mod_reg(iclk, module, iclk_off);
179 omap2_cm_write_mod_reg(fclk, module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500180 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700181
182 return c;
183}
184
Tero Kristo22f51372011-12-16 14:36:59 -0700185static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700186{
187 int c;
188
Tero Kristo22f51372011-12-16 14:36:59 -0700189 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
190 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700191
Tero Kristo22f51372011-12-16 14:36:59 -0700192 return c ? IRQ_HANDLED : IRQ_NONE;
Jon Hunter77da2d92009-06-27 00:07:25 -0500193}
194
Tero Kristo22f51372011-12-16 14:36:59 -0700195static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700196{
Tero Kristo22f51372011-12-16 14:36:59 -0700197 int c;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700198
Tero Kristo22f51372011-12-16 14:36:59 -0700199 /*
200 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
201 * these are handled in a separate handler to avoid acking
202 * IO events before parsing in mux code
203 */
204 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
205 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
206 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
207 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
208 if (omap_rev() > OMAP3430_REV_ES1_0) {
209 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
210 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
211 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700212
Tero Kristo22f51372011-12-16 14:36:59 -0700213 return c ? IRQ_HANDLED : IRQ_NONE;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700214}
215
Russell Kingcbe26342011-06-30 08:45:49 +0100216static void omap34xx_save_context(u32 *save)
217{
218 u32 val;
219
220 /* Read Auxiliary Control Register */
221 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
222 *save++ = 1;
223 *save++ = val;
224
225 /* Read L2 AUX ctrl register */
226 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
227 *save++ = 1;
228 *save++ = val;
229}
230
Russell King29cb3cd2011-07-02 09:54:01 +0100231static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530232{
Russell Kingcbe26342011-06-30 08:45:49 +0100233 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100234 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530235}
236
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530237void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700238{
239 /* Variable to tell what needs to be saved and restored
240 * in omap_sram_idle*/
241 /* save_state = 0 => Nothing to save and restored */
242 /* save_state = 1 => Only L1 and logic lost */
243 /* save_state = 2 => Only L2 lost */
244 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530245 int save_state = 0;
246 int mpu_next_state = PWRDM_POWER_ON;
247 int per_next_state = PWRDM_POWER_ON;
248 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700249 int per_going_off;
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600250 int core_prev_state;
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300251 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700252
Kevin Hilman8bd22942009-05-28 10:56:16 -0700253 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
254 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530255 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700256 case PWRDM_POWER_RET:
257 /* No need to save context */
258 save_state = 0;
259 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530260 case PWRDM_POWER_OFF:
261 save_state = 3;
262 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700263 default:
264 /* Invalid state */
Mark A. Greer98179852012-03-17 18:22:48 -0700265 pr_err("Invalid mpu state in sram_idle\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700266 return;
267 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300268
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530269 /* NEON control */
270 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200271 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530272
Mike Chan40742fa2010-05-03 16:04:06 -0700273 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800274 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200275 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Mike Chan40742fa2010-05-03 16:04:06 -0700276
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700277 pwrdm_pre_transition(NULL);
Charulatha Vff2f8e52011-09-13 18:32:37 +0530278
Mike Chan40742fa2010-05-03 16:04:06 -0700279 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800280 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700281 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700282 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilman658ce972008-11-04 20:50:52 -0800283 }
284
285 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530286 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530287 if (core_next_state == PWRDM_POWER_OFF) {
288 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700289 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530290 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530291 }
Mike Chan40742fa2010-05-03 16:04:06 -0700292
Tero Kristof18cc2f2009-10-23 19:03:50 +0300293 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700294
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530295 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600296 * On EMU/HS devices ROM code restores a SRDC value
297 * from scratchpad which has automatic self refresh on timeout
298 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
299 * Hence store/restore the SDRC_POWER register here.
300 */
301 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
302 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
303 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530304 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300305 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300306
307 /*
Russell King076f2cc2011-06-22 15:42:54 +0100308 * omap3_arm_context is the location where some ARM context
309 * get saved. The rest is placed on the stack, and restored
310 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530311 */
Russell Kingcbe26342011-06-30 08:45:49 +0100312 if (save_state)
313 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100314 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100315 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100316 else
317 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700318
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530319 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600320 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
321 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
322 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300323 core_next_state == PWRDM_POWER_OFF)
324 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
325
Kevin Hilman658ce972008-11-04 20:50:52 -0800326 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530327 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530328 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
329 if (core_prev_state == PWRDM_POWER_OFF) {
330 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700331 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530332 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300333 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530334 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800335 if (core_next_state == PWRDM_POWER_OFF)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700336 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
Kevin Hilman658ce972008-11-04 20:50:52 -0800337 OMAP3430_GR_MOD,
338 OMAP3_PRM_VOLTCTRL_OFFSET);
339 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300340 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800341
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700342 pwrdm_post_transition(NULL);
Kevin Hilman658ce972008-11-04 20:50:52 -0800343
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700344 /* PER */
345 if (per_next_state < PWRDM_POWER_ON)
346 omap2_gpio_resume_after_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700347}
348
Kevin Hilman8bd22942009-05-28 10:56:16 -0700349static void omap3_pm_idle(void)
350{
Kevin Hilman8bd22942009-05-28 10:56:16 -0700351 local_fiq_disable();
352
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500353 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700354 goto out;
355
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100356 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
357 trace_cpu_idle(1, smp_processor_id());
358
Kevin Hilman8bd22942009-05-28 10:56:16 -0700359 omap_sram_idle();
360
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100361 trace_power_end(smp_processor_id());
362 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
363
Kevin Hilman8bd22942009-05-28 10:56:16 -0700364out:
365 local_fiq_enable();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700366}
367
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700368#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700369static int omap3_pm_suspend(void)
370{
371 struct power_state *pwrst;
372 int state, ret = 0;
373
374 /* Read current next_pwrsts */
375 list_for_each_entry(pwrst, &pwrst_list, node)
376 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
377 /* Set ones wanted by suspend */
378 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530379 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700380 goto restore;
381 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
382 goto restore;
383 }
384
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300385 omap3_intc_suspend();
386
Kevin Hilman8bd22942009-05-28 10:56:16 -0700387 omap_sram_idle();
388
389restore:
390 /* Restore next_pwrsts */
391 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700392 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
393 if (state > pwrst->next_state) {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600394 pr_info("Powerdomain (%s) didn't enter target state %d\n",
395 pwrst->pwrdm->name, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700396 ret = -1;
397 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530398 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700399 }
400 if (ret)
Mark A. Greer98179852012-03-17 18:22:48 -0700401 pr_err("Could not enter target state in pm_suspend\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700402 else
Mark A. Greer98179852012-03-17 18:22:48 -0700403 pr_info("Successfully put all powerdomains to target state\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700404
405 return ret;
406}
407
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700408#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700409
Kevin Hilman1155e422008-11-25 11:48:24 -0800410
411/**
412 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
413 * retention
414 *
415 * In cases where IVA2 is activated by bootcode, it may prevent
416 * full-chip retention or off-mode because it is not idle. This
417 * function forces the IVA2 into idle state so it can go
418 * into retention/off and thus allow full-chip retention/off.
419 *
420 **/
421static void __init omap3_iva_idle(void)
422{
423 /* ensure IVA2 clock is disabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700424 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800425
426 /* if no clock activity, nothing else to do */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700427 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
Kevin Hilman1155e422008-11-25 11:48:24 -0800428 OMAP3430_CLKACTIVITY_IVA2_MASK))
429 return;
430
431 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700432 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600433 OMAP3430_RST2_IVA2_MASK |
434 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700435 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800436
437 /* Enable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700438 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
Kevin Hilman1155e422008-11-25 11:48:24 -0800439 OMAP3430_IVA2_MOD, CM_FCLKEN);
440
441 /* Set IVA2 boot mode to 'idle' */
442 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
443 OMAP343X_CONTROL_IVA2_BOOTMOD);
444
445 /* Un-reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700446 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800447
448 /* Disable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700449 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800450
451 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700452 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600453 OMAP3430_RST2_IVA2_MASK |
454 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700455 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800456}
457
Kevin Hilman8111b222009-04-28 15:27:44 -0700458static void __init omap3_d2d_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700459{
Kevin Hilman8111b222009-04-28 15:27:44 -0700460 u16 mask, padconf;
461
462 /* In a stand alone OMAP3430 where there is not a stacked
463 * modem for the D2D Idle Ack and D2D MStandby must be pulled
464 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
465 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
466 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
467 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
468 padconf |= mask;
469 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
470
471 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
472 padconf |= mask;
473 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
474
Kevin Hilman8bd22942009-05-28 10:56:16 -0700475 /* reset modem */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700476 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600477 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700478 CORE_MOD, OMAP2_RM_RSTCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700479 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman8111b222009-04-28 15:27:44 -0700480}
Kevin Hilman8bd22942009-05-28 10:56:16 -0700481
Kevin Hilman8111b222009-04-28 15:27:44 -0700482static void __init prcm_setup_regs(void)
483{
Govindraj.Re5863682010-09-27 20:20:25 +0530484 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
485 OMAP3630_EN_UART4_MASK : 0;
486 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
487 OMAP3630_GRPSEL_UART4_MASK : 0;
488
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700489 /* XXX This should be handled by hwmod code or SCM init code */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600490 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
Tero Kristob296c812009-10-23 19:03:49 +0300491
Kevin Hilman8bd22942009-05-28 10:56:16 -0700492 /*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700493 * Enable control of expternal oscillator through
494 * sys_clkreq. In the long run clock framework should
495 * take care of this.
496 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700497 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700498 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
499 OMAP3430_GR_MOD,
500 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
501
502 /* setup wakup source */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700503 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600504 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700505 WKUP_MOD, PM_WKEN);
506 /* No need to write EN_IO, that is always enabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700507 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600508 OMAP3430_GRPSEL_GPT1_MASK |
509 OMAP3430_GRPSEL_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700510 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800511
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530512 /* Enable PM_WKEN to support DSS LPR */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700513 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530514 OMAP3430_DSS_MOD, PM_WKEN);
515
Kevin Hilmanb427f922009-10-22 14:48:13 -0700516 /* Enable wakeups in PER */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700517 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530518 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600519 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
520 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
521 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
522 OMAP3430_EN_MCBSP4_MASK,
Kevin Hilmanb427f922009-10-22 14:48:13 -0700523 OMAP3430_PER_MOD, PM_WKEN);
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000524 /* and allow them to wake up MPU */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700525 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530526 OMAP3430_GRPSEL_GPIO2_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600527 OMAP3430_GRPSEL_GPIO3_MASK |
528 OMAP3430_GRPSEL_GPIO4_MASK |
529 OMAP3430_GRPSEL_GPIO5_MASK |
530 OMAP3430_GRPSEL_GPIO6_MASK |
531 OMAP3430_GRPSEL_UART3_MASK |
532 OMAP3430_GRPSEL_MCBSP2_MASK |
533 OMAP3430_GRPSEL_MCBSP3_MASK |
534 OMAP3430_GRPSEL_MCBSP4_MASK,
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000535 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
536
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700537 /* Don't attach IVA interrupts */
Mark A. Greera819c4f2012-04-19 11:17:45 -0700538 if (omap3_has_iva()) {
539 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
540 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
541 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
542 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
543 OMAP3430_PM_IVAGRPSEL);
544 }
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700545
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700546 /* Clear any pending 'reset' flags */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700547 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
548 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
549 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
550 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
551 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
552 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
553 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700554
Kevin Hilman014c46d2009-04-27 07:50:23 -0700555 /* Clear any pending PRCM interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700556 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman014c46d2009-04-27 07:50:23 -0700557
Mark A. Greera819c4f2012-04-19 11:17:45 -0700558 if (omap3_has_iva())
559 omap3_iva_idle();
560
Kevin Hilman8111b222009-04-28 15:27:44 -0700561 omap3_d2d_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700562}
563
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700564void omap3_pm_off_mode_enable(int enable)
565{
566 struct power_state *pwrst;
567 u32 state;
568
569 if (enable)
570 state = PWRDM_POWER_OFF;
571 else
572 state = PWRDM_POWER_RET;
573
574 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600575 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
576 pwrst->pwrdm == core_pwrdm &&
577 state == PWRDM_POWER_OFF) {
578 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200579 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600580 __func__);
581 } else {
582 pwrst->next_state = state;
583 }
584 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700585 }
586}
587
Tero Kristo68d47782008-11-26 12:26:24 +0200588int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
589{
590 struct power_state *pwrst;
591
592 list_for_each_entry(pwrst, &pwrst_list, node) {
593 if (pwrst->pwrdm == pwrdm)
594 return pwrst->next_state;
595 }
596 return -EINVAL;
597}
598
599int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
600{
601 struct power_state *pwrst;
602
603 list_for_each_entry(pwrst, &pwrst_list, node) {
604 if (pwrst->pwrdm == pwrdm) {
605 pwrst->next_state = state;
606 return 0;
607 }
608 }
609 return -EINVAL;
610}
611
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300612static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700613{
614 struct power_state *pwrst;
615
616 if (!pwrdm->pwrsts)
617 return 0;
618
Ming Leid3d381c2009-08-22 21:20:26 +0800619 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700620 if (!pwrst)
621 return -ENOMEM;
622 pwrst->pwrdm = pwrdm;
623 pwrst->next_state = PWRDM_POWER_RET;
624 list_add(&pwrst->node, &pwrst_list);
625
626 if (pwrdm_has_hdwr_sar(pwrdm))
627 pwrdm_enable_hdwr_sar(pwrdm);
628
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530629 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700630}
631
632/*
Jean Pihet46e130d2011-06-29 18:40:23 +0200633 * Push functions to SRAM
634 *
635 * The minimum set of functions is pushed to SRAM for execution:
636 * - omap3_do_wfi for erratum i581 WA,
637 * - save_secure_ram_context for security extensions.
638 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530639void omap_push_sram_idle(void)
640{
Jean Pihet46e130d2011-06-29 18:40:23 +0200641 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
642
Tero Kristo27d59a42008-10-13 13:15:00 +0300643 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
644 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
645 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530646}
647
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600648static void __init pm_errata_configure(void)
649{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600650 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600651 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600652 /* Enable the l2 cache toggling in sleep logic */
653 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600654 if (omap_rev() < OMAP3630_REV_ES1_2)
655 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600656 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600657}
658
Shawn Guobbd707a2012-04-26 16:06:50 +0800659int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700660{
661 struct power_state *pwrst, *tmp;
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600662 struct clockdomain *neon_clkdm, *mpu_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700663 int ret;
664
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600665 if (!omap3_has_io_chain_ctrl())
666 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
667
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600668 pm_errata_configure();
669
Kevin Hilman8bd22942009-05-28 10:56:16 -0700670 /* XXX prcm_setup_regs needs to be before enabling hw
671 * supervised mode for powerdomains */
672 prcm_setup_regs();
673
Tero Kristo22f51372011-12-16 14:36:59 -0700674 ret = request_irq(omap_prcm_event_to_irq("wkup"),
675 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
676
Kevin Hilman8bd22942009-05-28 10:56:16 -0700677 if (ret) {
Tero Kristo22f51372011-12-16 14:36:59 -0700678 pr_err("pm: Failed to request pm_wkup irq\n");
679 goto err1;
680 }
681
682 /* IO interrupt is shared with mux code */
683 ret = request_irq(omap_prcm_event_to_irq("io"),
684 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
685 omap3_pm_init);
Kevin Hilman99b59df2012-04-27 16:05:51 -0700686 enable_irq(omap_prcm_event_to_irq("io"));
Tero Kristo22f51372011-12-16 14:36:59 -0700687
688 if (ret) {
689 pr_err("pm: Failed to request pm_io irq\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700690 goto err2;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700691 }
692
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300693 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700694 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700695 pr_err("Failed to setup powerdomains\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700696 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700697 }
698
Paul Walmsley92206fd2012-02-02 02:38:50 -0700699 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700700
701 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
702 if (mpu_pwrdm == NULL) {
Mark A. Greer98179852012-03-17 18:22:48 -0700703 pr_err("Failed to get mpu_pwrdm\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700704 ret = -EINVAL;
705 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700706 }
707
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530708 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
709 per_pwrdm = pwrdm_lookup("per_pwrdm");
710 core_pwrdm = pwrdm_lookup("core_pwrdm");
711
Paul Walmsley55ed9692010-01-26 20:12:59 -0700712 neon_clkdm = clkdm_lookup("neon_clkdm");
713 mpu_clkdm = clkdm_lookup("mpu_clkdm");
Paul Walmsley55ed9692010-01-26 20:12:59 -0700714
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700715#ifdef CONFIG_SUSPEND
Paul Walmsley14164082012-02-02 02:30:50 -0700716 omap_pm_suspend = omap3_pm_suspend;
717#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -0700718
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500719 arm_pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300720 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700721
Nishanth Menon458e9992010-12-20 14:05:06 -0600722 /*
723 * RTA is disabled during initialization as per erratum i608
724 * it is safer to disable RTA by the bootloader, but we would like
725 * to be doubly sure here and prevent any mishaps.
726 */
727 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
728 omap3630_ctrl_disable_rta();
729
Paul Walmsley55ed9692010-01-26 20:12:59 -0700730 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300731 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
732 omap3_secure_ram_storage =
733 kmalloc(0x803F, GFP_KERNEL);
734 if (!omap3_secure_ram_storage)
Paul Walmsley7852ec02012-07-26 00:54:26 -0600735 pr_err("Memory allocation failed when allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300736
Tero Kristo9d971402008-12-12 11:20:05 +0200737 local_irq_disable();
738 local_fiq_disable();
739
740 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800741 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200742 omap_dma_global_context_restore();
743
744 local_irq_enable();
745 local_fiq_enable();
746 }
747
748 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700749 return ret;
Mark A. Greerce229c52012-03-17 18:22:47 -0700750
751err3:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700752 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
753 list_del(&pwrst->node);
754 kfree(pwrst);
755 }
Mark A. Greerce229c52012-03-17 18:22:47 -0700756 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
757err2:
758 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
759err1:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700760 return ret;
761}