Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/include/asm/uaccess.h |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | #ifndef __ASM_UACCESS_H |
| 19 | #define __ASM_UACCESS_H |
| 20 | |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 21 | #include <asm/alternative.h> |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 22 | #include <asm/kernel-pgtable.h> |
Will Deacon | d7013ed | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 23 | #include <asm/mmu.h> |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 24 | #include <asm/sysreg.h> |
| 25 | |
| 26 | #ifndef __ASSEMBLY__ |
| 27 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 28 | /* |
| 29 | * User space memory access functions |
| 30 | */ |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 31 | #include <linux/bitops.h> |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 32 | #include <linux/kasan-checks.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 33 | #include <linux/string.h> |
| 34 | #include <linux/thread_info.h> |
| 35 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 36 | #include <asm/cpufeature.h> |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 37 | #include <asm/processor.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 38 | #include <asm/ptrace.h> |
| 39 | #include <asm/errno.h> |
| 40 | #include <asm/memory.h> |
| 41 | #include <asm/compiler.h> |
| 42 | |
| 43 | #define VERIFY_READ 0 |
| 44 | #define VERIFY_WRITE 1 |
| 45 | |
| 46 | /* |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 47 | * The exception table consists of pairs of relative offsets: the first |
| 48 | * is the relative offset to an instruction that is allowed to fault, |
| 49 | * and the second is the relative offset at which the program should |
| 50 | * continue. No registers are modified, so it is entirely up to the |
| 51 | * continuation code to figure out what to do. |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 52 | * |
| 53 | * All the routines below use bits of fixup code that are out of line |
| 54 | * with the main instruction path. This means when everything is well, |
| 55 | * we don't even have to jump over them. Further, they do not intrude |
| 56 | * on our cache or tlb entries. |
| 57 | */ |
| 58 | |
| 59 | struct exception_table_entry |
| 60 | { |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 61 | int insn, fixup; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 62 | }; |
| 63 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 64 | #define ARCH_HAS_RELATIVE_EXTABLE |
| 65 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 66 | extern int fixup_exception(struct pt_regs *regs); |
| 67 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 68 | #define get_ds() (KERNEL_DS) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 69 | #define get_fs() (current_thread_info()->addr_limit) |
| 70 | |
| 71 | static inline void set_fs(mm_segment_t fs) |
| 72 | { |
| 73 | current_thread_info()->addr_limit = fs; |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 74 | |
Thomas Garnier | b17d6c4 | 2017-06-14 18:12:03 -0700 | [diff] [blame] | 75 | /* On user-mode return, check fs is correct */ |
| 76 | set_thread_flag(TIF_FSCHECK); |
| 77 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 78 | /* |
Mark Rutland | 346edd6 | 2018-04-12 12:11:03 +0100 | [diff] [blame] | 79 | * Prevent a mispredicted conditional call to set_fs from forwarding |
| 80 | * the wrong address limit to access_ok under speculation. |
| 81 | */ |
| 82 | dsb(nsh); |
| 83 | isb(); |
| 84 | |
| 85 | /* |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 86 | * Enable/disable UAO so that copy_to_user() etc can access |
| 87 | * kernel memory with the unprivileged instructions. |
| 88 | */ |
| 89 | if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS) |
| 90 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); |
| 91 | else |
| 92 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO, |
| 93 | CONFIG_ARM64_UAO)); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Michael S. Tsirkin | 967f0e5 | 2015-01-06 15:11:13 +0200 | [diff] [blame] | 96 | #define segment_eq(a, b) ((a) == (b)) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 97 | |
| 98 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 99 | * Test whether a block of memory is a valid user space address. |
| 100 | * Returns 1 if the range is valid, 0 otherwise. |
| 101 | * |
| 102 | * This is equivalent to the following test: |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 103 | * (u65)addr + (u65)size <= (u65)current->addr_limit + 1 |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 104 | */ |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 105 | static inline unsigned long __range_ok(unsigned long addr, unsigned long size) |
| 106 | { |
| 107 | unsigned long limit = current_thread_info()->addr_limit; |
| 108 | |
| 109 | __chk_user_ptr(addr); |
| 110 | asm volatile( |
| 111 | // A + B <= C + 1 for all A,B,C, in four easy steps: |
| 112 | // 1: X = A + B; X' = X % 2^64 |
| 113 | " adds %0, %0, %2\n" |
| 114 | // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 |
| 115 | " csel %1, xzr, %1, hi\n" |
| 116 | // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' |
| 117 | // to compensate for the carry flag being set in step 4. For |
| 118 | // X > 2^64, X' merely has to remain nonzero, which it does. |
| 119 | " csinv %0, %0, xzr, cc\n" |
| 120 | // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 |
| 121 | // comes from the carry in being clear. Otherwise, we are |
| 122 | // testing X' - C == 0, subject to the previous adjustments. |
| 123 | " sbcs xzr, %0, %1\n" |
| 124 | " cset %0, ls\n" |
| 125 | : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc"); |
| 126 | |
| 127 | return addr; |
| 128 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 129 | |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 130 | /* |
Kristina Martsenko | 1d61ccb | 2017-06-06 20:14:09 +0100 | [diff] [blame] | 131 | * When dealing with data aborts, watchpoints, or instruction traps we may end |
| 132 | * up with a tagged userland pointer. Clear the tag to get a sane pointer to |
| 133 | * pass on to access_ok(), for instance. |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 134 | */ |
| 135 | #define untagged_addr(addr) sign_extend64(addr, 55) |
| 136 | |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 137 | #define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 138 | #define user_addr_max get_fs |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 139 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 140 | #define _ASM_EXTABLE(from, to) \ |
| 141 | " .pushsection __ex_table, \"a\"\n" \ |
| 142 | " .align 3\n" \ |
| 143 | " .long (" #from " - .), (" #to " - .)\n" \ |
| 144 | " .popsection\n" |
| 145 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 146 | /* |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 147 | * User access enabling/disabling. |
| 148 | */ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 149 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 150 | static inline void __uaccess_ttbr0_disable(void) |
| 151 | { |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 152 | unsigned long flags, ttbr; |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 153 | |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 154 | local_irq_save(flags); |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 155 | ttbr = read_sysreg(ttbr1_el1); |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 156 | ttbr &= ~TTBR_ASID_MASK; |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 157 | /* reserved_ttbr0 placed at the end of swapper_pg_dir */ |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 158 | write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); |
| 159 | isb(); |
| 160 | /* Set reserved ASID */ |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 161 | write_sysreg(ttbr, ttbr1_el1); |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 162 | isb(); |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 163 | local_irq_restore(flags); |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | static inline void __uaccess_ttbr0_enable(void) |
| 167 | { |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 168 | unsigned long flags, ttbr0, ttbr1; |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 169 | |
| 170 | /* |
| 171 | * Disable interrupts to avoid preemption between reading the 'ttbr0' |
| 172 | * variable and the MSR. A context switch could trigger an ASID |
| 173 | * roll-over and an update of 'ttbr0'. |
| 174 | */ |
| 175 | local_irq_save(flags); |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 176 | ttbr0 = READ_ONCE(current_thread_info()->ttbr0); |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 177 | |
| 178 | /* Restore active ASID */ |
| 179 | ttbr1 = read_sysreg(ttbr1_el1); |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 180 | ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */ |
Will Deacon | d7013ed | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 181 | ttbr1 |= ttbr0 & TTBR_ASID_MASK; |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 182 | write_sysreg(ttbr1, ttbr1_el1); |
| 183 | isb(); |
| 184 | |
| 185 | /* Restore user page table */ |
| 186 | write_sysreg(ttbr0, ttbr0_el1); |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 187 | isb(); |
| 188 | local_irq_restore(flags); |
| 189 | } |
| 190 | |
| 191 | static inline bool uaccess_ttbr0_disable(void) |
| 192 | { |
| 193 | if (!system_uses_ttbr0_pan()) |
| 194 | return false; |
| 195 | __uaccess_ttbr0_disable(); |
| 196 | return true; |
| 197 | } |
| 198 | |
| 199 | static inline bool uaccess_ttbr0_enable(void) |
| 200 | { |
| 201 | if (!system_uses_ttbr0_pan()) |
| 202 | return false; |
| 203 | __uaccess_ttbr0_enable(); |
| 204 | return true; |
| 205 | } |
| 206 | #else |
| 207 | static inline bool uaccess_ttbr0_disable(void) |
| 208 | { |
| 209 | return false; |
| 210 | } |
| 211 | |
| 212 | static inline bool uaccess_ttbr0_enable(void) |
| 213 | { |
| 214 | return false; |
| 215 | } |
| 216 | #endif |
| 217 | |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 218 | #define __uaccess_disable(alt) \ |
| 219 | do { \ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 220 | if (!uaccess_ttbr0_disable()) \ |
| 221 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ |
| 222 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 223 | } while (0) |
| 224 | |
| 225 | #define __uaccess_enable(alt) \ |
| 226 | do { \ |
Marc Zyngier | 093284e | 2016-12-12 13:50:26 +0000 | [diff] [blame] | 227 | if (!uaccess_ttbr0_enable()) \ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 228 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ |
| 229 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 230 | } while (0) |
| 231 | |
| 232 | static inline void uaccess_disable(void) |
| 233 | { |
| 234 | __uaccess_disable(ARM64_HAS_PAN); |
| 235 | } |
| 236 | |
| 237 | static inline void uaccess_enable(void) |
| 238 | { |
| 239 | __uaccess_enable(ARM64_HAS_PAN); |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * These functions are no-ops when UAO is present. |
| 244 | */ |
| 245 | static inline void uaccess_disable_not_uao(void) |
| 246 | { |
| 247 | __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); |
| 248 | } |
| 249 | |
| 250 | static inline void uaccess_enable_not_uao(void) |
| 251 | { |
| 252 | __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); |
| 253 | } |
| 254 | |
| 255 | /* |
Mark Rutland | 891bea9 | 2018-04-12 12:11:01 +0100 | [diff] [blame] | 256 | * Sanitise a uaccess pointer such that it becomes NULL if above the |
| 257 | * current addr_limit. |
| 258 | */ |
| 259 | #define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) |
| 260 | static inline void __user *__uaccess_mask_ptr(const void __user *ptr) |
| 261 | { |
| 262 | void __user *safe_ptr; |
| 263 | |
| 264 | asm volatile( |
| 265 | " bics xzr, %1, %2\n" |
| 266 | " csel %0, %1, xzr, eq\n" |
| 267 | : "=&r" (safe_ptr) |
| 268 | : "r" (ptr), "r" (current_thread_info()->addr_limit) |
| 269 | : "cc"); |
| 270 | |
| 271 | csdb(); |
| 272 | return safe_ptr; |
| 273 | } |
| 274 | |
| 275 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 276 | * The "__xxx" versions of the user access functions do not verify the address |
| 277 | * space - it must have been done previously with a separate "access_ok()" |
| 278 | * call. |
| 279 | * |
| 280 | * The "__xxx_error" versions set the third argument to -EFAULT if an error |
| 281 | * occurs, and leave it unchanged on success. |
| 282 | */ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 283 | #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 284 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 285 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 286 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 287 | "2:\n" \ |
| 288 | " .section .fixup, \"ax\"\n" \ |
| 289 | " .align 2\n" \ |
| 290 | "3: mov %w0, %3\n" \ |
| 291 | " mov %1, #0\n" \ |
| 292 | " b 2b\n" \ |
| 293 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 294 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 295 | : "+r" (err), "=&r" (x) \ |
| 296 | : "r" (addr), "i" (-EFAULT)) |
| 297 | |
| 298 | #define __get_user_err(x, ptr, err) \ |
| 299 | do { \ |
| 300 | unsigned long __gu_val; \ |
| 301 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 302 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 303 | switch (sizeof(*(ptr))) { \ |
| 304 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 305 | __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \ |
| 306 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 307 | break; \ |
| 308 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 309 | __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \ |
| 310 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 311 | break; \ |
| 312 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 313 | __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \ |
| 314 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 315 | break; \ |
| 316 | case 8: \ |
Mark Rutland | f5a861c | 2017-05-03 16:09:38 +0100 | [diff] [blame] | 317 | __get_user_asm("ldr", "ldtr", "%x", __gu_val, (ptr), \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 318 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 319 | break; \ |
| 320 | default: \ |
| 321 | BUILD_BUG(); \ |
| 322 | } \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 323 | uaccess_disable_not_uao(); \ |
Michael S. Tsirkin | 58fff51 | 2014-12-12 01:56:04 +0200 | [diff] [blame] | 324 | (x) = (__force __typeof__(*(ptr)))__gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 325 | } while (0) |
| 326 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 327 | #define __get_user_check(x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 328 | ({ \ |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 329 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 330 | might_fault(); \ |
| 331 | if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \ |
| 332 | __p = uaccess_mask_ptr(__p); \ |
| 333 | __get_user_err((x), __p, (err)); \ |
| 334 | } else { \ |
| 335 | (x) = 0; (err) = -EFAULT; \ |
| 336 | } \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 337 | }) |
| 338 | |
| 339 | #define __get_user_error(x, ptr, err) \ |
| 340 | ({ \ |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 341 | __get_user_check((x), (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 342 | (void)0; \ |
| 343 | }) |
| 344 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 345 | #define __get_user(x, ptr) \ |
| 346 | ({ \ |
| 347 | int __gu_err = 0; \ |
| 348 | __get_user_check((x), (ptr), __gu_err); \ |
| 349 | __gu_err; \ |
| 350 | }) |
| 351 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 352 | #define __get_user_unaligned __get_user |
| 353 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 354 | #define get_user __get_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 355 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 356 | #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 357 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 358 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 359 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 360 | "2:\n" \ |
| 361 | " .section .fixup,\"ax\"\n" \ |
| 362 | " .align 2\n" \ |
| 363 | "3: mov %w0, %3\n" \ |
| 364 | " b 2b\n" \ |
| 365 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 366 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 367 | : "+r" (err) \ |
| 368 | : "r" (x), "r" (addr), "i" (-EFAULT)) |
| 369 | |
| 370 | #define __put_user_err(x, ptr, err) \ |
| 371 | do { \ |
| 372 | __typeof__(*(ptr)) __pu_val = (x); \ |
| 373 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 374 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 375 | switch (sizeof(*(ptr))) { \ |
| 376 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 377 | __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \ |
| 378 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 379 | break; \ |
| 380 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 381 | __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \ |
| 382 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 383 | break; \ |
| 384 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 385 | __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \ |
| 386 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 387 | break; \ |
| 388 | case 8: \ |
Mark Rutland | f5a861c | 2017-05-03 16:09:38 +0100 | [diff] [blame] | 389 | __put_user_asm("str", "sttr", "%x", __pu_val, (ptr), \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 390 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 391 | break; \ |
| 392 | default: \ |
| 393 | BUILD_BUG(); \ |
| 394 | } \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 395 | uaccess_disable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 396 | } while (0) |
| 397 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 398 | #define __put_user_check(x, ptr, err) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 399 | ({ \ |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 400 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
| 401 | might_fault(); \ |
| 402 | if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \ |
| 403 | __p = uaccess_mask_ptr(__p); \ |
| 404 | __put_user_err((x), __p, (err)); \ |
| 405 | } else { \ |
| 406 | (err) = -EFAULT; \ |
| 407 | } \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 408 | }) |
| 409 | |
| 410 | #define __put_user_error(x, ptr, err) \ |
| 411 | ({ \ |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 412 | __put_user_check((x), (ptr), (err)); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 413 | (void)0; \ |
| 414 | }) |
| 415 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 416 | #define __put_user(x, ptr) \ |
| 417 | ({ \ |
| 418 | int __pu_err = 0; \ |
| 419 | __put_user_check((x), (ptr), __pu_err); \ |
| 420 | __pu_err; \ |
| 421 | }) |
| 422 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 423 | #define __put_user_unaligned __put_user |
| 424 | |
Mark Rutland | 4c03928 | 2018-04-12 12:11:04 +0100 | [diff] [blame] | 425 | #define put_user __put_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 426 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 427 | extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); |
| 428 | extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 429 | extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 430 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 431 | static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) |
| 432 | { |
| 433 | kasan_check_write(to, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 434 | check_object_size(to, n, false); |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 435 | return __arch_copy_from_user(to, __uaccess_mask_ptr(from), n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) |
| 439 | { |
| 440 | kasan_check_read(from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 441 | check_object_size(from, n, true); |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 442 | return __arch_copy_to_user(__uaccess_mask_ptr(to), from, n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 443 | } |
| 444 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 445 | static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) |
| 446 | { |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 447 | unsigned long res = n; |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 448 | kasan_check_write(to, n); |
| 449 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 450 | if (access_ok(VERIFY_READ, from, n)) { |
| 451 | check_object_size(to, n, false); |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 452 | res = __arch_copy_from_user(to, from, n); |
| 453 | } |
| 454 | if (unlikely(res)) |
| 455 | memset(to + (n - res), 0, res); |
| 456 | return res; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) |
| 460 | { |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 461 | kasan_check_read(from, n); |
| 462 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 463 | if (access_ok(VERIFY_WRITE, to, n)) { |
| 464 | check_object_size(from, n, true); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 465 | n = __arch_copy_to_user(to, from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 466 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 467 | return n; |
| 468 | } |
| 469 | |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 470 | static inline unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 471 | { |
| 472 | if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 473 | n = __arch_copy_in_user(__uaccess_mask_ptr(to), __uaccess_mask_ptr(from), n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 474 | return n; |
| 475 | } |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 476 | #define copy_in_user __copy_in_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 477 | |
| 478 | #define __copy_to_user_inatomic __copy_to_user |
| 479 | #define __copy_from_user_inatomic __copy_from_user |
| 480 | |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 481 | extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); |
| 482 | static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 483 | { |
| 484 | if (access_ok(VERIFY_WRITE, to, n)) |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 485 | n = __arch_clear_user(__uaccess_mask_ptr(to), n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 486 | return n; |
| 487 | } |
Mark Rutland | 4504c5c | 2018-04-12 12:11:05 +0100 | [diff] [blame] | 488 | #define clear_user __clear_user |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 489 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 490 | extern long strncpy_from_user(char *dest, const char __user *src, long count); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 491 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 492 | extern __must_check long strlen_user(const char __user *str); |
| 493 | extern __must_check long strnlen_user(const char __user *str, long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 494 | |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 495 | #else /* __ASSEMBLY__ */ |
| 496 | |
| 497 | #include <asm/assembler.h> |
| 498 | |
| 499 | /* |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 500 | * User access enabling/disabling macros. |
| 501 | */ |
| 502 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 503 | .macro __uaccess_ttbr0_disable, tmp1 |
| 504 | mrs \tmp1, ttbr1_el1 // swapper_pg_dir |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 505 | bic \tmp1, \tmp1, #TTBR_ASID_MASK |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 506 | add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir |
| 507 | msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 |
| 508 | isb |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 509 | sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 510 | msr ttbr1_el1, \tmp1 // set reserved ASID |
| 511 | isb |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 512 | .endm |
| 513 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 514 | .macro __uaccess_ttbr0_enable, tmp1, tmp2 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 515 | get_thread_info \tmp1 |
| 516 | ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 517 | mrs \tmp2, ttbr1_el1 |
| 518 | extr \tmp2, \tmp2, \tmp1, #48 |
| 519 | ror \tmp2, \tmp2, #16 |
| 520 | msr ttbr1_el1, \tmp2 // set the active ASID |
| 521 | isb |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 522 | msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 |
| 523 | isb |
| 524 | .endm |
| 525 | |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 526 | .macro uaccess_ttbr0_disable, tmp1, tmp2 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 527 | alternative_if_not ARM64_HAS_PAN |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 528 | save_and_disable_irq \tmp2 // avoid preemption |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 529 | __uaccess_ttbr0_disable \tmp1 |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 530 | restore_irq \tmp2 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 531 | alternative_else_nop_endif |
| 532 | .endm |
| 533 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 534 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 535 | alternative_if_not ARM64_HAS_PAN |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 536 | save_and_disable_irq \tmp3 // avoid preemption |
| 537 | __uaccess_ttbr0_enable \tmp1, \tmp2 |
| 538 | restore_irq \tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 539 | alternative_else_nop_endif |
| 540 | .endm |
| 541 | #else |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 542 | .macro uaccess_ttbr0_disable, tmp1, tmp2 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 543 | .endm |
| 544 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 545 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 546 | .endm |
| 547 | #endif |
| 548 | |
| 549 | /* |
| 550 | * These macros are no-ops when UAO is present. |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 551 | */ |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 552 | .macro uaccess_disable_not_uao, tmp1, tmp2 |
| 553 | uaccess_ttbr0_disable \tmp1, \tmp2 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 554 | alternative_if ARM64_ALT_PAN_NOT_UAO |
| 555 | SET_PSTATE_PAN(1) |
| 556 | alternative_else_nop_endif |
| 557 | .endm |
| 558 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 559 | .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3 |
| 560 | uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 561 | alternative_if ARM64_ALT_PAN_NOT_UAO |
| 562 | SET_PSTATE_PAN(0) |
| 563 | alternative_else_nop_endif |
| 564 | .endm |
| 565 | |
| 566 | #endif /* __ASSEMBLY__ */ |
| 567 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 568 | #endif /* __ASM_UACCESS_H */ |