Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * numa.c - Low-level PCI access for NUMA-Q machines |
| 3 | */ |
| 4 | |
| 5 | #include <linux/pci.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/nodemask.h> |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 8 | #include <mach_apic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #include "pci.h" |
| 10 | |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 11 | #define XQUAD_PORTIO_BASE 0xfe400000 |
| 12 | #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */ |
| 13 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #define BUS2QUAD(global) (mp_bus_id_to_node[global]) |
Alexey Starikovskiy | e129cb4 | 2008-03-11 22:55:42 +0300 | [diff] [blame^] | 15 | |
| 16 | int mp_bus_id_to_local[MAX_MP_BUSSES]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #define BUS2LOCAL(global) (mp_bus_id_to_local[global]) |
Alexey Starikovskiy | 6079d2d | 2008-03-11 19:45:48 +0300 | [diff] [blame] | 18 | |
| 19 | int quad_local_to_mp_bus_id [NR_CPUS/4][4]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local]) |
| 21 | |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 22 | extern void *xquad_portio; /* Where the IO area was mapped */ |
| 23 | #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port) |
| 24 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \ |
| 26 | (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3)) |
| 27 | |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 28 | static void write_cf8(unsigned bus, unsigned devfn, unsigned reg) |
| 29 | { |
| 30 | unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg); |
| 31 | if (xquad_portio) |
| 32 | writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus))); |
| 33 | else |
| 34 | outl(val, 0xCF8); |
| 35 | } |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | static int pci_conf1_mq_read(unsigned int seg, unsigned int bus, |
| 38 | unsigned int devfn, int reg, int len, u32 *value) |
| 39 | { |
| 40 | unsigned long flags; |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 41 | void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
| 43 | if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) |
| 44 | return -EINVAL; |
| 45 | |
| 46 | spin_lock_irqsave(&pci_config_lock, flags); |
| 47 | |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 48 | write_cf8(bus, devfn, reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
| 50 | switch (len) { |
| 51 | case 1: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 52 | if (xquad_portio) |
| 53 | *value = readb(adr + (reg & 3)); |
| 54 | else |
| 55 | *value = inb(0xCFC + (reg & 3)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | break; |
| 57 | case 2: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 58 | if (xquad_portio) |
| 59 | *value = readw(adr + (reg & 2)); |
| 60 | else |
| 61 | *value = inw(0xCFC + (reg & 2)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | break; |
| 63 | case 4: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 64 | if (xquad_portio) |
| 65 | *value = readl(adr); |
| 66 | else |
| 67 | *value = inl(0xCFC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | break; |
| 69 | } |
| 70 | |
| 71 | spin_unlock_irqrestore(&pci_config_lock, flags); |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | static int pci_conf1_mq_write(unsigned int seg, unsigned int bus, |
| 77 | unsigned int devfn, int reg, int len, u32 value) |
| 78 | { |
| 79 | unsigned long flags; |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 80 | void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
| 82 | if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) |
| 83 | return -EINVAL; |
| 84 | |
| 85 | spin_lock_irqsave(&pci_config_lock, flags); |
| 86 | |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 87 | write_cf8(bus, devfn, reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | |
| 89 | switch (len) { |
| 90 | case 1: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 91 | if (xquad_portio) |
| 92 | writeb(value, adr + (reg & 3)); |
| 93 | else |
| 94 | outb((u8)value, 0xCFC + (reg & 3)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | break; |
| 96 | case 2: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 97 | if (xquad_portio) |
| 98 | writew(value, adr + (reg & 2)); |
| 99 | else |
| 100 | outw((u16)value, 0xCFC + (reg & 2)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | break; |
| 102 | case 4: |
Andi Kleen | c7e844f | 2008-02-04 16:48:03 +0100 | [diff] [blame] | 103 | if (xquad_portio) |
| 104 | writel(value, adr + reg); |
| 105 | else |
| 106 | outl((u32)value, 0xCFC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | break; |
| 108 | } |
| 109 | |
| 110 | spin_unlock_irqrestore(&pci_config_lock, flags); |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | #undef PCI_CONF1_MQ_ADDRESS |
| 116 | |
| 117 | static struct pci_raw_ops pci_direct_conf1_mq = { |
| 118 | .read = pci_conf1_mq_read, |
| 119 | .write = pci_conf1_mq_write |
| 120 | }; |
| 121 | |
| 122 | |
| 123 | static void __devinit pci_fixup_i450nx(struct pci_dev *d) |
| 124 | { |
| 125 | /* |
| 126 | * i450NX -- Find and scan all secondary buses on all PXB's. |
| 127 | */ |
| 128 | int pxb, reg; |
| 129 | u8 busno, suba, subb; |
| 130 | int quad = BUS2QUAD(d->bus->number); |
| 131 | |
| 132 | printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); |
| 133 | reg = 0xd0; |
| 134 | for(pxb=0; pxb<2; pxb++) { |
| 135 | pci_read_config_byte(d, reg++, &busno); |
| 136 | pci_read_config_byte(d, reg++, &suba); |
| 137 | pci_read_config_byte(d, reg++, &subb); |
| 138 | DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); |
Muli Ben-Yehuda | 73c59af | 2007-08-10 13:01:19 -0700 | [diff] [blame] | 139 | if (busno) { |
| 140 | /* Bus A */ |
| 141 | pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno)); |
| 142 | } |
| 143 | if (suba < subb) { |
| 144 | /* Bus B */ |
| 145 | pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1)); |
| 146 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | } |
| 148 | pcibios_last_bus = -1; |
| 149 | } |
| 150 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); |
| 151 | |
| 152 | static int __init pci_numa_init(void) |
| 153 | { |
| 154 | int quad; |
| 155 | |
| 156 | raw_pci_ops = &pci_direct_conf1_mq; |
| 157 | |
| 158 | if (pcibios_scanned++) |
| 159 | return 0; |
| 160 | |
| 161 | pci_root_bus = pcibios_scan_root(0); |
Rajesh Shah | c431ada | 2005-04-28 00:25:45 -0700 | [diff] [blame] | 162 | if (pci_root_bus) |
| 163 | pci_bus_add_devices(pci_root_bus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | if (num_online_nodes() > 1) |
| 165 | for_each_online_node(quad) { |
| 166 | if (quad == 0) |
| 167 | continue; |
| 168 | printk("Scanning PCI bus %d for quad %d\n", |
| 169 | QUADLOCAL2BUS(quad,0), quad); |
Muli Ben-Yehuda | 73c59af | 2007-08-10 13:01:19 -0700 | [diff] [blame] | 170 | pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | } |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | subsys_initcall(pci_numa_init); |