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gerrit-public.fairphone.software / kernel / msm-4.9 / e16415313c9b00b1adc313e85c2c8a81febe0b98 / . / arch / arm / boot / dts / imx6q.dtsi
blob: 095333b5b50f5c6a307970d98ac8e8f8aacdf368 [file] [log] [blame]
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]12#include "imx6q-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
24 /* kHz uV */
25 1200000 1275000
26 996000 1250000
27 792000 1150000
28 396000 950000
29 >;
30 clock-latency = <61036>; /* two CLK32 periods */
31 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
32 <&clks 17>, <&clks 170>;
33 clock-names = "arm", "pll2_pfd2_396m", "step",
34 "pll1_sw", "pll1_sys";
35 arm-supply = <&reg_arm>;
36 pu-supply = <&reg_pu>;
37 soc-supply = <&reg_soc>;
38 };
39
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 reg = <1>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@2 {
47 compatible = "arm,cortex-a9";
48 reg = <2>;
49 next-level-cache = <&L2>;
50 };
51
52 cpu@3 {
53 compatible = "arm,cortex-a9";
54 reg = <3>;
55 next-level-cache = <&L2>;
56 };
57 };
58
59 soc {
60 aips-bus@02000000 { /* AIPS1 */
61 spba-bus@02000000 {
62 ecspi5: ecspi@02018000 {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
66 reg = <0x02018000 0x4000>;
67 interrupts = <0 35 0x04>;
68 clocks = <&clks 116>, <&clks 116>;
69 clock-names = "ipg", "per";
70 status = "disabled";
71 };
72 };
73
74 iomuxc: iomuxc@020e0000 {
75 compatible = "fsl,imx6q-iomuxc";
76 reg = <0x020e0000 0x4000>;
77
78 /* shared pinctrl settings */
79 audmux {
80 pinctrl_audmux_1: audmux-1 {
81 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]82 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
83 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
84 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
85 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]86 >;
87 };
88 };
89
90 ecspi1 {
91 pinctrl_ecspi1_1: ecspi1grp-1 {
92 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]93 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
94 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
95 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]96 >;
97 };
98 };
99
100 enet {
101 pinctrl_enet_1: enetgrp-1 {
102 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]103 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
104 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
105 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
106 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
107 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
108 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
109 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
110 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
111 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
112 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
113 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
114 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
115 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
116 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
117 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
118 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]119 >;
120 };
121
122 pinctrl_enet_2: enetgrp-2 {
123 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]124 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
125 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
126 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
127 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
128 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
129 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
130 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
131 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
132 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
133 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
134 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
135 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
136 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
137 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
138 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]139 >;
140 };
141 };
142
143 gpmi-nand {
144 pinctrl_gpmi_nand_1: gpmi-nand-1 {
145 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]146 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
147 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
148 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
149 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
150 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
151 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
152 MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
153 MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
154 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
155 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
156 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
157 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
158 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
159 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
160 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
161 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
162 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
163 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
164 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]165 >;
166 };
167 };
168
169 i2c1 {
170 pinctrl_i2c1_1: i2c1grp-1 {
171 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]172 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
173 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]174 >;
175 };
176 };
177
178 uart1 {
179 pinctrl_uart1_1: uart1grp-1 {
180 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]181 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
182 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]183 >;
184 };
185 };
186
187 uart2 {
188 pinctrl_uart2_1: uart2grp-1 {
189 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]190 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
191 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]192 >;
193 };
194 };
195
196 uart4 {
197 pinctrl_uart4_1: uart4grp-1 {
198 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]199 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
200 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]201 >;
202 };
203 };
204
205 usbotg {
206 pinctrl_usbotg_1: usbotggrp-1 {
207 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]208 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]209 >;
210 };
Peter Chena10c22e2013-02-18 10:06:44 +0800[diff] [blame]211
212 pinctrl_usbotg_2: usbotggrp-2 {
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]213 fsl,pins = <
214 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
Peter Chena10c22e2013-02-18 10:06:44 +0800[diff] [blame]215 >;
216 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]217 };
218
219 usdhc2 {
220 pinctrl_usdhc2_1: usdhc2grp-1 {
221 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]222 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
223 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
224 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
225 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
226 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
227 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
228 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
229 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
230 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
231 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]232 >;
233 };
234 };
235
236 usdhc3 {
237 pinctrl_usdhc3_1: usdhc3grp-1 {
238 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]239 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
240 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
241 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
242 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
243 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
244 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
245 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
246 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
247 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
248 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]249 >;
250 };
251
252 pinctrl_usdhc3_2: usdhc3grp-2 {
253 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]254 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
255 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
256 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
257 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
258 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
259 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]260 >;
261 };
262 };
263
264 usdhc4 {
265 pinctrl_usdhc4_1: usdhc4grp-1 {
266 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]267 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
268 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
269 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
270 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
271 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
272 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
273 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
274 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
275 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
276 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]277 >;
278 };
279
280 pinctrl_usdhc4_2: usdhc4grp-2 {
281 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame^]282 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
283 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
284 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
285 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
286 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
287 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]288 >;
289 };
290 };
291 };
292 };
293
294 ipu2: ipu@02800000 {
295 #crtc-cells = <1>;
296 compatible = "fsl,imx6q-ipu";
297 reg = <0x02800000 0x400000>;
298 interrupts = <0 8 0x4 0 7 0x4>;
299 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
300 clock-names = "bus", "di0", "di1";
301 };
302 };
303};