David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2011, 2012 Cavium, Inc. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/spi/spi.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/of.h> |
| 17 | |
| 18 | #include <asm/octeon/octeon.h> |
| 19 | #include <asm/octeon/cvmx-mpi-defs.h> |
| 20 | |
| 21 | #define OCTEON_SPI_CFG 0 |
| 22 | #define OCTEON_SPI_STS 0x08 |
| 23 | #define OCTEON_SPI_TX 0x10 |
| 24 | #define OCTEON_SPI_DAT0 0x80 |
| 25 | |
| 26 | #define OCTEON_SPI_MAX_BYTES 9 |
| 27 | |
| 28 | #define OCTEON_SPI_MAX_CLOCK_HZ 16000000 |
| 29 | |
| 30 | struct octeon_spi { |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 31 | u64 register_base; |
| 32 | u64 last_cfg; |
| 33 | u64 cs_enax; |
| 34 | }; |
| 35 | |
| 36 | struct octeon_spi_setup { |
| 37 | u32 max_speed_hz; |
| 38 | u8 chip_select; |
| 39 | u8 mode; |
| 40 | u8 bits_per_word; |
| 41 | }; |
| 42 | |
| 43 | static void octeon_spi_wait_ready(struct octeon_spi *p) |
| 44 | { |
| 45 | union cvmx_mpi_sts mpi_sts; |
| 46 | unsigned int loops = 0; |
| 47 | |
| 48 | do { |
| 49 | if (loops++) |
| 50 | __delay(500); |
| 51 | mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS); |
| 52 | } while (mpi_sts.s.busy); |
| 53 | } |
| 54 | |
| 55 | static int octeon_spi_do_transfer(struct octeon_spi *p, |
| 56 | struct spi_message *msg, |
| 57 | struct spi_transfer *xfer, |
| 58 | bool last_xfer) |
| 59 | { |
| 60 | union cvmx_mpi_cfg mpi_cfg; |
| 61 | union cvmx_mpi_tx mpi_tx; |
| 62 | unsigned int clkdiv; |
| 63 | unsigned int speed_hz; |
| 64 | int mode; |
| 65 | bool cpha, cpol; |
| 66 | int bits_per_word; |
| 67 | const u8 *tx_buf; |
| 68 | u8 *rx_buf; |
| 69 | int len; |
| 70 | int i; |
| 71 | |
| 72 | struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi); |
| 73 | |
| 74 | speed_hz = msg_setup->max_speed_hz; |
| 75 | mode = msg_setup->mode; |
| 76 | cpha = mode & SPI_CPHA; |
| 77 | cpol = mode & SPI_CPOL; |
| 78 | bits_per_word = msg_setup->bits_per_word; |
| 79 | |
| 80 | if (xfer->speed_hz) |
| 81 | speed_hz = xfer->speed_hz; |
| 82 | if (xfer->bits_per_word) |
| 83 | bits_per_word = xfer->bits_per_word; |
| 84 | |
| 85 | if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ) |
| 86 | speed_hz = OCTEON_SPI_MAX_CLOCK_HZ; |
| 87 | |
| 88 | clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz); |
| 89 | |
| 90 | mpi_cfg.u64 = 0; |
| 91 | |
| 92 | mpi_cfg.s.clkdiv = clkdiv; |
| 93 | mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0; |
| 94 | mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0; |
| 95 | mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0; |
| 96 | mpi_cfg.s.idlelo = cpha != cpol; |
| 97 | mpi_cfg.s.cslate = cpha ? 1 : 0; |
| 98 | mpi_cfg.s.enable = 1; |
| 99 | |
| 100 | if (msg_setup->chip_select < 4) |
| 101 | p->cs_enax |= 1ull << (12 + msg_setup->chip_select); |
| 102 | mpi_cfg.u64 |= p->cs_enax; |
| 103 | |
| 104 | if (mpi_cfg.u64 != p->last_cfg) { |
| 105 | p->last_cfg = mpi_cfg.u64; |
| 106 | cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64); |
| 107 | } |
| 108 | tx_buf = xfer->tx_buf; |
| 109 | rx_buf = xfer->rx_buf; |
| 110 | len = xfer->len; |
| 111 | while (len > OCTEON_SPI_MAX_BYTES) { |
| 112 | for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { |
| 113 | u8 d; |
| 114 | if (tx_buf) |
| 115 | d = *tx_buf++; |
| 116 | else |
| 117 | d = 0; |
| 118 | cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); |
| 119 | } |
| 120 | mpi_tx.u64 = 0; |
| 121 | mpi_tx.s.csid = msg_setup->chip_select; |
| 122 | mpi_tx.s.leavecs = 1; |
| 123 | mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; |
| 124 | mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; |
| 125 | cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); |
| 126 | |
| 127 | octeon_spi_wait_ready(p); |
| 128 | if (rx_buf) |
| 129 | for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) { |
| 130 | u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); |
| 131 | *rx_buf++ = (u8)v; |
| 132 | } |
| 133 | len -= OCTEON_SPI_MAX_BYTES; |
| 134 | } |
| 135 | |
| 136 | for (i = 0; i < len; i++) { |
| 137 | u8 d; |
| 138 | if (tx_buf) |
| 139 | d = *tx_buf++; |
| 140 | else |
| 141 | d = 0; |
| 142 | cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); |
| 143 | } |
| 144 | |
| 145 | mpi_tx.u64 = 0; |
| 146 | mpi_tx.s.csid = msg_setup->chip_select; |
| 147 | if (last_xfer) |
| 148 | mpi_tx.s.leavecs = xfer->cs_change; |
| 149 | else |
| 150 | mpi_tx.s.leavecs = !xfer->cs_change; |
| 151 | mpi_tx.s.txnum = tx_buf ? len : 0; |
| 152 | mpi_tx.s.totnum = len; |
| 153 | cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64); |
| 154 | |
| 155 | octeon_spi_wait_ready(p); |
| 156 | if (rx_buf) |
| 157 | for (i = 0; i < len; i++) { |
| 158 | u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i)); |
| 159 | *rx_buf++ = (u8)v; |
| 160 | } |
| 161 | |
| 162 | if (xfer->delay_usecs) |
| 163 | udelay(xfer->delay_usecs); |
| 164 | |
| 165 | return xfer->len; |
| 166 | } |
| 167 | |
| 168 | static int octeon_spi_validate_bpw(struct spi_device *spi, u32 speed) |
| 169 | { |
| 170 | switch (speed) { |
| 171 | case 8: |
| 172 | break; |
| 173 | default: |
| 174 | dev_err(&spi->dev, "Error: %d bits per word not supported\n", |
| 175 | speed); |
| 176 | return -EINVAL; |
| 177 | } |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | static int octeon_spi_transfer_one_message(struct spi_master *master, |
| 182 | struct spi_message *msg) |
| 183 | { |
| 184 | struct octeon_spi *p = spi_master_get_devdata(master); |
| 185 | unsigned int total_len = 0; |
| 186 | int status = 0; |
| 187 | struct spi_transfer *xfer; |
| 188 | |
| 189 | /* |
| 190 | * We better have set the configuration via a call to .setup |
| 191 | * before we get here. |
| 192 | */ |
| 193 | if (spi_get_ctldata(msg->spi) == NULL) { |
| 194 | status = -EINVAL; |
| 195 | goto err; |
| 196 | } |
| 197 | |
| 198 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 199 | if (xfer->bits_per_word) { |
| 200 | status = octeon_spi_validate_bpw(msg->spi, |
| 201 | xfer->bits_per_word); |
| 202 | if (status) |
| 203 | goto err; |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 208 | bool last_xfer = &xfer->transfer_list == msg->transfers.prev; |
| 209 | int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); |
| 210 | if (r < 0) { |
| 211 | status = r; |
| 212 | goto err; |
| 213 | } |
| 214 | total_len += r; |
| 215 | } |
| 216 | err: |
| 217 | msg->status = status; |
| 218 | msg->actual_length = total_len; |
| 219 | spi_finalize_current_message(master); |
| 220 | return status; |
| 221 | } |
| 222 | |
| 223 | static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi) |
| 224 | { |
| 225 | struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL); |
| 226 | if (!setup) |
| 227 | return NULL; |
| 228 | |
| 229 | setup->max_speed_hz = spi->max_speed_hz; |
| 230 | setup->chip_select = spi->chip_select; |
| 231 | setup->mode = spi->mode; |
| 232 | setup->bits_per_word = spi->bits_per_word; |
| 233 | return setup; |
| 234 | } |
| 235 | |
| 236 | static int octeon_spi_setup(struct spi_device *spi) |
| 237 | { |
| 238 | int r; |
| 239 | struct octeon_spi_setup *new_setup; |
| 240 | struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); |
| 241 | |
| 242 | r = octeon_spi_validate_bpw(spi, spi->bits_per_word); |
| 243 | if (r) |
| 244 | return r; |
| 245 | |
| 246 | new_setup = octeon_spi_new_setup(spi); |
| 247 | if (!new_setup) |
| 248 | return -ENOMEM; |
| 249 | |
| 250 | spi_set_ctldata(spi, new_setup); |
| 251 | kfree(old_setup); |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static void octeon_spi_cleanup(struct spi_device *spi) |
| 257 | { |
| 258 | struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); |
| 259 | spi_set_ctldata(spi, NULL); |
| 260 | kfree(old_setup); |
| 261 | } |
| 262 | |
| 263 | static int octeon_spi_nop_transfer_hardware(struct spi_master *master) |
| 264 | { |
| 265 | return 0; |
| 266 | } |
| 267 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 268 | static int octeon_spi_probe(struct platform_device *pdev) |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 269 | { |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 270 | struct resource *res_mem; |
| 271 | struct spi_master *master; |
| 272 | struct octeon_spi *p; |
| 273 | int err = -ENOENT; |
| 274 | |
| 275 | master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi)); |
| 276 | if (!master) |
| 277 | return -ENOMEM; |
| 278 | p = spi_master_get_devdata(master); |
Axel Lin | e1b18ea | 2013-08-05 15:53:32 +0800 | [diff] [blame^] | 279 | platform_set_drvdata(pdev, master); |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 280 | |
| 281 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 282 | |
| 283 | if (res_mem == NULL) { |
| 284 | dev_err(&pdev->dev, "found no memory resource\n"); |
| 285 | err = -ENXIO; |
| 286 | goto fail; |
| 287 | } |
| 288 | if (!devm_request_mem_region(&pdev->dev, res_mem->start, |
| 289 | resource_size(res_mem), res_mem->name)) { |
| 290 | dev_err(&pdev->dev, "request_mem_region failed\n"); |
| 291 | goto fail; |
| 292 | } |
| 293 | p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, |
| 294 | resource_size(res_mem)); |
| 295 | |
| 296 | /* Dynamic bus numbering */ |
| 297 | master->bus_num = -1; |
| 298 | master->num_chipselect = 4; |
| 299 | master->mode_bits = SPI_CPHA | |
| 300 | SPI_CPOL | |
| 301 | SPI_CS_HIGH | |
| 302 | SPI_LSB_FIRST | |
| 303 | SPI_3WIRE; |
| 304 | |
| 305 | master->setup = octeon_spi_setup; |
| 306 | master->cleanup = octeon_spi_cleanup; |
| 307 | master->prepare_transfer_hardware = octeon_spi_nop_transfer_hardware; |
| 308 | master->transfer_one_message = octeon_spi_transfer_one_message; |
| 309 | master->unprepare_transfer_hardware = octeon_spi_nop_transfer_hardware; |
| 310 | |
| 311 | master->dev.of_node = pdev->dev.of_node; |
| 312 | err = spi_register_master(master); |
| 313 | if (err) { |
| 314 | dev_err(&pdev->dev, "register master failed: %d\n", err); |
| 315 | goto fail; |
| 316 | } |
| 317 | |
| 318 | dev_info(&pdev->dev, "OCTEON SPI bus driver\n"); |
| 319 | |
| 320 | return 0; |
| 321 | fail: |
| 322 | spi_master_put(master); |
| 323 | return err; |
| 324 | } |
| 325 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 326 | static int octeon_spi_remove(struct platform_device *pdev) |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 327 | { |
Axel Lin | e1b18ea | 2013-08-05 15:53:32 +0800 | [diff] [blame^] | 328 | struct spi_master *master = platform_get_drvdata(pdev); |
| 329 | struct octeon_spi *p = spi_master_get_devdata(master); |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 330 | u64 register_base = p->register_base; |
| 331 | |
Axel Lin | e1b18ea | 2013-08-05 15:53:32 +0800 | [diff] [blame^] | 332 | spi_unregister_master(master); |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 333 | |
| 334 | /* Clear the CSENA* and put everything in a known state. */ |
| 335 | cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0); |
| 336 | |
| 337 | return 0; |
| 338 | } |
| 339 | |
| 340 | static struct of_device_id octeon_spi_match[] = { |
| 341 | { .compatible = "cavium,octeon-3010-spi", }, |
| 342 | {}, |
| 343 | }; |
| 344 | MODULE_DEVICE_TABLE(of, octeon_spi_match); |
| 345 | |
| 346 | static struct platform_driver octeon_spi_driver = { |
| 347 | .driver = { |
| 348 | .name = "spi-octeon", |
| 349 | .owner = THIS_MODULE, |
| 350 | .of_match_table = octeon_spi_match, |
| 351 | }, |
| 352 | .probe = octeon_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 353 | .remove = octeon_spi_remove, |
David Daney | 6b52c00 | 2012-08-22 12:25:07 -0700 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | module_platform_driver(octeon_spi_driver); |
| 357 | |
| 358 | MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver"); |
| 359 | MODULE_AUTHOR("David Daney"); |
| 360 | MODULE_LICENSE("GPL"); |