blob: ea385bd3f02cdd832ca44b220816b3b4bb7a86b5 [file] [log] [blame]
Teng Fei Fanbc333fe2018-05-18 18:11:12 +08001/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include "sdm670-qrd.dtsi"
13#include "sdm670-external-codec.dtsi"
Pengfei Liu891486d2018-05-22 17:33:17 +080014#include "sda670-camera-sensor-hdk.dtsi"
Teng Fei Fanbc333fe2018-05-18 18:11:12 +080015
16&dsi_dual_nt36850_truly_cmd_display {
17 /delete-property/ qcom,dsi-display-active;
18};
19
c_hshenff399b02018-06-20 13:52:54 +080020&qrd_batterydata {
21 #include "fg-gen3-batterydata-mlp466076-3250mah.dtsi"
22};
23
Teng Fei Fanbc333fe2018-05-18 18:11:12 +080024&dsi_hx8399_truly_cmd {
25 qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
26 qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
27 qcom,mdss-dsi-bl-min-level = <1>;
28 qcom,mdss-dsi-bl-max-level = <4095>;
29 qcom,panel-mode-gpio = <&tlmm 76 0>;
30 qcom,mdss-dsi-mode-sel-gpio-state = "single_port";
31 qcom,platform-reset-gpio = <&tlmm 75 0>;
32 qcom,platform-te-gpio = <&tlmm 10 0>;
33};
34
35&dsi_hx8399_truly_cmd_display {
36 qcom,dsi-display-active;
37};
Can Guoadb8ebf2018-05-22 00:57:05 -070038
Meng Wangc105f692018-05-23 15:15:31 +080039&tavil_snd {
40 qcom,model = "sdm670-tavil-hdk-snd-card";
41 com,audio-routing =
42 "AIF4 VI", "MCLK",
43 "RX_BIAS", "MCLK",
44 "MADINPUT", "MCLK",
45 "AMIC2", "MIC BIAS2",
46 "MIC BIAS2", "Headset Mic",
47 "DMIC0", "MIC BIAS1",
48 "MIC BIAS1", "Digital Mic0",
49 "DMIC1", "MIC BIAS1",
50 "MIC BIAS1", "Digital Mic1",
51 "DMIC3", "MIC BIAS3",
52 "MIC BIAS3", "Digital Mic3",
53 "DMIC4", "MIC BIAS4",
54 "MIC BIAS4", "Digital Mic4",
55 "SpkrLeft IN", "SPK1 OUT";
56
57 qcom,wsa-max-devs = <1>;
58 qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>;
59 qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
60};
61
Can Guoadb8ebf2018-05-22 00:57:05 -070062&ufsphy_mem {
63 compatible = "qcom,ufs-phy-qmp-v3";
64
65 vdda-phy-supply = <&pm660l_l1>; /* 0.88v */
66 vdda-pll-supply = <&pm660_l1>; /* 1.2v */
67 vdda-phy-max-microamp = <62900>;
68 vdda-pll-max-microamp = <18300>;
69
70 status = "ok";
71};
72
73&ufshc_mem {
74 vdd-hba-supply = <&ufs_phy_gdsc>;
75 vdd-hba-fixed-regulator;
76 vcc-supply = <&pm660l_l4>;
77 vcc-voltage-level = <2960000 2960000>;
78 vccq2-supply = <&pm660_l8>;
79 vcc-max-microamp = <600000>;
80 vccq2-max-microamp = <600000>;
81
82 qcom,vddp-ref-clk-supply = <&pm660_l1>;
83 qcom,vddp-ref-clk-max-microamp = <100>;
84
85 status = "ok";
86};
Liangliang Lu280fbb72018-06-28 14:54:30 +080087
88&qusb_phy0 {
89 qcom,qusb-phy-host-init-seq =
90 /* <value reg_offset> */
91 <0x23 0x210 /* PWR_CTRL1 */
92 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
93 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
94 0x80 0x2c /* PLL_CMODE */
95 0x0a 0x184 /* PLL_LOCK_DELAY */
96 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
97 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
98 0x20 0x198 /* PLL_BIAS_CONTROL_2 */
99 0x21 0x214 /* PWR_CTRL2 */
Liangliang Luc40b40a2018-07-26 17:13:11 +0800100 0x0f 0x220 /* IMP_CTRL1 */
Liangliang Lu280fbb72018-06-28 14:54:30 +0800101 0x58 0x224 /* IMP_CTRL2 */
Liangliang Luc40b40a2018-07-26 17:13:11 +0800102 0xc5 0x240 /* TUNE1 */
Liangliang Lu280fbb72018-06-28 14:54:30 +0800103 0x29 0x244 /* TUNE2 */
104 0xca 0x248 /* TUNE3 */
105 0x04 0x24c /* TUNE4 */
106 0x03 0x250 /* TUNE5 */
107 0x00 0x23c /* CHG_CTRL2 */
108 0x22 0x210>; /* PWR_CTRL1 */
109 qcom,qusb-phy-init-seq =
110 /* <value reg_offset> */
111 <0x23 0x210 /* PWR_CTRL1 */
112 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
113 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
114 0x80 0x2c /* PLL_CMODE */
115 0x0a 0x184 /* PLL_LOCK_DELAY */
116 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
117 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
118 0x20 0x198 /* PLL_BIAS_CONTROL_2 */
119 0x21 0x214 /* PWR_CTRL2 */
Liangliang Luc40b40a2018-07-26 17:13:11 +0800120 0x00 0x220 /* IMP_CTRL1 */
Liangliang Lu280fbb72018-06-28 14:54:30 +0800121 0x58 0x224 /* IMP_CTRL2 */
Liangliang Luc40b40a2018-07-26 17:13:11 +0800122 0x67 0x240 /* TUNE1 */
Liangliang Lu280fbb72018-06-28 14:54:30 +0800123 0x29 0x244 /* TUNE2 */
124 0xca 0x248 /* TUNE3 */
125 0x04 0x24c /* TUNE4 */
126 0x03 0x250 /* TUNE5 */
127 0x00 0x23c /* CHG_CTRL2 */
128 0x22 0x210>; /* PWR_CTRL1 */
129};