blob: 7985982ab4e9d04d493df3ed856b26007b9a1d8c [file] [log] [blame]
Stephen Boyd6d00b562014-01-15 10:47:29 -08001/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/clk-provider.h>
23#include <linux/regmap.h>
24#include <linux/reset-controller.h>
25
26#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28
Stephen Boyd49fc8252014-03-21 17:59:37 -070029#include "common.h"
Stephen Boyd6d00b562014-01-15 10:47:29 -080030#include "clk-regmap.h"
31#include "clk-pll.h"
32#include "clk-rcg.h"
33#include "clk-branch.h"
34#include "reset.h"
35
36#define P_PXO 0
37#define P_PLL8 1
38#define P_PLL2 2
39#define P_PLL3 3
40
Stephen Boydff207832014-07-08 18:36:06 -070041#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
42
Stephen Boyd6d00b562014-01-15 10:47:29 -080043static u8 mmcc_pxo_pll8_pll2_map[] = {
44 [P_PXO] = 0,
45 [P_PLL8] = 2,
46 [P_PLL2] = 1,
47};
48
49static const char *mmcc_pxo_pll8_pll2[] = {
50 "pxo",
51 "pll8_vote",
52 "pll2",
53};
54
55static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
56 [P_PXO] = 0,
57 [P_PLL8] = 2,
58 [P_PLL2] = 1,
59 [P_PLL3] = 3,
60};
61
62static const char *mmcc_pxo_pll8_pll2_pll3[] = {
63 "pxo",
Stephen Boyd6d00b562014-01-15 10:47:29 -080064 "pll8_vote",
Stephen Boydff207832014-07-08 18:36:06 -070065 "pll2",
Stephen Boyd6d00b562014-01-15 10:47:29 -080066 "pll3",
67};
68
69static struct clk_pll pll2 = {
70 .l_reg = 0x320,
71 .m_reg = 0x324,
72 .n_reg = 0x328,
73 .config_reg = 0x32c,
74 .mode_reg = 0x31c,
75 .status_reg = 0x334,
76 .status_bit = 16,
77 .clkr.hw.init = &(struct clk_init_data){
78 .name = "pll2",
79 .parent_names = (const char *[]){ "pxo" },
80 .num_parents = 1,
81 .ops = &clk_pll_ops,
82 },
83};
84
85static struct freq_tbl clk_tbl_cam[] = {
86 { 6000000, P_PLL8, 4, 1, 16 },
87 { 8000000, P_PLL8, 4, 1, 12 },
88 { 12000000, P_PLL8, 4, 1, 8 },
89 { 16000000, P_PLL8, 4, 1, 6 },
90 { 19200000, P_PLL8, 4, 1, 5 },
91 { 24000000, P_PLL8, 4, 1, 4 },
92 { 32000000, P_PLL8, 4, 1, 3 },
93 { 48000000, P_PLL8, 4, 1, 2 },
94 { 64000000, P_PLL8, 3, 1, 2 },
95 { 96000000, P_PLL8, 4, 0, 0 },
96 { 128000000, P_PLL8, 3, 0, 0 },
97 { }
98};
99
100static struct clk_rcg camclk0_src = {
101 .ns_reg = 0x0148,
102 .md_reg = 0x0144,
103 .mn = {
104 .mnctr_en_bit = 5,
105 .mnctr_reset_bit = 8,
106 .reset_in_cc = true,
107 .mnctr_mode_shift = 6,
108 .n_val_shift = 24,
109 .m_val_shift = 8,
110 .width = 8,
111 },
112 .p = {
113 .pre_div_shift = 14,
114 .pre_div_width = 2,
115 },
116 .s = {
117 .src_sel_shift = 0,
118 .parent_map = mmcc_pxo_pll8_pll2_map,
119 },
120 .freq_tbl = clk_tbl_cam,
121 .clkr = {
122 .enable_reg = 0x0140,
123 .enable_mask = BIT(2),
124 .hw.init = &(struct clk_init_data){
125 .name = "camclk0_src",
126 .parent_names = mmcc_pxo_pll8_pll2,
127 .num_parents = 3,
128 .ops = &clk_rcg_ops,
129 },
130 },
131};
132
133static struct clk_branch camclk0_clk = {
134 .halt_reg = 0x01e8,
135 .halt_bit = 15,
136 .clkr = {
137 .enable_reg = 0x0140,
138 .enable_mask = BIT(0),
139 .hw.init = &(struct clk_init_data){
140 .name = "camclk0_clk",
141 .parent_names = (const char *[]){ "camclk0_src" },
142 .num_parents = 1,
143 .ops = &clk_branch_ops,
144 },
145 },
146
147};
148
149static struct clk_rcg camclk1_src = {
150 .ns_reg = 0x015c,
151 .md_reg = 0x0158,
152 .mn = {
153 .mnctr_en_bit = 5,
154 .mnctr_reset_bit = 8,
155 .reset_in_cc = true,
156 .mnctr_mode_shift = 6,
157 .n_val_shift = 24,
158 .m_val_shift = 8,
159 .width = 8,
160 },
161 .p = {
162 .pre_div_shift = 14,
163 .pre_div_width = 2,
164 },
165 .s = {
166 .src_sel_shift = 0,
167 .parent_map = mmcc_pxo_pll8_pll2_map,
168 },
169 .freq_tbl = clk_tbl_cam,
170 .clkr = {
171 .enable_reg = 0x0154,
172 .enable_mask = BIT(2),
173 .hw.init = &(struct clk_init_data){
174 .name = "camclk1_src",
175 .parent_names = mmcc_pxo_pll8_pll2,
176 .num_parents = 3,
177 .ops = &clk_rcg_ops,
178 },
179 },
180};
181
182static struct clk_branch camclk1_clk = {
183 .halt_reg = 0x01e8,
184 .halt_bit = 16,
185 .clkr = {
186 .enable_reg = 0x0154,
187 .enable_mask = BIT(0),
188 .hw.init = &(struct clk_init_data){
189 .name = "camclk1_clk",
190 .parent_names = (const char *[]){ "camclk1_src" },
191 .num_parents = 1,
192 .ops = &clk_branch_ops,
193 },
194 },
195
196};
197
198static struct clk_rcg camclk2_src = {
199 .ns_reg = 0x0228,
200 .md_reg = 0x0224,
201 .mn = {
202 .mnctr_en_bit = 5,
203 .mnctr_reset_bit = 8,
204 .reset_in_cc = true,
205 .mnctr_mode_shift = 6,
206 .n_val_shift = 24,
207 .m_val_shift = 8,
208 .width = 8,
209 },
210 .p = {
211 .pre_div_shift = 14,
212 .pre_div_width = 2,
213 },
214 .s = {
215 .src_sel_shift = 0,
216 .parent_map = mmcc_pxo_pll8_pll2_map,
217 },
218 .freq_tbl = clk_tbl_cam,
219 .clkr = {
220 .enable_reg = 0x0220,
221 .enable_mask = BIT(2),
222 .hw.init = &(struct clk_init_data){
223 .name = "camclk2_src",
224 .parent_names = mmcc_pxo_pll8_pll2,
225 .num_parents = 3,
226 .ops = &clk_rcg_ops,
227 },
228 },
229};
230
231static struct clk_branch camclk2_clk = {
232 .halt_reg = 0x01e8,
233 .halt_bit = 16,
234 .clkr = {
235 .enable_reg = 0x0220,
236 .enable_mask = BIT(0),
237 .hw.init = &(struct clk_init_data){
238 .name = "camclk2_clk",
239 .parent_names = (const char *[]){ "camclk2_src" },
240 .num_parents = 1,
241 .ops = &clk_branch_ops,
242 },
243 },
244
245};
246
247static struct freq_tbl clk_tbl_csi[] = {
248 { 27000000, P_PXO, 1, 0, 0 },
249 { 85330000, P_PLL8, 1, 2, 9 },
250 { 177780000, P_PLL2, 1, 2, 9 },
251 { }
252};
253
254static struct clk_rcg csi0_src = {
255 .ns_reg = 0x0048,
256 .md_reg = 0x0044,
257 .mn = {
258 .mnctr_en_bit = 5,
259 .mnctr_reset_bit = 7,
260 .mnctr_mode_shift = 6,
261 .n_val_shift = 24,
262 .m_val_shift = 8,
263 .width = 8,
264 },
265 .p = {
266 .pre_div_shift = 14,
267 .pre_div_width = 2,
268 },
269 .s = {
270 .src_sel_shift = 0,
271 .parent_map = mmcc_pxo_pll8_pll2_map,
272 },
273 .freq_tbl = clk_tbl_csi,
274 .clkr = {
275 .enable_reg = 0x0040,
276 .enable_mask = BIT(2),
277 .hw.init = &(struct clk_init_data){
278 .name = "csi0_src",
279 .parent_names = mmcc_pxo_pll8_pll2,
280 .num_parents = 3,
281 .ops = &clk_rcg_ops,
282 },
283 },
284};
285
286static struct clk_branch csi0_clk = {
287 .halt_reg = 0x01cc,
288 .halt_bit = 13,
289 .clkr = {
290 .enable_reg = 0x0040,
291 .enable_mask = BIT(0),
292 .hw.init = &(struct clk_init_data){
293 .parent_names = (const char *[]){ "csi0_src" },
294 .num_parents = 1,
295 .name = "csi0_clk",
296 .ops = &clk_branch_ops,
297 .flags = CLK_SET_RATE_PARENT,
298 },
299 },
300};
301
302static struct clk_branch csi0_phy_clk = {
303 .halt_reg = 0x01e8,
304 .halt_bit = 9,
305 .clkr = {
306 .enable_reg = 0x0040,
307 .enable_mask = BIT(8),
308 .hw.init = &(struct clk_init_data){
309 .parent_names = (const char *[]){ "csi0_src" },
310 .num_parents = 1,
311 .name = "csi0_phy_clk",
312 .ops = &clk_branch_ops,
313 .flags = CLK_SET_RATE_PARENT,
314 },
315 },
316};
317
318static struct clk_rcg csi1_src = {
319 .ns_reg = 0x0010,
320 .md_reg = 0x0028,
321 .mn = {
322 .mnctr_en_bit = 5,
323 .mnctr_reset_bit = 7,
324 .mnctr_mode_shift = 6,
325 .n_val_shift = 24,
326 .m_val_shift = 8,
327 .width = 8,
328 },
329 .p = {
330 .pre_div_shift = 14,
331 .pre_div_width = 2,
332 },
333 .s = {
334 .src_sel_shift = 0,
335 .parent_map = mmcc_pxo_pll8_pll2_map,
336 },
337 .freq_tbl = clk_tbl_csi,
338 .clkr = {
339 .enable_reg = 0x0024,
340 .enable_mask = BIT(2),
341 .hw.init = &(struct clk_init_data){
342 .name = "csi1_src",
343 .parent_names = mmcc_pxo_pll8_pll2,
344 .num_parents = 3,
345 .ops = &clk_rcg_ops,
346 },
347 },
348};
349
350static struct clk_branch csi1_clk = {
351 .halt_reg = 0x01cc,
352 .halt_bit = 14,
353 .clkr = {
354 .enable_reg = 0x0024,
355 .enable_mask = BIT(0),
356 .hw.init = &(struct clk_init_data){
357 .parent_names = (const char *[]){ "csi1_src" },
358 .num_parents = 1,
359 .name = "csi1_clk",
360 .ops = &clk_branch_ops,
361 .flags = CLK_SET_RATE_PARENT,
362 },
363 },
364};
365
366static struct clk_branch csi1_phy_clk = {
367 .halt_reg = 0x01e8,
368 .halt_bit = 10,
369 .clkr = {
370 .enable_reg = 0x0024,
371 .enable_mask = BIT(8),
372 .hw.init = &(struct clk_init_data){
373 .parent_names = (const char *[]){ "csi1_src" },
374 .num_parents = 1,
375 .name = "csi1_phy_clk",
376 .ops = &clk_branch_ops,
377 .flags = CLK_SET_RATE_PARENT,
378 },
379 },
380};
381
382static struct clk_rcg csi2_src = {
383 .ns_reg = 0x0234,
384 .md_reg = 0x022c,
385 .mn = {
386 .mnctr_en_bit = 5,
387 .mnctr_reset_bit = 7,
388 .mnctr_mode_shift = 6,
389 .n_val_shift = 24,
390 .m_val_shift = 8,
391 .width = 8,
392 },
393 .p = {
394 .pre_div_shift = 14,
395 .pre_div_width = 2,
396 },
397 .s = {
398 .src_sel_shift = 0,
399 .parent_map = mmcc_pxo_pll8_pll2_map,
400 },
401 .freq_tbl = clk_tbl_csi,
402 .clkr = {
403 .enable_reg = 0x022c,
404 .enable_mask = BIT(2),
405 .hw.init = &(struct clk_init_data){
406 .name = "csi2_src",
407 .parent_names = mmcc_pxo_pll8_pll2,
408 .num_parents = 3,
409 .ops = &clk_rcg_ops,
410 },
411 },
412};
413
414static struct clk_branch csi2_clk = {
415 .halt_reg = 0x01cc,
416 .halt_bit = 29,
417 .clkr = {
418 .enable_reg = 0x022c,
419 .enable_mask = BIT(0),
420 .hw.init = &(struct clk_init_data){
421 .parent_names = (const char *[]){ "csi2_src" },
422 .num_parents = 1,
423 .name = "csi2_clk",
424 .ops = &clk_branch_ops,
425 .flags = CLK_SET_RATE_PARENT,
426 },
427 },
428};
429
430static struct clk_branch csi2_phy_clk = {
431 .halt_reg = 0x01e8,
432 .halt_bit = 29,
433 .clkr = {
434 .enable_reg = 0x022c,
435 .enable_mask = BIT(8),
436 .hw.init = &(struct clk_init_data){
437 .parent_names = (const char *[]){ "csi2_src" },
438 .num_parents = 1,
439 .name = "csi2_phy_clk",
440 .ops = &clk_branch_ops,
441 .flags = CLK_SET_RATE_PARENT,
442 },
443 },
444};
445
446struct clk_pix_rdi {
447 u32 s_reg;
448 u32 s_mask;
449 u32 s2_reg;
450 u32 s2_mask;
451 struct clk_regmap clkr;
452};
453
454#define to_clk_pix_rdi(_hw) \
455 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
456
457static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
458{
459 int i;
460 int ret = 0;
461 u32 val;
462 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
463 struct clk *clk = hw->clk;
464 int num_parents = __clk_get_num_parents(hw->clk);
465
466 /*
467 * These clocks select three inputs via two muxes. One mux selects
468 * between csi0 and csi1 and the second mux selects between that mux's
469 * output and csi2. The source and destination selections for each
470 * mux must be clocking for the switch to succeed so just turn on
471 * all three sources because it's easier than figuring out what source
472 * needs to be on at what time.
473 */
474 for (i = 0; i < num_parents; i++) {
475 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
476 if (ret)
477 goto err;
478 }
479
480 if (index == 2)
481 val = rdi->s2_mask;
482 else
483 val = 0;
484 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
485 /*
486 * Wait at least 6 cycles of slowest clock
487 * for the glitch-free MUX to fully switch sources.
488 */
489 udelay(1);
490
491 if (index == 1)
492 val = rdi->s_mask;
493 else
494 val = 0;
495 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
496 /*
497 * Wait at least 6 cycles of slowest clock
498 * for the glitch-free MUX to fully switch sources.
499 */
500 udelay(1);
501
502err:
503 for (i--; i >= 0; i--)
504 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
505
506 return ret;
507}
508
509static u8 pix_rdi_get_parent(struct clk_hw *hw)
510{
511 u32 val;
512 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
513
514
515 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
516 if (val & rdi->s2_mask)
517 return 2;
518
519 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
520 if (val & rdi->s_mask)
521 return 1;
522
523 return 0;
524}
525
526static const struct clk_ops clk_ops_pix_rdi = {
527 .enable = clk_enable_regmap,
528 .disable = clk_disable_regmap,
529 .set_parent = pix_rdi_set_parent,
530 .get_parent = pix_rdi_get_parent,
531 .determine_rate = __clk_mux_determine_rate,
532};
533
534static const char *pix_rdi_parents[] = {
535 "csi0_clk",
536 "csi1_clk",
537 "csi2_clk",
538};
539
540static struct clk_pix_rdi csi_pix_clk = {
541 .s_reg = 0x0058,
542 .s_mask = BIT(25),
543 .s2_reg = 0x0238,
544 .s2_mask = BIT(13),
545 .clkr = {
546 .enable_reg = 0x0058,
547 .enable_mask = BIT(26),
548 .hw.init = &(struct clk_init_data){
549 .name = "csi_pix_clk",
550 .parent_names = pix_rdi_parents,
551 .num_parents = 3,
552 .ops = &clk_ops_pix_rdi,
553 },
554 },
555};
556
557static struct clk_pix_rdi csi_pix1_clk = {
558 .s_reg = 0x0238,
559 .s_mask = BIT(8),
560 .s2_reg = 0x0238,
561 .s2_mask = BIT(9),
562 .clkr = {
563 .enable_reg = 0x0238,
564 .enable_mask = BIT(10),
565 .hw.init = &(struct clk_init_data){
566 .name = "csi_pix1_clk",
567 .parent_names = pix_rdi_parents,
568 .num_parents = 3,
569 .ops = &clk_ops_pix_rdi,
570 },
571 },
572};
573
574static struct clk_pix_rdi csi_rdi_clk = {
575 .s_reg = 0x0058,
576 .s_mask = BIT(12),
577 .s2_reg = 0x0238,
578 .s2_mask = BIT(12),
579 .clkr = {
580 .enable_reg = 0x0058,
581 .enable_mask = BIT(13),
582 .hw.init = &(struct clk_init_data){
583 .name = "csi_rdi_clk",
584 .parent_names = pix_rdi_parents,
585 .num_parents = 3,
586 .ops = &clk_ops_pix_rdi,
587 },
588 },
589};
590
591static struct clk_pix_rdi csi_rdi1_clk = {
592 .s_reg = 0x0238,
593 .s_mask = BIT(0),
594 .s2_reg = 0x0238,
595 .s2_mask = BIT(1),
596 .clkr = {
597 .enable_reg = 0x0238,
598 .enable_mask = BIT(2),
599 .hw.init = &(struct clk_init_data){
600 .name = "csi_rdi1_clk",
601 .parent_names = pix_rdi_parents,
602 .num_parents = 3,
603 .ops = &clk_ops_pix_rdi,
604 },
605 },
606};
607
608static struct clk_pix_rdi csi_rdi2_clk = {
609 .s_reg = 0x0238,
610 .s_mask = BIT(4),
611 .s2_reg = 0x0238,
612 .s2_mask = BIT(5),
613 .clkr = {
614 .enable_reg = 0x0238,
615 .enable_mask = BIT(6),
616 .hw.init = &(struct clk_init_data){
617 .name = "csi_rdi2_clk",
618 .parent_names = pix_rdi_parents,
619 .num_parents = 3,
620 .ops = &clk_ops_pix_rdi,
621 },
622 },
623};
624
625static struct freq_tbl clk_tbl_csiphytimer[] = {
626 { 85330000, P_PLL8, 1, 2, 9 },
627 { 177780000, P_PLL2, 1, 2, 9 },
628 { }
629};
630
631static struct clk_rcg csiphytimer_src = {
632 .ns_reg = 0x0168,
633 .md_reg = 0x0164,
634 .mn = {
635 .mnctr_en_bit = 5,
636 .mnctr_reset_bit = 8,
637 .reset_in_cc = true,
638 .mnctr_mode_shift = 6,
639 .n_val_shift = 24,
640 .m_val_shift = 8,
641 .width = 8,
642 },
643 .p = {
644 .pre_div_shift = 14,
645 .pre_div_width = 2,
646 },
647 .s = {
648 .src_sel_shift = 0,
649 .parent_map = mmcc_pxo_pll8_pll2_map,
650 },
651 .freq_tbl = clk_tbl_csiphytimer,
652 .clkr = {
653 .enable_reg = 0x0160,
654 .enable_mask = BIT(2),
655 .hw.init = &(struct clk_init_data){
656 .name = "csiphytimer_src",
657 .parent_names = mmcc_pxo_pll8_pll2,
658 .num_parents = 3,
659 .ops = &clk_rcg_ops,
660 },
661 },
662};
663
664static const char *csixphy_timer_src[] = { "csiphytimer_src" };
665
666static struct clk_branch csiphy0_timer_clk = {
667 .halt_reg = 0x01e8,
668 .halt_bit = 17,
669 .clkr = {
670 .enable_reg = 0x0160,
671 .enable_mask = BIT(0),
672 .hw.init = &(struct clk_init_data){
673 .parent_names = csixphy_timer_src,
674 .num_parents = 1,
675 .name = "csiphy0_timer_clk",
676 .ops = &clk_branch_ops,
677 .flags = CLK_SET_RATE_PARENT,
678 },
679 },
680};
681
682static struct clk_branch csiphy1_timer_clk = {
683 .halt_reg = 0x01e8,
684 .halt_bit = 18,
685 .clkr = {
686 .enable_reg = 0x0160,
687 .enable_mask = BIT(9),
688 .hw.init = &(struct clk_init_data){
689 .parent_names = csixphy_timer_src,
690 .num_parents = 1,
691 .name = "csiphy1_timer_clk",
692 .ops = &clk_branch_ops,
693 .flags = CLK_SET_RATE_PARENT,
694 },
695 },
696};
697
698static struct clk_branch csiphy2_timer_clk = {
699 .halt_reg = 0x01e8,
700 .halt_bit = 30,
701 .clkr = {
702 .enable_reg = 0x0160,
703 .enable_mask = BIT(11),
704 .hw.init = &(struct clk_init_data){
705 .parent_names = csixphy_timer_src,
706 .num_parents = 1,
707 .name = "csiphy2_timer_clk",
708 .ops = &clk_branch_ops,
709 .flags = CLK_SET_RATE_PARENT,
710 },
711 },
712};
713
714static struct freq_tbl clk_tbl_gfx2d[] = {
Stephen Boydff207832014-07-08 18:36:06 -0700715 F_MN( 27000000, P_PXO, 1, 0),
716 F_MN( 48000000, P_PLL8, 1, 8),
717 F_MN( 54857000, P_PLL8, 1, 7),
718 F_MN( 64000000, P_PLL8, 1, 6),
719 F_MN( 76800000, P_PLL8, 1, 5),
720 F_MN( 96000000, P_PLL8, 1, 4),
721 F_MN(128000000, P_PLL8, 1, 3),
722 F_MN(145455000, P_PLL2, 2, 11),
723 F_MN(160000000, P_PLL2, 1, 5),
724 F_MN(177778000, P_PLL2, 2, 9),
725 F_MN(200000000, P_PLL2, 1, 4),
726 F_MN(228571000, P_PLL2, 2, 7),
Stephen Boyd6d00b562014-01-15 10:47:29 -0800727 { }
728};
729
730static struct clk_dyn_rcg gfx2d0_src = {
731 .ns_reg = 0x0070,
732 .md_reg[0] = 0x0064,
733 .md_reg[1] = 0x0068,
734 .mn[0] = {
735 .mnctr_en_bit = 8,
736 .mnctr_reset_bit = 25,
737 .mnctr_mode_shift = 9,
738 .n_val_shift = 20,
739 .m_val_shift = 4,
740 .width = 4,
741 },
742 .mn[1] = {
743 .mnctr_en_bit = 5,
744 .mnctr_reset_bit = 24,
745 .mnctr_mode_shift = 6,
746 .n_val_shift = 16,
747 .m_val_shift = 4,
748 .width = 4,
749 },
750 .s[0] = {
751 .src_sel_shift = 3,
752 .parent_map = mmcc_pxo_pll8_pll2_map,
753 },
754 .s[1] = {
755 .src_sel_shift = 0,
756 .parent_map = mmcc_pxo_pll8_pll2_map,
757 },
758 .mux_sel_bit = 11,
759 .freq_tbl = clk_tbl_gfx2d,
760 .clkr = {
761 .enable_reg = 0x0060,
762 .enable_mask = BIT(2),
763 .hw.init = &(struct clk_init_data){
764 .name = "gfx2d0_src",
765 .parent_names = mmcc_pxo_pll8_pll2,
766 .num_parents = 3,
767 .ops = &clk_dyn_rcg_ops,
768 },
769 },
770};
771
772static struct clk_branch gfx2d0_clk = {
773 .halt_reg = 0x01c8,
774 .halt_bit = 9,
775 .clkr = {
776 .enable_reg = 0x0060,
777 .enable_mask = BIT(0),
778 .hw.init = &(struct clk_init_data){
779 .name = "gfx2d0_clk",
780 .parent_names = (const char *[]){ "gfx2d0_src" },
781 .num_parents = 1,
782 .ops = &clk_branch_ops,
783 .flags = CLK_SET_RATE_PARENT,
784 },
785 },
786};
787
788static struct clk_dyn_rcg gfx2d1_src = {
789 .ns_reg = 0x007c,
790 .md_reg[0] = 0x0078,
791 .md_reg[1] = 0x006c,
792 .mn[0] = {
793 .mnctr_en_bit = 8,
794 .mnctr_reset_bit = 25,
795 .mnctr_mode_shift = 9,
796 .n_val_shift = 20,
797 .m_val_shift = 4,
798 .width = 4,
799 },
800 .mn[1] = {
801 .mnctr_en_bit = 5,
802 .mnctr_reset_bit = 24,
803 .mnctr_mode_shift = 6,
804 .n_val_shift = 16,
805 .m_val_shift = 4,
806 .width = 4,
807 },
808 .s[0] = {
809 .src_sel_shift = 3,
810 .parent_map = mmcc_pxo_pll8_pll2_map,
811 },
812 .s[1] = {
813 .src_sel_shift = 0,
814 .parent_map = mmcc_pxo_pll8_pll2_map,
815 },
816 .mux_sel_bit = 11,
817 .freq_tbl = clk_tbl_gfx2d,
818 .clkr = {
819 .enable_reg = 0x0074,
820 .enable_mask = BIT(2),
821 .hw.init = &(struct clk_init_data){
822 .name = "gfx2d1_src",
823 .parent_names = mmcc_pxo_pll8_pll2,
824 .num_parents = 3,
825 .ops = &clk_dyn_rcg_ops,
826 },
827 },
828};
829
830static struct clk_branch gfx2d1_clk = {
831 .halt_reg = 0x01c8,
832 .halt_bit = 14,
833 .clkr = {
834 .enable_reg = 0x0074,
835 .enable_mask = BIT(0),
836 .hw.init = &(struct clk_init_data){
837 .name = "gfx2d1_clk",
838 .parent_names = (const char *[]){ "gfx2d1_src" },
839 .num_parents = 1,
840 .ops = &clk_branch_ops,
841 .flags = CLK_SET_RATE_PARENT,
842 },
843 },
844};
845
846static struct freq_tbl clk_tbl_gfx3d[] = {
Stephen Boydff207832014-07-08 18:36:06 -0700847 F_MN( 27000000, P_PXO, 1, 0),
848 F_MN( 48000000, P_PLL8, 1, 8),
849 F_MN( 54857000, P_PLL8, 1, 7),
850 F_MN( 64000000, P_PLL8, 1, 6),
851 F_MN( 76800000, P_PLL8, 1, 5),
852 F_MN( 96000000, P_PLL8, 1, 4),
853 F_MN(128000000, P_PLL8, 1, 3),
854 F_MN(145455000, P_PLL2, 2, 11),
855 F_MN(160000000, P_PLL2, 1, 5),
856 F_MN(177778000, P_PLL2, 2, 9),
857 F_MN(200000000, P_PLL2, 1, 4),
858 F_MN(228571000, P_PLL2, 2, 7),
859 F_MN(266667000, P_PLL2, 1, 3),
860 F_MN(300000000, P_PLL3, 1, 4),
861 F_MN(320000000, P_PLL2, 2, 5),
862 F_MN(400000000, P_PLL2, 1, 2),
Stephen Boyd6d00b562014-01-15 10:47:29 -0800863 { }
864};
865
866static struct clk_dyn_rcg gfx3d_src = {
867 .ns_reg = 0x008c,
868 .md_reg[0] = 0x0084,
869 .md_reg[1] = 0x0088,
870 .mn[0] = {
871 .mnctr_en_bit = 8,
872 .mnctr_reset_bit = 25,
873 .mnctr_mode_shift = 9,
874 .n_val_shift = 18,
875 .m_val_shift = 4,
876 .width = 4,
877 },
878 .mn[1] = {
879 .mnctr_en_bit = 5,
880 .mnctr_reset_bit = 24,
881 .mnctr_mode_shift = 6,
882 .n_val_shift = 14,
883 .m_val_shift = 4,
884 .width = 4,
885 },
886 .s[0] = {
887 .src_sel_shift = 3,
888 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
889 },
890 .s[1] = {
891 .src_sel_shift = 0,
892 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
893 },
894 .mux_sel_bit = 11,
895 .freq_tbl = clk_tbl_gfx3d,
896 .clkr = {
897 .enable_reg = 0x0080,
898 .enable_mask = BIT(2),
899 .hw.init = &(struct clk_init_data){
900 .name = "gfx3d_src",
901 .parent_names = mmcc_pxo_pll8_pll2_pll3,
Stephen Boydff207832014-07-08 18:36:06 -0700902 .num_parents = 4,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800903 .ops = &clk_dyn_rcg_ops,
904 },
905 },
906};
907
908static struct clk_branch gfx3d_clk = {
909 .halt_reg = 0x01c8,
910 .halt_bit = 4,
911 .clkr = {
912 .enable_reg = 0x0080,
913 .enable_mask = BIT(0),
914 .hw.init = &(struct clk_init_data){
915 .name = "gfx3d_clk",
916 .parent_names = (const char *[]){ "gfx3d_src" },
917 .num_parents = 1,
918 .ops = &clk_branch_ops,
919 .flags = CLK_SET_RATE_PARENT,
920 },
921 },
922};
923
924static struct freq_tbl clk_tbl_ijpeg[] = {
925 { 27000000, P_PXO, 1, 0, 0 },
926 { 36570000, P_PLL8, 1, 2, 21 },
927 { 54860000, P_PLL8, 7, 0, 0 },
928 { 96000000, P_PLL8, 4, 0, 0 },
929 { 109710000, P_PLL8, 1, 2, 7 },
930 { 128000000, P_PLL8, 3, 0, 0 },
931 { 153600000, P_PLL8, 1, 2, 5 },
932 { 200000000, P_PLL2, 4, 0, 0 },
933 { 228571000, P_PLL2, 1, 2, 7 },
934 { 266667000, P_PLL2, 1, 1, 3 },
935 { 320000000, P_PLL2, 1, 2, 5 },
936 { }
937};
938
939static struct clk_rcg ijpeg_src = {
940 .ns_reg = 0x00a0,
941 .md_reg = 0x009c,
942 .mn = {
943 .mnctr_en_bit = 5,
944 .mnctr_reset_bit = 7,
945 .mnctr_mode_shift = 6,
946 .n_val_shift = 16,
947 .m_val_shift = 8,
948 .width = 8,
949 },
950 .p = {
951 .pre_div_shift = 12,
952 .pre_div_width = 2,
953 },
954 .s = {
955 .src_sel_shift = 0,
956 .parent_map = mmcc_pxo_pll8_pll2_map,
957 },
958 .freq_tbl = clk_tbl_ijpeg,
959 .clkr = {
960 .enable_reg = 0x0098,
961 .enable_mask = BIT(2),
962 .hw.init = &(struct clk_init_data){
963 .name = "ijpeg_src",
964 .parent_names = mmcc_pxo_pll8_pll2,
965 .num_parents = 3,
966 .ops = &clk_rcg_ops,
967 },
968 },
969};
970
971static struct clk_branch ijpeg_clk = {
972 .halt_reg = 0x01c8,
973 .halt_bit = 24,
974 .clkr = {
975 .enable_reg = 0x0098,
976 .enable_mask = BIT(0),
977 .hw.init = &(struct clk_init_data){
978 .name = "ijpeg_clk",
979 .parent_names = (const char *[]){ "ijpeg_src" },
980 .num_parents = 1,
981 .ops = &clk_branch_ops,
982 .flags = CLK_SET_RATE_PARENT,
983 },
984 },
985};
986
987static struct freq_tbl clk_tbl_jpegd[] = {
988 { 64000000, P_PLL8, 6 },
989 { 76800000, P_PLL8, 5 },
990 { 96000000, P_PLL8, 4 },
991 { 160000000, P_PLL2, 5 },
992 { 200000000, P_PLL2, 4 },
993 { }
994};
995
996static struct clk_rcg jpegd_src = {
997 .ns_reg = 0x00ac,
998 .p = {
999 .pre_div_shift = 12,
Stephen Boydff207832014-07-08 18:36:06 -07001000 .pre_div_width = 4,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001001 },
1002 .s = {
1003 .src_sel_shift = 0,
1004 .parent_map = mmcc_pxo_pll8_pll2_map,
1005 },
1006 .freq_tbl = clk_tbl_jpegd,
1007 .clkr = {
1008 .enable_reg = 0x00a4,
1009 .enable_mask = BIT(2),
1010 .hw.init = &(struct clk_init_data){
1011 .name = "jpegd_src",
1012 .parent_names = mmcc_pxo_pll8_pll2,
1013 .num_parents = 3,
1014 .ops = &clk_rcg_ops,
1015 },
1016 },
1017};
1018
1019static struct clk_branch jpegd_clk = {
1020 .halt_reg = 0x01c8,
1021 .halt_bit = 19,
1022 .clkr = {
1023 .enable_reg = 0x00a4,
1024 .enable_mask = BIT(0),
1025 .hw.init = &(struct clk_init_data){
1026 .name = "jpegd_clk",
1027 .parent_names = (const char *[]){ "jpegd_src" },
1028 .num_parents = 1,
1029 .ops = &clk_branch_ops,
1030 .flags = CLK_SET_RATE_PARENT,
1031 },
1032 },
1033};
1034
1035static struct freq_tbl clk_tbl_mdp[] = {
1036 { 9600000, P_PLL8, 1, 1, 40 },
1037 { 13710000, P_PLL8, 1, 1, 28 },
1038 { 27000000, P_PXO, 1, 0, 0 },
1039 { 29540000, P_PLL8, 1, 1, 13 },
1040 { 34910000, P_PLL8, 1, 1, 11 },
1041 { 38400000, P_PLL8, 1, 1, 10 },
1042 { 59080000, P_PLL8, 1, 2, 13 },
1043 { 76800000, P_PLL8, 1, 1, 5 },
1044 { 85330000, P_PLL8, 1, 2, 9 },
1045 { 96000000, P_PLL8, 1, 1, 4 },
1046 { 128000000, P_PLL8, 1, 1, 3 },
1047 { 160000000, P_PLL2, 1, 1, 5 },
1048 { 177780000, P_PLL2, 1, 2, 9 },
1049 { 200000000, P_PLL2, 1, 1, 4 },
1050 { 228571000, P_PLL2, 1, 2, 7 },
1051 { 266667000, P_PLL2, 1, 1, 3 },
1052 { }
1053};
1054
1055static struct clk_dyn_rcg mdp_src = {
1056 .ns_reg = 0x00d0,
1057 .md_reg[0] = 0x00c4,
1058 .md_reg[1] = 0x00c8,
1059 .mn[0] = {
1060 .mnctr_en_bit = 8,
1061 .mnctr_reset_bit = 31,
1062 .mnctr_mode_shift = 9,
1063 .n_val_shift = 22,
1064 .m_val_shift = 8,
1065 .width = 8,
1066 },
1067 .mn[1] = {
1068 .mnctr_en_bit = 5,
1069 .mnctr_reset_bit = 30,
1070 .mnctr_mode_shift = 6,
1071 .n_val_shift = 14,
1072 .m_val_shift = 8,
1073 .width = 8,
1074 },
1075 .s[0] = {
1076 .src_sel_shift = 3,
1077 .parent_map = mmcc_pxo_pll8_pll2_map,
1078 },
1079 .s[1] = {
1080 .src_sel_shift = 0,
1081 .parent_map = mmcc_pxo_pll8_pll2_map,
1082 },
1083 .mux_sel_bit = 11,
1084 .freq_tbl = clk_tbl_mdp,
1085 .clkr = {
1086 .enable_reg = 0x00c0,
1087 .enable_mask = BIT(2),
1088 .hw.init = &(struct clk_init_data){
1089 .name = "mdp_src",
1090 .parent_names = mmcc_pxo_pll8_pll2,
1091 .num_parents = 3,
1092 .ops = &clk_dyn_rcg_ops,
1093 },
1094 },
1095};
1096
1097static struct clk_branch mdp_clk = {
1098 .halt_reg = 0x01d0,
1099 .halt_bit = 10,
1100 .clkr = {
1101 .enable_reg = 0x00c0,
1102 .enable_mask = BIT(0),
1103 .hw.init = &(struct clk_init_data){
1104 .name = "mdp_clk",
1105 .parent_names = (const char *[]){ "mdp_src" },
1106 .num_parents = 1,
1107 .ops = &clk_branch_ops,
1108 .flags = CLK_SET_RATE_PARENT,
1109 },
1110 },
1111};
1112
1113static struct clk_branch mdp_lut_clk = {
1114 .halt_reg = 0x01e8,
1115 .halt_bit = 13,
1116 .clkr = {
1117 .enable_reg = 0x016c,
1118 .enable_mask = BIT(0),
1119 .hw.init = &(struct clk_init_data){
Stephen Boydf87dfca2014-07-08 18:36:06 -07001120 .parent_names = (const char *[]){ "mdp_src" },
Stephen Boyd6d00b562014-01-15 10:47:29 -08001121 .num_parents = 1,
1122 .name = "mdp_lut_clk",
1123 .ops = &clk_branch_ops,
1124 .flags = CLK_SET_RATE_PARENT,
1125 },
1126 },
1127};
1128
1129static struct clk_branch mdp_vsync_clk = {
1130 .halt_reg = 0x01cc,
1131 .halt_bit = 22,
1132 .clkr = {
1133 .enable_reg = 0x0058,
1134 .enable_mask = BIT(6),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "mdp_vsync_clk",
1137 .parent_names = (const char *[]){ "pxo" },
1138 .num_parents = 1,
1139 .ops = &clk_branch_ops
1140 },
1141 },
1142};
1143
1144static struct freq_tbl clk_tbl_rot[] = {
1145 { 27000000, P_PXO, 1 },
1146 { 29540000, P_PLL8, 13 },
1147 { 32000000, P_PLL8, 12 },
1148 { 38400000, P_PLL8, 10 },
1149 { 48000000, P_PLL8, 8 },
1150 { 54860000, P_PLL8, 7 },
1151 { 64000000, P_PLL8, 6 },
1152 { 76800000, P_PLL8, 5 },
1153 { 96000000, P_PLL8, 4 },
1154 { 100000000, P_PLL2, 8 },
1155 { 114290000, P_PLL2, 7 },
1156 { 133330000, P_PLL2, 6 },
1157 { 160000000, P_PLL2, 5 },
1158 { 200000000, P_PLL2, 4 },
1159 { }
1160};
1161
1162static struct clk_dyn_rcg rot_src = {
1163 .ns_reg = 0x00e8,
1164 .p[0] = {
1165 .pre_div_shift = 22,
1166 .pre_div_width = 4,
1167 },
1168 .p[1] = {
1169 .pre_div_shift = 26,
1170 .pre_div_width = 4,
1171 },
1172 .s[0] = {
1173 .src_sel_shift = 16,
1174 .parent_map = mmcc_pxo_pll8_pll2_map,
1175 },
1176 .s[1] = {
1177 .src_sel_shift = 19,
1178 .parent_map = mmcc_pxo_pll8_pll2_map,
1179 },
1180 .mux_sel_bit = 30,
1181 .freq_tbl = clk_tbl_rot,
1182 .clkr = {
1183 .enable_reg = 0x00e0,
1184 .enable_mask = BIT(2),
1185 .hw.init = &(struct clk_init_data){
1186 .name = "rot_src",
1187 .parent_names = mmcc_pxo_pll8_pll2,
1188 .num_parents = 3,
1189 .ops = &clk_dyn_rcg_ops,
1190 },
1191 },
1192};
1193
1194static struct clk_branch rot_clk = {
1195 .halt_reg = 0x01d0,
1196 .halt_bit = 15,
1197 .clkr = {
1198 .enable_reg = 0x00e0,
1199 .enable_mask = BIT(0),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "rot_clk",
1202 .parent_names = (const char *[]){ "rot_src" },
1203 .num_parents = 1,
1204 .ops = &clk_branch_ops,
1205 .flags = CLK_SET_RATE_PARENT,
1206 },
1207 },
1208};
1209
1210#define P_HDMI_PLL 1
1211
1212static u8 mmcc_pxo_hdmi_map[] = {
1213 [P_PXO] = 0,
1214 [P_HDMI_PLL] = 2,
1215};
1216
1217static const char *mmcc_pxo_hdmi[] = {
1218 "pxo",
1219 "hdmi_pll",
1220};
1221
1222static struct freq_tbl clk_tbl_tv[] = {
Stephen Boyd404c1ff2014-07-11 12:55:27 -07001223 { .src = P_HDMI_PLL, .pre_div = 1 },
Stephen Boyd6d00b562014-01-15 10:47:29 -08001224 { }
1225};
1226
1227static struct clk_rcg tv_src = {
1228 .ns_reg = 0x00f4,
1229 .md_reg = 0x00f0,
1230 .mn = {
1231 .mnctr_en_bit = 5,
1232 .mnctr_reset_bit = 7,
1233 .mnctr_mode_shift = 6,
1234 .n_val_shift = 16,
1235 .m_val_shift = 8,
1236 .width = 8,
1237 },
1238 .p = {
1239 .pre_div_shift = 14,
1240 .pre_div_width = 2,
1241 },
1242 .s = {
1243 .src_sel_shift = 0,
1244 .parent_map = mmcc_pxo_hdmi_map,
1245 },
1246 .freq_tbl = clk_tbl_tv,
1247 .clkr = {
1248 .enable_reg = 0x00ec,
1249 .enable_mask = BIT(2),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "tv_src",
1252 .parent_names = mmcc_pxo_hdmi,
1253 .num_parents = 2,
Stephen Boyd404c1ff2014-07-11 12:55:27 -07001254 .ops = &clk_rcg_bypass_ops,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001255 .flags = CLK_SET_RATE_PARENT,
1256 },
1257 },
1258};
1259
1260static const char *tv_src_name[] = { "tv_src" };
1261
1262static struct clk_branch tv_enc_clk = {
1263 .halt_reg = 0x01d4,
1264 .halt_bit = 9,
1265 .clkr = {
1266 .enable_reg = 0x00ec,
1267 .enable_mask = BIT(8),
1268 .hw.init = &(struct clk_init_data){
1269 .parent_names = tv_src_name,
1270 .num_parents = 1,
1271 .name = "tv_enc_clk",
1272 .ops = &clk_branch_ops,
1273 .flags = CLK_SET_RATE_PARENT,
1274 },
1275 },
1276};
1277
1278static struct clk_branch tv_dac_clk = {
1279 .halt_reg = 0x01d4,
1280 .halt_bit = 10,
1281 .clkr = {
1282 .enable_reg = 0x00ec,
1283 .enable_mask = BIT(10),
1284 .hw.init = &(struct clk_init_data){
1285 .parent_names = tv_src_name,
1286 .num_parents = 1,
1287 .name = "tv_dac_clk",
1288 .ops = &clk_branch_ops,
1289 .flags = CLK_SET_RATE_PARENT,
1290 },
1291 },
1292};
1293
1294static struct clk_branch mdp_tv_clk = {
1295 .halt_reg = 0x01d4,
1296 .halt_bit = 12,
1297 .clkr = {
1298 .enable_reg = 0x00ec,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data){
1301 .parent_names = tv_src_name,
1302 .num_parents = 1,
1303 .name = "mdp_tv_clk",
1304 .ops = &clk_branch_ops,
1305 .flags = CLK_SET_RATE_PARENT,
1306 },
1307 },
1308};
1309
1310static struct clk_branch hdmi_tv_clk = {
1311 .halt_reg = 0x01d4,
1312 .halt_bit = 11,
1313 .clkr = {
1314 .enable_reg = 0x00ec,
1315 .enable_mask = BIT(12),
1316 .hw.init = &(struct clk_init_data){
1317 .parent_names = tv_src_name,
1318 .num_parents = 1,
1319 .name = "hdmi_tv_clk",
1320 .ops = &clk_branch_ops,
1321 .flags = CLK_SET_RATE_PARENT,
1322 },
1323 },
1324};
1325
1326static struct clk_branch hdmi_app_clk = {
1327 .halt_reg = 0x01cc,
1328 .halt_bit = 25,
1329 .clkr = {
1330 .enable_reg = 0x005c,
1331 .enable_mask = BIT(11),
1332 .hw.init = &(struct clk_init_data){
1333 .parent_names = (const char *[]){ "pxo" },
1334 .num_parents = 1,
1335 .name = "hdmi_app_clk",
1336 .ops = &clk_branch_ops,
1337 },
1338 },
1339};
1340
1341static struct freq_tbl clk_tbl_vcodec[] = {
Stephen Boydff207832014-07-08 18:36:06 -07001342 F_MN( 27000000, P_PXO, 1, 0),
1343 F_MN( 32000000, P_PLL8, 1, 12),
1344 F_MN( 48000000, P_PLL8, 1, 8),
1345 F_MN( 54860000, P_PLL8, 1, 7),
1346 F_MN( 96000000, P_PLL8, 1, 4),
1347 F_MN(133330000, P_PLL2, 1, 6),
1348 F_MN(200000000, P_PLL2, 1, 4),
1349 F_MN(228570000, P_PLL2, 2, 7),
1350 F_MN(266670000, P_PLL2, 1, 3),
Stephen Boyd6d00b562014-01-15 10:47:29 -08001351 { }
1352};
1353
1354static struct clk_dyn_rcg vcodec_src = {
1355 .ns_reg = 0x0100,
1356 .md_reg[0] = 0x00fc,
1357 .md_reg[1] = 0x0128,
1358 .mn[0] = {
1359 .mnctr_en_bit = 5,
1360 .mnctr_reset_bit = 31,
1361 .mnctr_mode_shift = 6,
1362 .n_val_shift = 11,
1363 .m_val_shift = 8,
1364 .width = 8,
1365 },
1366 .mn[1] = {
1367 .mnctr_en_bit = 10,
1368 .mnctr_reset_bit = 30,
1369 .mnctr_mode_shift = 11,
1370 .n_val_shift = 19,
1371 .m_val_shift = 8,
1372 .width = 8,
1373 },
1374 .s[0] = {
1375 .src_sel_shift = 27,
1376 .parent_map = mmcc_pxo_pll8_pll2_map,
1377 },
1378 .s[1] = {
1379 .src_sel_shift = 0,
1380 .parent_map = mmcc_pxo_pll8_pll2_map,
1381 },
1382 .mux_sel_bit = 13,
1383 .freq_tbl = clk_tbl_vcodec,
1384 .clkr = {
1385 .enable_reg = 0x00f8,
1386 .enable_mask = BIT(2),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "vcodec_src",
1389 .parent_names = mmcc_pxo_pll8_pll2,
1390 .num_parents = 3,
1391 .ops = &clk_dyn_rcg_ops,
1392 },
1393 },
1394};
1395
1396static struct clk_branch vcodec_clk = {
1397 .halt_reg = 0x01d0,
1398 .halt_bit = 29,
1399 .clkr = {
1400 .enable_reg = 0x00f8,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(struct clk_init_data){
1403 .name = "vcodec_clk",
1404 .parent_names = (const char *[]){ "vcodec_src" },
1405 .num_parents = 1,
1406 .ops = &clk_branch_ops,
1407 .flags = CLK_SET_RATE_PARENT,
1408 },
1409 },
1410};
1411
1412static struct freq_tbl clk_tbl_vpe[] = {
1413 { 27000000, P_PXO, 1 },
1414 { 34909000, P_PLL8, 11 },
1415 { 38400000, P_PLL8, 10 },
1416 { 64000000, P_PLL8, 6 },
1417 { 76800000, P_PLL8, 5 },
1418 { 96000000, P_PLL8, 4 },
1419 { 100000000, P_PLL2, 8 },
1420 { 160000000, P_PLL2, 5 },
1421 { }
1422};
1423
1424static struct clk_rcg vpe_src = {
1425 .ns_reg = 0x0118,
1426 .p = {
1427 .pre_div_shift = 12,
1428 .pre_div_width = 4,
1429 },
1430 .s = {
1431 .src_sel_shift = 0,
1432 .parent_map = mmcc_pxo_pll8_pll2_map,
1433 },
1434 .freq_tbl = clk_tbl_vpe,
1435 .clkr = {
1436 .enable_reg = 0x0110,
1437 .enable_mask = BIT(2),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "vpe_src",
1440 .parent_names = mmcc_pxo_pll8_pll2,
1441 .num_parents = 3,
1442 .ops = &clk_rcg_ops,
1443 },
1444 },
1445};
1446
1447static struct clk_branch vpe_clk = {
1448 .halt_reg = 0x01c8,
1449 .halt_bit = 28,
1450 .clkr = {
1451 .enable_reg = 0x0110,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "vpe_clk",
1455 .parent_names = (const char *[]){ "vpe_src" },
1456 .num_parents = 1,
1457 .ops = &clk_branch_ops,
1458 .flags = CLK_SET_RATE_PARENT,
1459 },
1460 },
1461};
1462
1463static struct freq_tbl clk_tbl_vfe[] = {
1464 { 13960000, P_PLL8, 1, 2, 55 },
1465 { 27000000, P_PXO, 1, 0, 0 },
1466 { 36570000, P_PLL8, 1, 2, 21 },
1467 { 38400000, P_PLL8, 2, 1, 5 },
1468 { 45180000, P_PLL8, 1, 2, 17 },
1469 { 48000000, P_PLL8, 2, 1, 4 },
1470 { 54860000, P_PLL8, 1, 1, 7 },
1471 { 64000000, P_PLL8, 2, 1, 3 },
1472 { 76800000, P_PLL8, 1, 1, 5 },
1473 { 96000000, P_PLL8, 2, 1, 2 },
1474 { 109710000, P_PLL8, 1, 2, 7 },
1475 { 128000000, P_PLL8, 1, 1, 3 },
1476 { 153600000, P_PLL8, 1, 2, 5 },
1477 { 200000000, P_PLL2, 2, 1, 2 },
1478 { 228570000, P_PLL2, 1, 2, 7 },
1479 { 266667000, P_PLL2, 1, 1, 3 },
1480 { 320000000, P_PLL2, 1, 2, 5 },
1481 { }
1482};
1483
1484static struct clk_rcg vfe_src = {
1485 .ns_reg = 0x0108,
1486 .mn = {
1487 .mnctr_en_bit = 5,
1488 .mnctr_reset_bit = 7,
1489 .mnctr_mode_shift = 6,
1490 .n_val_shift = 16,
1491 .m_val_shift = 8,
1492 .width = 8,
1493 },
1494 .p = {
1495 .pre_div_shift = 10,
1496 .pre_div_width = 1,
1497 },
1498 .s = {
1499 .src_sel_shift = 0,
1500 .parent_map = mmcc_pxo_pll8_pll2_map,
1501 },
1502 .freq_tbl = clk_tbl_vfe,
1503 .clkr = {
1504 .enable_reg = 0x0104,
1505 .enable_mask = BIT(2),
1506 .hw.init = &(struct clk_init_data){
1507 .name = "vfe_src",
1508 .parent_names = mmcc_pxo_pll8_pll2,
1509 .num_parents = 3,
1510 .ops = &clk_rcg_ops,
1511 },
1512 },
1513};
1514
1515static struct clk_branch vfe_clk = {
1516 .halt_reg = 0x01cc,
1517 .halt_bit = 6,
1518 .clkr = {
1519 .enable_reg = 0x0104,
1520 .enable_mask = BIT(0),
1521 .hw.init = &(struct clk_init_data){
1522 .name = "vfe_clk",
1523 .parent_names = (const char *[]){ "vfe_src" },
1524 .num_parents = 1,
1525 .ops = &clk_branch_ops,
1526 .flags = CLK_SET_RATE_PARENT,
1527 },
1528 },
1529};
1530
1531static struct clk_branch vfe_csi_clk = {
1532 .halt_reg = 0x01cc,
1533 .halt_bit = 8,
1534 .clkr = {
1535 .enable_reg = 0x0104,
1536 .enable_mask = BIT(12),
1537 .hw.init = &(struct clk_init_data){
1538 .parent_names = (const char *[]){ "vfe_src" },
1539 .num_parents = 1,
1540 .name = "vfe_csi_clk",
1541 .ops = &clk_branch_ops,
1542 .flags = CLK_SET_RATE_PARENT,
1543 },
1544 },
1545};
1546
1547static struct clk_branch gmem_axi_clk = {
1548 .halt_reg = 0x01d8,
1549 .halt_bit = 6,
1550 .clkr = {
1551 .enable_reg = 0x0018,
1552 .enable_mask = BIT(24),
1553 .hw.init = &(struct clk_init_data){
1554 .name = "gmem_axi_clk",
1555 .ops = &clk_branch_ops,
1556 .flags = CLK_IS_ROOT,
1557 },
1558 },
1559};
1560
1561static struct clk_branch ijpeg_axi_clk = {
1562 .hwcg_reg = 0x0018,
1563 .hwcg_bit = 11,
1564 .halt_reg = 0x01d8,
1565 .halt_bit = 4,
1566 .clkr = {
1567 .enable_reg = 0x0018,
1568 .enable_mask = BIT(21),
1569 .hw.init = &(struct clk_init_data){
1570 .name = "ijpeg_axi_clk",
1571 .ops = &clk_branch_ops,
1572 .flags = CLK_IS_ROOT,
1573 },
1574 },
1575};
1576
1577static struct clk_branch mmss_imem_axi_clk = {
1578 .hwcg_reg = 0x0018,
1579 .hwcg_bit = 15,
1580 .halt_reg = 0x01d8,
1581 .halt_bit = 7,
1582 .clkr = {
1583 .enable_reg = 0x0018,
1584 .enable_mask = BIT(22),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "mmss_imem_axi_clk",
1587 .ops = &clk_branch_ops,
1588 .flags = CLK_IS_ROOT,
1589 },
1590 },
1591};
1592
1593static struct clk_branch jpegd_axi_clk = {
1594 .halt_reg = 0x01d8,
1595 .halt_bit = 5,
1596 .clkr = {
1597 .enable_reg = 0x0018,
1598 .enable_mask = BIT(25),
1599 .hw.init = &(struct clk_init_data){
1600 .name = "jpegd_axi_clk",
1601 .ops = &clk_branch_ops,
1602 .flags = CLK_IS_ROOT,
1603 },
1604 },
1605};
1606
1607static struct clk_branch vcodec_axi_b_clk = {
1608 .hwcg_reg = 0x0114,
1609 .hwcg_bit = 22,
1610 .halt_reg = 0x01e8,
1611 .halt_bit = 25,
1612 .clkr = {
1613 .enable_reg = 0x0114,
1614 .enable_mask = BIT(23),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "vcodec_axi_b_clk",
1617 .ops = &clk_branch_ops,
1618 .flags = CLK_IS_ROOT,
1619 },
1620 },
1621};
1622
1623static struct clk_branch vcodec_axi_a_clk = {
1624 .hwcg_reg = 0x0114,
1625 .hwcg_bit = 24,
1626 .halt_reg = 0x01e8,
1627 .halt_bit = 26,
1628 .clkr = {
1629 .enable_reg = 0x0114,
1630 .enable_mask = BIT(25),
1631 .hw.init = &(struct clk_init_data){
1632 .name = "vcodec_axi_a_clk",
1633 .ops = &clk_branch_ops,
1634 .flags = CLK_IS_ROOT,
1635 },
1636 },
1637};
1638
1639static struct clk_branch vcodec_axi_clk = {
1640 .hwcg_reg = 0x0018,
1641 .hwcg_bit = 13,
1642 .halt_reg = 0x01d8,
1643 .halt_bit = 3,
1644 .clkr = {
1645 .enable_reg = 0x0018,
1646 .enable_mask = BIT(19),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "vcodec_axi_clk",
1649 .ops = &clk_branch_ops,
1650 .flags = CLK_IS_ROOT,
1651 },
1652 },
1653};
1654
1655static struct clk_branch vfe_axi_clk = {
1656 .halt_reg = 0x01d8,
1657 .halt_bit = 0,
1658 .clkr = {
1659 .enable_reg = 0x0018,
1660 .enable_mask = BIT(18),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "vfe_axi_clk",
1663 .ops = &clk_branch_ops,
1664 .flags = CLK_IS_ROOT,
1665 },
1666 },
1667};
1668
1669static struct clk_branch mdp_axi_clk = {
1670 .hwcg_reg = 0x0018,
1671 .hwcg_bit = 16,
1672 .halt_reg = 0x01d8,
1673 .halt_bit = 8,
1674 .clkr = {
1675 .enable_reg = 0x0018,
1676 .enable_mask = BIT(23),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "mdp_axi_clk",
1679 .ops = &clk_branch_ops,
1680 .flags = CLK_IS_ROOT,
1681 },
1682 },
1683};
1684
1685static struct clk_branch rot_axi_clk = {
1686 .hwcg_reg = 0x0020,
1687 .hwcg_bit = 25,
1688 .halt_reg = 0x01d8,
1689 .halt_bit = 2,
1690 .clkr = {
1691 .enable_reg = 0x0020,
1692 .enable_mask = BIT(24),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "rot_axi_clk",
1695 .ops = &clk_branch_ops,
1696 .flags = CLK_IS_ROOT,
1697 },
1698 },
1699};
1700
1701static struct clk_branch vpe_axi_clk = {
1702 .hwcg_reg = 0x0020,
1703 .hwcg_bit = 27,
1704 .halt_reg = 0x01d8,
1705 .halt_bit = 1,
1706 .clkr = {
1707 .enable_reg = 0x0020,
1708 .enable_mask = BIT(26),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "vpe_axi_clk",
1711 .ops = &clk_branch_ops,
1712 .flags = CLK_IS_ROOT,
1713 },
1714 },
1715};
1716
1717static struct clk_branch gfx3d_axi_clk = {
1718 .hwcg_reg = 0x0244,
1719 .hwcg_bit = 24,
1720 .halt_reg = 0x0240,
1721 .halt_bit = 30,
1722 .clkr = {
1723 .enable_reg = 0x0244,
1724 .enable_mask = BIT(25),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "gfx3d_axi_clk",
1727 .ops = &clk_branch_ops,
1728 .flags = CLK_IS_ROOT,
1729 },
1730 },
1731};
1732
1733static struct clk_branch amp_ahb_clk = {
1734 .halt_reg = 0x01dc,
1735 .halt_bit = 18,
1736 .clkr = {
1737 .enable_reg = 0x0008,
1738 .enable_mask = BIT(24),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "amp_ahb_clk",
1741 .ops = &clk_branch_ops,
1742 .flags = CLK_IS_ROOT,
1743 },
1744 },
1745};
1746
1747static struct clk_branch csi_ahb_clk = {
1748 .halt_reg = 0x01dc,
1749 .halt_bit = 16,
1750 .clkr = {
1751 .enable_reg = 0x0008,
1752 .enable_mask = BIT(7),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "csi_ahb_clk",
1755 .ops = &clk_branch_ops,
1756 .flags = CLK_IS_ROOT
1757 },
1758 },
1759};
1760
1761static struct clk_branch dsi_m_ahb_clk = {
1762 .halt_reg = 0x01dc,
1763 .halt_bit = 19,
1764 .clkr = {
1765 .enable_reg = 0x0008,
1766 .enable_mask = BIT(9),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "dsi_m_ahb_clk",
1769 .ops = &clk_branch_ops,
1770 .flags = CLK_IS_ROOT,
1771 },
1772 },
1773};
1774
1775static struct clk_branch dsi_s_ahb_clk = {
1776 .hwcg_reg = 0x0038,
1777 .hwcg_bit = 20,
1778 .halt_reg = 0x01dc,
1779 .halt_bit = 21,
1780 .clkr = {
1781 .enable_reg = 0x0008,
1782 .enable_mask = BIT(18),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "dsi_s_ahb_clk",
1785 .ops = &clk_branch_ops,
1786 .flags = CLK_IS_ROOT,
1787 },
1788 },
1789};
1790
1791static struct clk_branch dsi2_m_ahb_clk = {
1792 .halt_reg = 0x01d8,
1793 .halt_bit = 18,
1794 .clkr = {
1795 .enable_reg = 0x0008,
1796 .enable_mask = BIT(17),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "dsi2_m_ahb_clk",
1799 .ops = &clk_branch_ops,
1800 .flags = CLK_IS_ROOT
1801 },
1802 },
1803};
1804
1805static struct clk_branch dsi2_s_ahb_clk = {
1806 .hwcg_reg = 0x0038,
1807 .hwcg_bit = 15,
1808 .halt_reg = 0x01dc,
1809 .halt_bit = 20,
1810 .clkr = {
1811 .enable_reg = 0x0008,
1812 .enable_mask = BIT(22),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "dsi2_s_ahb_clk",
1815 .ops = &clk_branch_ops,
1816 .flags = CLK_IS_ROOT,
1817 },
1818 },
1819};
1820
1821static struct clk_branch gfx2d0_ahb_clk = {
1822 .hwcg_reg = 0x0038,
1823 .hwcg_bit = 28,
1824 .halt_reg = 0x01dc,
1825 .halt_bit = 2,
1826 .clkr = {
1827 .enable_reg = 0x0008,
1828 .enable_mask = BIT(19),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "gfx2d0_ahb_clk",
1831 .ops = &clk_branch_ops,
1832 .flags = CLK_IS_ROOT,
1833 },
1834 },
1835};
1836
1837static struct clk_branch gfx2d1_ahb_clk = {
1838 .hwcg_reg = 0x0038,
1839 .hwcg_bit = 29,
1840 .halt_reg = 0x01dc,
1841 .halt_bit = 3,
1842 .clkr = {
1843 .enable_reg = 0x0008,
1844 .enable_mask = BIT(2),
1845 .hw.init = &(struct clk_init_data){
1846 .name = "gfx2d1_ahb_clk",
1847 .ops = &clk_branch_ops,
1848 .flags = CLK_IS_ROOT,
1849 },
1850 },
1851};
1852
1853static struct clk_branch gfx3d_ahb_clk = {
1854 .hwcg_reg = 0x0038,
1855 .hwcg_bit = 27,
1856 .halt_reg = 0x01dc,
1857 .halt_bit = 4,
1858 .clkr = {
1859 .enable_reg = 0x0008,
1860 .enable_mask = BIT(3),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gfx3d_ahb_clk",
1863 .ops = &clk_branch_ops,
1864 .flags = CLK_IS_ROOT,
1865 },
1866 },
1867};
1868
1869static struct clk_branch hdmi_m_ahb_clk = {
1870 .hwcg_reg = 0x0038,
1871 .hwcg_bit = 21,
1872 .halt_reg = 0x01dc,
1873 .halt_bit = 5,
1874 .clkr = {
1875 .enable_reg = 0x0008,
1876 .enable_mask = BIT(14),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "hdmi_m_ahb_clk",
1879 .ops = &clk_branch_ops,
1880 .flags = CLK_IS_ROOT,
1881 },
1882 },
1883};
1884
1885static struct clk_branch hdmi_s_ahb_clk = {
1886 .hwcg_reg = 0x0038,
1887 .hwcg_bit = 22,
1888 .halt_reg = 0x01dc,
1889 .halt_bit = 6,
1890 .clkr = {
1891 .enable_reg = 0x0008,
1892 .enable_mask = BIT(4),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "hdmi_s_ahb_clk",
1895 .ops = &clk_branch_ops,
1896 .flags = CLK_IS_ROOT,
1897 },
1898 },
1899};
1900
1901static struct clk_branch ijpeg_ahb_clk = {
1902 .halt_reg = 0x01dc,
1903 .halt_bit = 9,
1904 .clkr = {
1905 .enable_reg = 0x0008,
1906 .enable_mask = BIT(5),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "ijpeg_ahb_clk",
1909 .ops = &clk_branch_ops,
1910 .flags = CLK_IS_ROOT
1911 },
1912 },
1913};
1914
1915static struct clk_branch mmss_imem_ahb_clk = {
1916 .hwcg_reg = 0x0038,
1917 .hwcg_bit = 12,
1918 .halt_reg = 0x01dc,
1919 .halt_bit = 10,
1920 .clkr = {
1921 .enable_reg = 0x0008,
1922 .enable_mask = BIT(6),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "mmss_imem_ahb_clk",
1925 .ops = &clk_branch_ops,
1926 .flags = CLK_IS_ROOT
1927 },
1928 },
1929};
1930
1931static struct clk_branch jpegd_ahb_clk = {
1932 .halt_reg = 0x01dc,
1933 .halt_bit = 7,
1934 .clkr = {
1935 .enable_reg = 0x0008,
1936 .enable_mask = BIT(21),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "jpegd_ahb_clk",
1939 .ops = &clk_branch_ops,
1940 .flags = CLK_IS_ROOT,
1941 },
1942 },
1943};
1944
1945static struct clk_branch mdp_ahb_clk = {
1946 .halt_reg = 0x01dc,
1947 .halt_bit = 11,
1948 .clkr = {
1949 .enable_reg = 0x0008,
1950 .enable_mask = BIT(10),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "mdp_ahb_clk",
1953 .ops = &clk_branch_ops,
1954 .flags = CLK_IS_ROOT,
1955 },
1956 },
1957};
1958
1959static struct clk_branch rot_ahb_clk = {
1960 .halt_reg = 0x01dc,
1961 .halt_bit = 13,
1962 .clkr = {
1963 .enable_reg = 0x0008,
1964 .enable_mask = BIT(12),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "rot_ahb_clk",
1967 .ops = &clk_branch_ops,
1968 .flags = CLK_IS_ROOT
1969 },
1970 },
1971};
1972
1973static struct clk_branch smmu_ahb_clk = {
1974 .hwcg_reg = 0x0008,
1975 .hwcg_bit = 26,
1976 .halt_reg = 0x01dc,
1977 .halt_bit = 22,
1978 .clkr = {
1979 .enable_reg = 0x0008,
1980 .enable_mask = BIT(15),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "smmu_ahb_clk",
1983 .ops = &clk_branch_ops,
1984 .flags = CLK_IS_ROOT,
1985 },
1986 },
1987};
1988
1989static struct clk_branch tv_enc_ahb_clk = {
1990 .halt_reg = 0x01dc,
1991 .halt_bit = 23,
1992 .clkr = {
1993 .enable_reg = 0x0008,
1994 .enable_mask = BIT(25),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "tv_enc_ahb_clk",
1997 .ops = &clk_branch_ops,
1998 .flags = CLK_IS_ROOT,
1999 },
2000 },
2001};
2002
2003static struct clk_branch vcodec_ahb_clk = {
2004 .hwcg_reg = 0x0038,
2005 .hwcg_bit = 26,
2006 .halt_reg = 0x01dc,
2007 .halt_bit = 12,
2008 .clkr = {
2009 .enable_reg = 0x0008,
2010 .enable_mask = BIT(11),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "vcodec_ahb_clk",
2013 .ops = &clk_branch_ops,
2014 .flags = CLK_IS_ROOT,
2015 },
2016 },
2017};
2018
2019static struct clk_branch vfe_ahb_clk = {
2020 .halt_reg = 0x01dc,
2021 .halt_bit = 14,
2022 .clkr = {
2023 .enable_reg = 0x0008,
2024 .enable_mask = BIT(13),
2025 .hw.init = &(struct clk_init_data){
2026 .name = "vfe_ahb_clk",
2027 .ops = &clk_branch_ops,
2028 .flags = CLK_IS_ROOT,
2029 },
2030 },
2031};
2032
2033static struct clk_branch vpe_ahb_clk = {
2034 .halt_reg = 0x01dc,
2035 .halt_bit = 15,
2036 .clkr = {
2037 .enable_reg = 0x0008,
2038 .enable_mask = BIT(16),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "vpe_ahb_clk",
2041 .ops = &clk_branch_ops,
2042 .flags = CLK_IS_ROOT,
2043 },
2044 },
2045};
2046
2047static struct clk_regmap *mmcc_msm8960_clks[] = {
2048 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2049 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2050 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2051 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2052 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2053 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2054 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2055 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2056 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2057 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2058 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2059 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2060 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2061 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2062 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2063 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2064 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2065 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2066 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2067 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2068 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2069 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2070 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2071 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2072 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2073 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2074 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2075 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2076 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2077 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2078 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2079 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2080 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2081 [CSI0_SRC] = &csi0_src.clkr,
2082 [CSI0_CLK] = &csi0_clk.clkr,
2083 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2084 [CSI1_SRC] = &csi1_src.clkr,
2085 [CSI1_CLK] = &csi1_clk.clkr,
2086 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2087 [CSI2_SRC] = &csi2_src.clkr,
2088 [CSI2_CLK] = &csi2_clk.clkr,
2089 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2090 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2091 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2092 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2093 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2094 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2095 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2096 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2097 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2098 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2099 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2100 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2101 [GFX3D_SRC] = &gfx3d_src.clkr,
2102 [GFX3D_CLK] = &gfx3d_clk.clkr,
2103 [IJPEG_SRC] = &ijpeg_src.clkr,
2104 [IJPEG_CLK] = &ijpeg_clk.clkr,
2105 [JPEGD_SRC] = &jpegd_src.clkr,
2106 [JPEGD_CLK] = &jpegd_clk.clkr,
2107 [MDP_SRC] = &mdp_src.clkr,
2108 [MDP_CLK] = &mdp_clk.clkr,
2109 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2110 [ROT_SRC] = &rot_src.clkr,
2111 [ROT_CLK] = &rot_clk.clkr,
2112 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2113 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2114 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2115 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2116 [TV_SRC] = &tv_src.clkr,
2117 [VCODEC_SRC] = &vcodec_src.clkr,
2118 [VCODEC_CLK] = &vcodec_clk.clkr,
2119 [VFE_SRC] = &vfe_src.clkr,
2120 [VFE_CLK] = &vfe_clk.clkr,
2121 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2122 [VPE_SRC] = &vpe_src.clkr,
2123 [VPE_CLK] = &vpe_clk.clkr,
2124 [CAMCLK0_SRC] = &camclk0_src.clkr,
2125 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2126 [CAMCLK1_SRC] = &camclk1_src.clkr,
2127 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2128 [CAMCLK2_SRC] = &camclk2_src.clkr,
2129 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2130 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2131 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2132 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2133 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2134 [PLL2] = &pll2.clkr,
2135};
2136
2137static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2138 [VPE_AXI_RESET] = { 0x0208, 15 },
2139 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2140 [MPD_AXI_RESET] = { 0x0208, 13 },
2141 [VFE_AXI_RESET] = { 0x0208, 9 },
2142 [SP_AXI_RESET] = { 0x0208, 8 },
2143 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2144 [ROT_AXI_RESET] = { 0x0208, 6 },
2145 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2146 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2147 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2148 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2149 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2150 [FAB_S0_AXI_RESET] = { 0x0208 },
2151 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2152 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2153 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2154 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2155 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2156 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2157 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2158 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2159 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2160 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2161 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2162 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2163 [APU_AHB_RESET] = { 0x020c, 18 },
2164 [CSI_AHB_RESET] = { 0x020c, 17 },
2165 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2166 [VPE_AHB_RESET] = { 0x020c, 14 },
2167 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2168 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2169 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2170 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2171 [HDMI_AHB_RESET] = { 0x020c, 9 },
2172 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2173 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2174 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2175 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2176 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2177 [MDP_AHB_RESET] = { 0x020c, 3 },
2178 [ROT_AHB_RESET] = { 0x020c, 2 },
2179 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2180 [VFE_AHB_RESET] = { 0x020c, 0 },
2181 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2182 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2183 [CSIPHY2_RESET] = { 0x0210, 29 },
2184 [CSI_PIX1_RESET] = { 0x0210, 28 },
2185 [CSIPHY0_RESET] = { 0x0210, 27 },
2186 [CSIPHY1_RESET] = { 0x0210, 26 },
2187 [DSI2_RESET] = { 0x0210, 25 },
2188 [VFE_CSI_RESET] = { 0x0210, 24 },
2189 [MDP_RESET] = { 0x0210, 21 },
2190 [AMP_RESET] = { 0x0210, 20 },
2191 [JPEGD_RESET] = { 0x0210, 19 },
2192 [CSI1_RESET] = { 0x0210, 18 },
2193 [VPE_RESET] = { 0x0210, 17 },
2194 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2195 [VFE_RESET] = { 0x0210, 15 },
2196 [GFX2D0_RESET] = { 0x0210, 14 },
2197 [GFX2D1_RESET] = { 0x0210, 13 },
2198 [GFX3D_RESET] = { 0x0210, 12 },
2199 [HDMI_RESET] = { 0x0210, 11 },
2200 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2201 [IJPEG_RESET] = { 0x0210, 9 },
2202 [CSI0_RESET] = { 0x0210, 8 },
2203 [DSI_RESET] = { 0x0210, 7 },
2204 [VCODEC_RESET] = { 0x0210, 6 },
2205 [MDP_TV_RESET] = { 0x0210, 4 },
2206 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2207 [ROT_RESET] = { 0x0210, 2 },
2208 [TV_HDMI_RESET] = { 0x0210, 1 },
2209 [TV_ENC_RESET] = { 0x0210 },
2210 [CSI2_RESET] = { 0x0214, 2 },
2211 [CSI_RDI1_RESET] = { 0x0214, 1 },
2212 [CSI_RDI2_RESET] = { 0x0214 },
2213};
2214
2215static const struct regmap_config mmcc_msm8960_regmap_config = {
2216 .reg_bits = 32,
2217 .reg_stride = 4,
2218 .val_bits = 32,
2219 .max_register = 0x334,
2220 .fast_io = true,
2221};
2222
Stephen Boyd49fc8252014-03-21 17:59:37 -07002223static const struct qcom_cc_desc mmcc_msm8960_desc = {
2224 .config = &mmcc_msm8960_regmap_config,
2225 .clks = mmcc_msm8960_clks,
2226 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2227 .resets = mmcc_msm8960_resets,
2228 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2229};
2230
Stephen Boyd6d00b562014-01-15 10:47:29 -08002231static const struct of_device_id mmcc_msm8960_match_table[] = {
2232 { .compatible = "qcom,mmcc-msm8960" },
2233 { }
2234};
2235MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2236
Stephen Boyd6d00b562014-01-15 10:47:29 -08002237static int mmcc_msm8960_probe(struct platform_device *pdev)
2238{
Stephen Boyd49fc8252014-03-21 17:59:37 -07002239 return qcom_cc_probe(pdev, &mmcc_msm8960_desc);
Stephen Boyd6d00b562014-01-15 10:47:29 -08002240}
2241
2242static int mmcc_msm8960_remove(struct platform_device *pdev)
2243{
Stephen Boyd49fc8252014-03-21 17:59:37 -07002244 qcom_cc_remove(pdev);
Stephen Boyd6d00b562014-01-15 10:47:29 -08002245 return 0;
2246}
2247
2248static struct platform_driver mmcc_msm8960_driver = {
2249 .probe = mmcc_msm8960_probe,
2250 .remove = mmcc_msm8960_remove,
2251 .driver = {
2252 .name = "mmcc-msm8960",
2253 .owner = THIS_MODULE,
2254 .of_match_table = mmcc_msm8960_match_table,
2255 },
2256};
2257
2258module_platform_driver(mmcc_msm8960_driver);
2259
2260MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2261MODULE_LICENSE("GPL v2");
2262MODULE_ALIAS("platform:mmcc-msm8960");