Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | |
| 3 | (c) SYSTEC electronic GmbH, D-07973 Greiz, August-Bebel-Str. 29 |
| 4 | www.systec-electronic.com |
| 5 | |
| 6 | Project: openPOWERLINK |
| 7 | |
| 8 | Description: interface for ethernetdriver |
| 9 | "fast ethernet controller" (FEC) |
| 10 | freescale coldfire MCF528x and compatible FEC |
| 11 | |
| 12 | License: |
| 13 | |
| 14 | Redistribution and use in source and binary forms, with or without |
| 15 | modification, are permitted provided that the following conditions |
| 16 | are met: |
| 17 | |
| 18 | 1. Redistributions of source code must retain the above copyright |
| 19 | notice, this list of conditions and the following disclaimer. |
| 20 | |
| 21 | 2. Redistributions in binary form must reproduce the above copyright |
| 22 | notice, this list of conditions and the following disclaimer in the |
| 23 | documentation and/or other materials provided with the distribution. |
| 24 | |
| 25 | 3. Neither the name of SYSTEC electronic GmbH nor the names of its |
| 26 | contributors may be used to endorse or promote products derived |
| 27 | from this software without prior written permission. For written |
| 28 | permission, please contact info@systec-electronic.com. |
| 29 | |
| 30 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 31 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 32 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 33 | FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 34 | COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 35 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 36 | BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 38 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 39 | LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| 40 | ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 41 | POSSIBILITY OF SUCH DAMAGE. |
| 42 | |
| 43 | Severability Clause: |
| 44 | |
| 45 | If a provision of this License is or becomes illegal, invalid or |
| 46 | unenforceable in any jurisdiction, that shall not affect: |
| 47 | 1. the validity or enforceability in that jurisdiction of any other |
| 48 | provision of this License; or |
| 49 | 2. the validity or enforceability in other jurisdictions of that or |
| 50 | any other provision of this License. |
| 51 | |
| 52 | ------------------------------------------------------------------------- |
| 53 | |
| 54 | $RCSfile: EdrvFec5282.h,v $ |
| 55 | |
| 56 | $Author: D.Krueger $ |
| 57 | |
| 58 | $Revision: 1.3 $ $Date: 2008/04/17 21:36:32 $ |
| 59 | |
| 60 | $State: Exp $ |
| 61 | |
| 62 | Build Environment: |
| 63 | Dev C++ and GNU-Compiler for m68k |
| 64 | |
| 65 | ------------------------------------------------------------------------- |
| 66 | |
| 67 | Revision History: |
| 68 | |
| 69 | 2005/08/01 m.b.: start of implementation |
| 70 | |
| 71 | ****************************************************************************/ |
| 72 | |
| 73 | #ifndef _EDRVFEC_H_ |
| 74 | #define _EDRVFEC_H_ |
| 75 | |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 76 | //--------------------------------------------------------------------------- |
| 77 | // const defines |
| 78 | //--------------------------------------------------------------------------- |
| 79 | // base addresses |
| 80 | #define FEC0_ADDR 0x0000 |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 81 | #define FEC1_ADDR 0x0000 //tbd |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 82 | |
| 83 | // control / status registers |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 84 | #define FEC_EIR 0x1004 // interrupt event register |
| 85 | #define FEC_EIMR 0x1008 // interrupt mask register |
| 86 | #define FEC_RDAR 0x1010 // receive descriptor active register |
| 87 | #define FEC_TDAR 0x1014 // transmit descriptor active register |
| 88 | #define FEC_ECR 0x1024 // ethernet control register |
| 89 | #define FEC_MMFR 0x1040 // MII data register |
| 90 | #define FEC_MSCR 0x1044 // MII speed register |
| 91 | #define FEC_MIBC 0x1064 // MIB control/status register |
| 92 | #define FEC_RCR 0x1084 // receive control register |
| 93 | #define FEC_TCR 0x10C4 // transmit control register |
| 94 | #define FEC_PALR 0x10E4 // physical address low register |
| 95 | #define FEC_PAUR 0x10E8 // physical address high + type register |
| 96 | #define FEC_OPD 0x10EC // opcode + pause register |
| 97 | #define FEC_IAUR 0x1118 // upper 32 bit of individual hash table |
| 98 | #define FEC_IALR 0x111C // lower 32 bit of individual hash table |
| 99 | #define FEC_GAUR 0x1120 // upper 32 bit of group hash table |
| 100 | #define FEC_GALR 0x1124 // lower 32 bit of group hash table |
| 101 | #define FEC_TFWR 0x1144 // transmit FIFO watermark |
| 102 | #define FEC_FRBR 0x114C // FIFO receive bound register |
| 103 | #define FEC_FRSR 0x1150 // FIFO receive FIFO start register |
| 104 | #define FEC_ERDSR 0x1180 // pointer to receive descriptor ring |
| 105 | #define FEC_ETDSR 0x1184 // pointer to transmit descriptor ring |
| 106 | #define FEC_EMRBR 0x1188 // maximum receive buffer size |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 107 | |
| 108 | // mib block counters memory map |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 109 | #define FEC_RMON_T_DROP 0x1200 // count of frames not counted correctly |
| 110 | #define FEC_RMON_T_PACKETS 0x1204 // RMON tx packet count |
| 111 | #define FEC_RMON_T_BC_PKT 0x1208 // RMON tx broadcast packets |
| 112 | #define FEC_RMON_T_MC_PKT 0x120C // RMON tx multicast packets |
| 113 | #define FEC_RMON_T_CRC_ALIGN 0x1210 // RMON tx packets w CRC/align error |
| 114 | #define FEC_RMON_T_UNDERSIZE 0x1214 // RMON tx packets < 64 bytes, good CRC |
| 115 | #define FEC_RMON_T_OVERSIZE 0x1218 // RMON tx packets > MAX_FL bytes, good CRC |
| 116 | #define FEC_RMON_T_FRAG 0x121C // RMON tx packets < 64 bytes, bad CRC |
| 117 | #define FEC_RMON_T_JAB 0x1220 // RMON tx packets > MAX_FL bytes, bad CRC |
| 118 | #define FEC_RMON_T_COL 0x1224 // RMON tx collision count |
| 119 | #define FEC_RMON_T_P64 0x1228 // RMON tx 64 byte packets |
| 120 | #define FEC_RMON_T_P65TO127 0x122C // RMON tx 65 to 127 byte packets |
| 121 | #define FEC_RMON_T_P128TO255 0x1230 // RMON tx 128 to 255 byte packets |
| 122 | #define FEC_RMON_T_P256TO511 0x1234 // RMON tx 256 to 511 byte packets |
| 123 | #define FEC_RMON_T_P512TO1023 0x1238 // RMON tx 512 to 1023 byte packets |
| 124 | #define FEC_RMON_T_P1024TO2047 0x123C // RMON tx 1024 to 2047 byte packets |
| 125 | #define FEC_RMON_T_P_GTE2048 0x1240 // RMON tx w > 2048 bytes |
| 126 | #define FEC_RMON_T_OCTETS 0x1244 // RMON tx octets |
| 127 | #define FEC_IEEE_T_DROP 0x1248 // count of frames not counted correctly |
| 128 | #define FEC_IEEE_T_FRAME_OK 0x124C // frames transmitted OK |
| 129 | #define FEC_IEEE_T_1COL 0x1250 // frames transmitted with single collision |
| 130 | #define FEC_IEEE_T_MCOL 0x1254 // frames transmitted with multiple collisions |
| 131 | #define FEC_IEEE_T_DEF 0x1258 // frames transmitted after deferral delay |
| 132 | #define FEC_IEEE_T_LCOL 0x125C // frames transmitted with late collisions |
| 133 | #define FEC_IEEE_T_EXCOL 0x1260 // frames transmitted with excessive collisions |
| 134 | #define FEC_IEEE_T_MACERR 0x1264 // frames transmitted with tx-FIFO underrun |
| 135 | #define FEC_IEEE_T_CSERR 0x1268 // frames transmitted with carrier sense error |
| 136 | #define FEC_IEEE_T_SQE 0x126C // frames transmitted with SQE error |
| 137 | #define FEC_IEEE_T_FDXFC 0x1270 // flow control pause frames transmitted |
| 138 | #define FEC_IEEE_T_OCTETS_OK 0x1274 // octet count for frames transmitted w/o error |
| 139 | #define FEC_RMON_R_PACKETS 0x1284 // RMON rx packet count |
| 140 | #define FEC_RMON_R_BC_PKT 0x1288 // RMON rx broadcast packets |
| 141 | #define FEC_RMON_R_MC_PKT 0x128C // RMON rx multicast packets |
| 142 | #define FEC_RMON_R_CRC_ALIGN 0x1290 // RMON rx packets w CRC/align error |
| 143 | #define FEC_RMON_R_UNDERSIZE 0x1294 // RMON rx packets < 64 bytes, good CRC |
| 144 | #define FEC_RMON_R_OVERSIZE 0x1298 // RMON rx packets > MAX_FL bytes, good CRC |
| 145 | #define FEC_RMON_R_FRAG 0x129C // RMON rx packets < 64 bytes, bad CRC |
| 146 | #define FEC_RMON_R_JAB 0x12A0 // RMON rx packets > MAX_FL bytes, bad CRC |
| 147 | #define FEC_RMON_R_RESVD_0 0x12A4 // |
| 148 | #define FEC_RMON_R_P64 0x12A8 // RMON rx 64 byte packets |
| 149 | #define FEC_RMON_R_P65T0127 0x12AC // RMON rx 65 to 127 byte packets |
| 150 | #define FEC_RMON_R_P128TO255 0x12B0 // RMON rx 128 to 255 byte packets |
| 151 | #define FEC_RMON_R_P256TO511 0x12B4 // RMON rx 256 to 511 byte packets |
| 152 | #define FEC_RMON_R_P512TO1023 0x12B8 // RMON rx 512 to 1023 byte packets |
| 153 | #define FEC_RMON_R_P1024TO2047 0x12BC // RMON rx 1024 to 2047 byte packets |
| 154 | #define FEC_RMON_R_GTE2048 0x12C0 // RMON rx w > 2048 bytes |
| 155 | #define FEC_RMON_R_OCTETS 0x12C4 // RMON rx octets |
| 156 | #define FEC_IEEE_R_DROP 0x12C8 // count of frames not counted correctly |
| 157 | #define FEC_IEEE_R_FRAME_OK 0x12CC // frames received OK |
| 158 | #define FEC_IEEE_R_CRC 0x12D0 // frames received with CRC error |
| 159 | #define FEC_IEEE_R_ALIGN 0x12D4 // frames received with alignment error |
| 160 | #define FEC_IEEE_R_MACERR 0x12D8 // receive FIFO overflow count |
| 161 | #define FEC_IEEE_R_FDXFC 0x12DC // flow control pause frames received |
| 162 | #define FEC_IEEE_R_OCTETS_OK 0x12E0 // octet count for frames rcvd w/o error |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 163 | |
| 164 | // register bit definitions and macros |
| 165 | #define FEC_EIR_UN (0x00080000) |
| 166 | #define FEC_EIR_RL (0x00100000) |
| 167 | #define FEC_EIR_LC (0x00200000) |
| 168 | #define FEC_EIR_EBERR (0x00400000) |
| 169 | #define FEC_EIR_MII (0x00800000) |
| 170 | #define FEC_EIR_RXB (0x01000000) |
| 171 | #define FEC_EIR_RXF (0x02000000) |
| 172 | #define FEC_EIR_TXB (0x04000000) |
| 173 | #define FEC_EIR_TXF (0x08000000) |
| 174 | #define FEC_EIR_GRA (0x10000000) |
| 175 | #define FEC_EIR_BABT (0x20000000) |
| 176 | #define FEC_EIR_BABR (0x40000000) |
| 177 | #define FEC_EIR_HBERR (0x80000000) |
| 178 | |
| 179 | #define FEC_EIMR_UN (0x00080000) |
| 180 | #define FEC_EIMR_RL (0x00100000) |
| 181 | #define FEC_EIMR_LC (0x00200000) |
| 182 | #define FEC_EIMR_EBERR (0x00400000) |
| 183 | #define FEC_EIMR_MII (0x00800000) |
| 184 | #define FEC_EIMR_RXB (0x01000000) |
| 185 | #define FEC_EIMR_RXF (0x02000000) |
| 186 | #define FEC_EIMR_TXB (0x04000000) |
| 187 | #define FEC_EIMR_TXF (0x08000000) |
| 188 | #define FEC_EIMR_GRA (0x10000000) |
| 189 | #define FEC_EIMR_BABT (0x20000000) |
| 190 | #define FEC_EIMR_BABR (0x40000000) |
| 191 | #define FEC_EIMR_HBERR (0x80000000) |
| 192 | |
| 193 | #define FEC_RDAR_R_DES_ACTIVE (0x01000000) |
| 194 | |
| 195 | #define FEC_TDAR_X_DES_ACTIVE (0x01000000) |
| 196 | |
| 197 | #define FEC_ECR_RESET (0x00000001) |
| 198 | #define FEC_ECR_ETHER_EN (0x00000002) |
| 199 | |
| 200 | #define FEC_MMFR_DATA(x) (((x) & 0xFFFF)) |
| 201 | #define FEC_MMFR_TA (0x00020000) |
| 202 | #define FEC_MMFR_RA(x) (((x) & 0x1F) << 18) |
| 203 | #define FEC_MMFR_PA(x) (((x) & 0x1F) << 23) |
| 204 | #define FEC_MMFR_OP_WR (0x10000000) |
| 205 | #define FEC_MMFR_OP_RD (0x20000000) |
| 206 | #define FEC_MMFR_ST (0x40000000) |
| 207 | |
| 208 | #define FEC_MSCR_MII_SPEED(x) (((x) & 0x1F) << 1) |
| 209 | #define FEC_MSCR_DIS_PREAMBLE (0x00000008) |
| 210 | |
| 211 | #define FEC_MIBC_MIB_IDLE (0x40000000) |
| 212 | #define FEC_MIBC_MIB_DISABLE (0x80000000) |
| 213 | |
| 214 | #define FEC_RCR_LOOP (0x00000001) |
| 215 | #define FEC_RCR_DRT (0x00000002) |
| 216 | #define FEC_RCR_MII_MODE (0x00000004) |
| 217 | #define FEC_RCR_PROM (0x00000008) |
| 218 | #define FEC_RCR_BC_REJ (0x00000010) |
| 219 | #define FEC_RCR_FCE (0x00000020) |
| 220 | #define FEC_RCR_MAX_FL(x) (((x) & 0x07FF) << 16) |
| 221 | |
| 222 | #define FEC_TCR_GTS (0x00000001) |
| 223 | #define FEC_TCR_HBC (0x00000002) |
| 224 | #define FEC_TCR_FDEN (0x00000004) |
| 225 | #define FEC_TCR_TFC_PAUSE (0x00000008) |
| 226 | #define FEC_TCR_RFC_PAUSE (0x00000010) |
| 227 | |
| 228 | #define FEC_PALR_BYTE3(x) (((x) & 0xFF) << 0) |
| 229 | #define FEC_PALR_BYTE2(x) (((x) & 0xFF) << 8) |
| 230 | #define FEC_PALR_BYTE1(x) (((x) & 0xFF) << 16) |
| 231 | #define FEC_PALR_BYTE0(x) (((x) & 0xFF) << 24) |
| 232 | |
| 233 | //#define FEC_PAUR_TYPE(x) (((x) & 0xFFFF) << 0) |
| 234 | #define FEC_PAUR_BYTE5(x) (((x) & 0xFF) << 16) |
| 235 | #define FEC_PAUR_BYTE4(x) (((x) & 0xFF) << 24) |
| 236 | |
| 237 | #define FEC_OPD_PAUSE_DUR(x) (((x) & 0xFFFF)) |
| 238 | //#define FEC_OPD_OPCODE(x) (((x) & 0xFFFF) << 16) |
| 239 | |
| 240 | //m.b. |
| 241 | #define FEC_IAUR_BYTE7(x) (((x) & 0xFF) << 0) |
| 242 | #define FEC_IAUR_BYTE6(x) (((x) & 0xFF) << 8) |
| 243 | #define FEC_IAUR_BYTE5(x) (((x) & 0xFF) << 16) |
| 244 | #define FEC_IAUR_BYTE4(x) (((x) & 0xFF) << 24) |
| 245 | |
| 246 | #define FEC_IALR_BYTE3(x) (((x) & 0xFF) << 0) |
| 247 | #define FEC_IALR_BYTE2(x) (((x) & 0xFF) << 8) |
| 248 | #define FEC_IALR_BYTE1(x) (((x) & 0xFF) << 16) |
| 249 | #define FEC_IALR_BYTE0(x) (((x) & 0xFF) << 24) |
| 250 | |
| 251 | #define FEC_GAUR_BYTE7(x) (((x) & 0xFF) << 0) |
| 252 | #define FEC_GAUR_BYTE6(x) (((x) & 0xFF) << 8) |
| 253 | #define FEC_GAUR_BYTE5(x) (((x) & 0xFF) << 16) |
| 254 | #define FEC_GAUR_BYTE4(x) (((x) & 0xFF) << 24) |
| 255 | |
| 256 | #define FEC_GALR_BYTE3(x) (((x) & 0xFF) << 0) |
| 257 | #define FEC_GALR_BYTE2(x) (((x) & 0xFF) << 8) |
| 258 | #define FEC_GALR_BYTE1(x) (((x) & 0xFF) << 16) |
| 259 | #define FEC_GALR_BYTE0(x) (((x) & 0xFF) << 24) |
| 260 | // ^^^^ |
| 261 | |
| 262 | #define FEC_TFWR_X_WMRK_64 (0x00000001) |
| 263 | #define FEC_TFWR_X_WMRK_128 (0x00000002) |
| 264 | #define FEC_TFWR_X_WMRK_192 (0x00000003) |
| 265 | |
| 266 | //m.b. |
| 267 | #define FEC_FRBR_R_BOUND(x) (((x) & 0xFF) << 2) |
| 268 | |
| 269 | //m.b. |
| 270 | #define FEC_FRSR_R_FSTART(x) (((x) & 0xFF) << 2) |
| 271 | |
| 272 | //m.b. |
| 273 | #define FEC_ERDSR_R_DES_START(x) (((x) & 0x3FFFFFFF) << 2) |
| 274 | |
| 275 | //m.b. |
| 276 | #define FEC_ETSDR_X_DES_START(x) (((x) & 0x3FFFFFFF) << 2) |
| 277 | |
| 278 | #define FEC_EMRBR_R_BUF_SIZE(x) (((x) & 0x7F) << 4) |
| 279 | |
| 280 | #define FEC_RxBD_TR 0x0001 |
| 281 | #define FEC_RxBD_OV 0x0002 |
| 282 | #define FEC_RxBD_CR 0x0004 |
| 283 | #define FEC_RxBD_NO 0x0010 |
| 284 | #define FEC_RxBD_LG 0x0020 |
| 285 | #define FEC_RxBD_MC 0x0040 |
| 286 | #define FEC_RxBD_BC 0x0080 |
| 287 | #define FEC_RxBD_M 0x0100 |
| 288 | #define FEC_RxBD_L 0x0800 |
| 289 | #define FEC_RxBD_R02 0x1000 |
| 290 | #define FEC_RxBD_W 0x2000 |
| 291 | #define FEC_RxBD_R01 0x4000 |
| 292 | #define FEC_RxBD_INUSE 0x4000 |
| 293 | #define FEC_RxBD_E 0x8000 |
| 294 | |
| 295 | //m.b. |
| 296 | //#define FEC_TxBD_CSL 0x0001 |
| 297 | //#define FEC_TxBD_UN 0x0002 |
| 298 | //#define FEC_TxBD_RL 0x0040 |
| 299 | //#define FEC_TxBD_LC 0x0080 |
| 300 | //#define FEC_TxBD_HB 0x0100 |
| 301 | //#define FEC_TxBD_DEF 0x0200 |
| 302 | #define FEC_TxBD_ABC 0x0200 |
| 303 | // ^^^^ |
| 304 | #define FEC_TxBD_TC 0x0400 |
| 305 | #define FEC_TxBD_L 0x0800 |
| 306 | #define FEC_TxBD_TO2 0x1000 |
| 307 | #define FEC_TxBD_W 0x2000 |
| 308 | #define FEC_TxBD_TO1 0x4000 |
| 309 | #define FEC_TxBD_INUSE 0x4000 |
| 310 | #define FEC_TxBD_R 0x8000 |
| 311 | |
| 312 | //--------------------------------------------------------------------------- |
| 313 | // types |
| 314 | //--------------------------------------------------------------------------- |
| 315 | |
| 316 | // Rx and Tx buffer descriptor format |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 317 | typedef struct { |
| 318 | WORD m_wStatus; // control / status --- used by edrv, do not change in application |
| 319 | WORD m_wLength; // transfer length |
| 320 | BYTE *m_pbData; // buffer address |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 321 | } tBufferDescr; |
| 322 | |
| 323 | //--------------------------------------------------------------------------- |
| 324 | // function prototypes |
| 325 | //--------------------------------------------------------------------------- |
| 326 | |
| 327 | #if (NO_OF_INSTANCES > 1) |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 328 | #define ECI_WRITE_DW_REG(off,val) (*(DWORD *)(void *)(&__IPSBAR[off]) = val) |
| 329 | #define ECI_READ_DW_REG(off) (*(DWORD *)(void *)(&__IPSBAR[off])) |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 330 | #else |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 331 | #if (EDRV_USED_ETH_CTRL == 0) |
| 332 | #define ECI_WRITE_DW_REG(off,val) (*(DWORD *)(void *)(&__IPSBAR[FEC0_ADDR+off]) = val) |
| 333 | #define ECI_READ_DW_REG(off) (*(DWORD *)(void *)(&__IPSBAR[FEC0_ADDR+off])) |
| 334 | #else |
| 335 | #define ECI_WRITE_DW_REG(off,val) (*(DWORD *)(void *)(&__IPSBAR[FEC1_ADDR+off]) = val) |
| 336 | #define ECI_READ_DW_REG(off) (*(DWORD *)(void *)(&__IPSBAR[FEC1_ADDR+off])) |
| 337 | #endif |
Daniel Krueger | 9d7164c | 2008-12-19 11:41:57 -0800 | [diff] [blame] | 338 | #endif |
| 339 | |
Greg Kroah-Hartman | e0ca059 | 2008-12-19 17:09:38 -0800 | [diff] [blame] | 340 | #endif // #ifndef _EDRV_FEC_H_ |