Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Agere Systems Inc. |
| 3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 4 | * |
| 5 | * Copyright © 2005 Agere Systems Inc. |
| 6 | * All rights reserved. |
| 7 | * http://www.agere.com |
| 8 | * |
| 9 | *------------------------------------------------------------------------------ |
| 10 | * |
| 11 | * et1310_eeprom.c - Code used to access the device's EEPROM |
| 12 | * |
| 13 | *------------------------------------------------------------------------------ |
| 14 | * |
| 15 | * SOFTWARE LICENSE |
| 16 | * |
| 17 | * This software is provided subject to the following terms and conditions, |
| 18 | * which you should read carefully before using the software. Using this |
| 19 | * software indicates your acceptance of these terms and conditions. If you do |
| 20 | * not agree with these terms and conditions, do not use the software. |
| 21 | * |
| 22 | * Copyright © 2005 Agere Systems Inc. |
| 23 | * All rights reserved. |
| 24 | * |
| 25 | * Redistribution and use in source or binary forms, with or without |
| 26 | * modifications, are permitted provided that the following conditions are met: |
| 27 | * |
| 28 | * . Redistributions of source code must retain the above copyright notice, this |
| 29 | * list of conditions and the following Disclaimer as comments in the code as |
| 30 | * well as in the documentation and/or other materials provided with the |
| 31 | * distribution. |
| 32 | * |
| 33 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 34 | * this list of conditions and the following Disclaimer in the documentation |
| 35 | * and/or other materials provided with the distribution. |
| 36 | * |
| 37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 38 | * may be used to endorse or promote products derived from this software |
| 39 | * without specific prior written permission. |
| 40 | * |
| 41 | * Disclaimer |
| 42 | * |
| 43 | * THIS SOFTWARE IS PROVIDED AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, |
| 44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 54 | * DAMAGE. |
| 55 | * |
| 56 | */ |
| 57 | |
| 58 | #include "et131x_version.h" |
| 59 | #include "et131x_debug.h" |
| 60 | #include "et131x_defs.h" |
| 61 | |
| 62 | #include <linux/pci.h> |
| 63 | #include <linux/init.h> |
| 64 | #include <linux/module.h> |
| 65 | #include <linux/types.h> |
| 66 | #include <linux/kernel.h> |
| 67 | |
| 68 | #include <linux/sched.h> |
| 69 | #include <linux/ptrace.h> |
| 70 | #include <linux/slab.h> |
| 71 | #include <linux/ctype.h> |
| 72 | #include <linux/string.h> |
| 73 | #include <linux/timer.h> |
| 74 | #include <linux/interrupt.h> |
| 75 | #include <linux/in.h> |
| 76 | #include <linux/delay.h> |
| 77 | #include <asm/io.h> |
| 78 | #include <asm/system.h> |
| 79 | #include <asm/bitops.h> |
| 80 | |
| 81 | #include <linux/netdevice.h> |
| 82 | #include <linux/etherdevice.h> |
| 83 | #include <linux/skbuff.h> |
| 84 | #include <linux/if_arp.h> |
| 85 | #include <linux/ioport.h> |
| 86 | |
| 87 | #include "et1310_phy.h" |
| 88 | #include "et1310_pm.h" |
| 89 | #include "et1310_jagcore.h" |
| 90 | #include "et1310_eeprom.h" |
| 91 | |
| 92 | #include "et131x_adapter.h" |
| 93 | #include "et131x_initpci.h" |
| 94 | #include "et131x_isr.h" |
| 95 | |
| 96 | #include "et1310_tx.h" |
| 97 | |
| 98 | |
| 99 | /* |
| 100 | * EEPROM Defines |
| 101 | */ |
| 102 | |
| 103 | /* LBCIF Register Groups (addressed via 32-bit offsets) */ |
| 104 | #define LBCIF_DWORD0_GROUP_OFFSET 0xAC |
| 105 | #define LBCIF_DWORD1_GROUP_OFFSET 0xB0 |
| 106 | |
| 107 | /* LBCIF Registers (addressed via 8-bit offsets) */ |
| 108 | #define LBCIF_ADDRESS_REGISTER_OFFSET 0xAC |
| 109 | #define LBCIF_DATA_REGISTER_OFFSET 0xB0 |
| 110 | #define LBCIF_CONTROL_REGISTER_OFFSET 0xB1 |
| 111 | #define LBCIF_STATUS_REGISTER_OFFSET 0xB2 |
| 112 | |
| 113 | /* LBCIF Control Register Bits */ |
| 114 | #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 |
| 115 | #define LBCIF_CONTROL_PAGE_WRITE 0x02 |
| 116 | #define LBCIF_CONTROL_UNUSED1 0x04 |
| 117 | #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 |
| 118 | #define LBCIF_CONTROL_UNUSED2 0x10 |
| 119 | #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 |
| 120 | #define LBCIF_CONTROL_I2C_WRITE 0x40 |
| 121 | #define LBCIF_CONTROL_LBCIF_ENABLE 0x80 |
| 122 | |
| 123 | /* LBCIF Status Register Bits */ |
| 124 | #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 |
| 125 | #define LBCIF_STATUS_I2C_IDLE 0x02 |
| 126 | #define LBCIF_STATUS_ACK_ERROR 0x04 |
| 127 | #define LBCIF_STATUS_GENERAL_ERROR 0x08 |
| 128 | #define LBCIF_STATUS_UNUSED 0x30 |
| 129 | #define LBCIF_STATUS_CHECKSUM_ERROR 0x40 |
| 130 | #define LBCIF_STATUS_EEPROM_PRESENT 0x80 |
| 131 | |
| 132 | /* Miscellaneous Constraints */ |
| 133 | #define MAX_NUM_REGISTER_POLLS 1000 |
| 134 | #define MAX_NUM_WRITE_RETRIES 2 |
| 135 | |
| 136 | /* |
| 137 | * Define macros that allow individual register values to be extracted from a |
| 138 | * DWORD1 register grouping |
| 139 | */ |
| 140 | #define EXTRACT_DATA_REGISTER(x) (uint8_t)(x & 0xFF) |
| 141 | #define EXTRACT_STATUS_REGISTER(x) (uint8_t)((x >> 16) & 0xFF) |
| 142 | #define EXTRACT_CONTROL_REG(x) (uint8_t)((x >> 8) & 0xFF) |
| 143 | |
| 144 | /** |
| 145 | * EepromWriteByte - Write a byte to the ET1310's EEPROM |
| 146 | * @pAdapter: pointer to our private adapter structure |
| 147 | * @unAddress: the address to write |
| 148 | * @bData: the value to write |
| 149 | * @unEepronId: the ID of the EEPROM |
| 150 | * @unAddressingMode: how the EEPROM is to be accessed |
| 151 | * |
| 152 | * Returns SUCCESS or FAILURE |
| 153 | */ |
| 154 | int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress, |
| 155 | uint8_t bData, uint32_t unEepromId, |
| 156 | uint32_t unAddressingMode) |
| 157 | { |
| 158 | struct pci_dev *pdev = pAdapter->pdev; |
| 159 | int32_t nIndex; |
| 160 | int32_t nRetries; |
| 161 | int32_t nError = false; |
| 162 | int32_t nI2CWriteActive = 0; |
| 163 | int32_t nWriteSuccessful = 0; |
| 164 | uint8_t bControl; |
| 165 | uint8_t bStatus = 0; |
| 166 | uint32_t unDword1 = 0; |
| 167 | uint32_t unData = 0; |
| 168 | |
| 169 | /* |
| 170 | * The following excerpt is from "Serial EEPROM HW Design |
| 171 | * Specification" Version 0.92 (9/20/2004): |
| 172 | * |
| 173 | * Single Byte Writes |
| 174 | * |
| 175 | * For an EEPROM, an I2C single byte write is defined as a START |
| 176 | * condition followed by the device address, EEPROM address, one byte |
| 177 | * of data and a STOP condition. The STOP condition will trigger the |
| 178 | * EEPROM's internally timed write cycle to the nonvolatile memory. |
| 179 | * All inputs are disabled during this write cycle and the EEPROM will |
| 180 | * not respond to any access until the internal write is complete. |
| 181 | * The steps to execute a single byte write are as follows: |
| 182 | * |
| 183 | * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and |
| 184 | * bits 7,1:0 both equal to 1, at least once after reset. |
| 185 | * Subsequent operations need only to check that bits 1:0 are |
| 186 | * equal to 1 prior to starting a single byte write. |
| 187 | * |
| 188 | * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0, |
| 189 | * and bits 1:0 both =0. Bit 5 should be set according to the |
| 190 | * type of EEPROM being accessed (1=two byte addressing, 0=one |
| 191 | * byte addressing). |
| 192 | * |
| 193 | * 3. Write the address to the LBCIF Address Register. |
| 194 | * |
| 195 | * 4. Write the data to the LBCIF Data Register (the I2C write will |
| 196 | * begin). |
| 197 | * |
| 198 | * 5. Monitor bit 1:0 of the LBCIF Status Register. When bits 1:0 are |
| 199 | * both equal to 1, the I2C write has completed and the internal |
| 200 | * write cycle of the EEPROM is about to start. (bits 1:0 = 01 is |
| 201 | * a legal state while waiting from both equal to 1, but bits |
| 202 | * 1:0 = 10 is invalid and implies that something is broken). |
| 203 | * |
| 204 | * 6. Check bit 3 of the LBCIF Status Register. If equal to 1, an |
| 205 | * error has occurred. |
| 206 | * |
| 207 | * 7. Check bit 2 of the LBCIF Status Register. If equal to 1 an ACK |
| 208 | * error has occurred on the address phase of the write. This |
| 209 | * could be due to an actual hardware failure or the EEPROM may |
| 210 | * still be in its internal write cycle from a previous write. |
| 211 | * This write operation was ignored and must be repeated later. |
| 212 | * |
| 213 | * 8. Set bit 6 of the LBCIF Control Register = 0. If another write is |
| 214 | * required, go to step 1. |
| 215 | */ |
| 216 | |
| 217 | /* Step 1: */ |
| 218 | for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) { |
| 219 | /* Read registers grouped in DWORD1 */ |
| 220 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET, |
| 221 | &unDword1)) { |
| 222 | nError = 1; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | bStatus = EXTRACT_STATUS_REGISTER(unDword1); |
| 227 | |
| 228 | if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL && |
| 229 | bStatus & LBCIF_STATUS_I2C_IDLE) { |
| 230 | /* bits 1:0 are equal to 1 */ |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) { |
| 236 | return FAILURE; |
| 237 | } |
| 238 | |
| 239 | /* Step 2: */ |
| 240 | bControl = 0; |
| 241 | bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE; |
| 242 | |
| 243 | if (unAddressingMode == DUAL_BYTE) { |
| 244 | bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR; |
| 245 | } |
| 246 | |
| 247 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET, |
| 248 | bControl)) { |
| 249 | return FAILURE; |
| 250 | } |
| 251 | |
| 252 | nI2CWriteActive = 1; |
| 253 | |
| 254 | /* Prepare EEPROM address for Step 3 */ |
| 255 | unAddress |= (unAddressingMode == DUAL_BYTE) ? |
| 256 | (unEepromId << 16) : (unEepromId << 8); |
| 257 | |
| 258 | for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) { |
| 259 | /* Step 3:*/ |
| 260 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET, |
| 261 | unAddress)) { |
| 262 | break; |
| 263 | } |
| 264 | |
| 265 | /* Step 4: */ |
| 266 | if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET, |
| 267 | bData)) { |
| 268 | break; |
| 269 | } |
| 270 | |
| 271 | /* Step 5: */ |
| 272 | for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) { |
| 273 | /* Read registers grouped in DWORD1 */ |
| 274 | if (pci_read_config_dword(pdev, |
| 275 | LBCIF_DWORD1_GROUP_OFFSET, |
| 276 | &unDword1)) { |
| 277 | nError = 1; |
| 278 | break; |
| 279 | } |
| 280 | |
| 281 | bStatus = EXTRACT_STATUS_REGISTER(unDword1); |
| 282 | |
| 283 | if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL && |
| 284 | bStatus & LBCIF_STATUS_I2C_IDLE) { |
| 285 | /* I2C write complete */ |
| 286 | break; |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) { |
| 291 | break; |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * Step 6: Don't break here if we are revision 1, this is |
| 296 | * so we do a blind write for load bug. |
| 297 | */ |
| 298 | if (bStatus & LBCIF_STATUS_GENERAL_ERROR |
| 299 | && pAdapter->RevisionID == 0) { |
| 300 | break; |
| 301 | } |
| 302 | |
| 303 | /* Step 7 */ |
| 304 | if (bStatus & LBCIF_STATUS_ACK_ERROR) { |
| 305 | /* |
| 306 | * This could be due to an actual hardware failure |
| 307 | * or the EEPROM may still be in its internal write |
| 308 | * cycle from a previous write. This write operation |
| 309 | * was ignored and must be repeated later. |
| 310 | */ |
| 311 | udelay(10); |
| 312 | continue; |
| 313 | } |
| 314 | |
| 315 | nWriteSuccessful = 1; |
| 316 | break; |
| 317 | } |
| 318 | |
| 319 | /* Step 8: */ |
| 320 | udelay(10); |
| 321 | nIndex = 0; |
| 322 | while (nI2CWriteActive) { |
| 323 | bControl &= ~LBCIF_CONTROL_I2C_WRITE; |
| 324 | |
| 325 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET, |
| 326 | bControl)) { |
| 327 | nWriteSuccessful = 0; |
| 328 | } |
| 329 | |
| 330 | /* Do read until internal ACK_ERROR goes away meaning write |
| 331 | * completed |
| 332 | */ |
| 333 | do { |
| 334 | pci_write_config_dword(pdev, |
| 335 | LBCIF_ADDRESS_REGISTER_OFFSET, |
| 336 | unAddress); |
| 337 | do { |
| 338 | pci_read_config_dword(pdev, |
| 339 | LBCIF_DATA_REGISTER_OFFSET, &unData); |
| 340 | } while ((unData & 0x00010000) == 0); |
| 341 | } while (unData & 0x00040000); |
| 342 | |
| 343 | bControl = EXTRACT_CONTROL_REG(unData); |
| 344 | |
| 345 | if (bControl != 0xC0 || nIndex == 10000) { |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | nIndex++; |
| 350 | } |
| 351 | |
| 352 | return nWriteSuccessful ? SUCCESS : FAILURE; |
| 353 | } |
| 354 | |
| 355 | /** |
| 356 | * EepromReadByte - Read a byte from the ET1310's EEPROM |
| 357 | * @pAdapter: pointer to our private adapter structure |
| 358 | * @unAddress: the address from which to read |
| 359 | * @pbData: a pointer to a byte in which to store the value of the read |
| 360 | * @unEepronId: the ID of the EEPROM |
| 361 | * @unAddressingMode: how the EEPROM is to be accessed |
| 362 | * |
| 363 | * Returns SUCCESS or FAILURE |
| 364 | */ |
| 365 | int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress, |
| 366 | uint8_t *pbData, uint32_t unEepromId, |
| 367 | uint32_t unAddressingMode) |
| 368 | { |
| 369 | struct pci_dev *pdev = pAdapter->pdev; |
| 370 | int32_t nIndex; |
| 371 | int32_t nError = 0; |
| 372 | uint8_t bControl; |
| 373 | uint8_t bStatus = 0; |
| 374 | uint32_t unDword1 = 0; |
| 375 | |
| 376 | /* |
| 377 | * The following excerpt is from "Serial EEPROM HW Design |
| 378 | * Specification" Version 0.92 (9/20/2004): |
| 379 | * |
| 380 | * Single Byte Reads |
| 381 | * |
| 382 | * A single byte read is similar to the single byte write, with the |
| 383 | * exception of the data flow: |
| 384 | * |
| 385 | * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and |
| 386 | * bits 7,1:0 both equal to 1, at least once after reset. |
| 387 | * Subsequent operations need only to check that bits 1:0 are equal |
| 388 | * to 1 prior to starting a single byte read. |
| 389 | * |
| 390 | * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0, |
| 391 | * and bits 1:0 both =0. Bit 5 should be set according to the type |
| 392 | * of EEPROM being accessed (1=two byte addressing, 0=one byte |
| 393 | * addressing). |
| 394 | * |
| 395 | * 3. Write the address to the LBCIF Address Register (I2C read will |
| 396 | * begin). |
| 397 | * |
| 398 | * 4. Monitor bit 0 of the LBCIF Status Register. When =1, I2C read |
| 399 | * is complete. (if bit 1 =1 and bit 0 stays =0, a hardware failure |
| 400 | * has occurred). |
| 401 | * |
| 402 | * 5. Check bit 2 of the LBCIF Status Register. If =1, then an error |
| 403 | * has occurred. The data that has been returned from the PHY may |
| 404 | * be invalid. |
| 405 | * |
| 406 | * 6. Regardless of error status, read data byte from LBCIF Data |
| 407 | * Register. If another byte is required, go to step 1. |
| 408 | */ |
| 409 | |
| 410 | /* Step 1: */ |
| 411 | for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) { |
| 412 | /* Read registers grouped in DWORD1 */ |
| 413 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET, |
| 414 | &unDword1)) { |
| 415 | nError = 1; |
| 416 | break; |
| 417 | } |
| 418 | |
| 419 | bStatus = EXTRACT_STATUS_REGISTER(unDword1); |
| 420 | |
| 421 | if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL && |
| 422 | bStatus & LBCIF_STATUS_I2C_IDLE) { |
| 423 | /* bits 1:0 are equal to 1 */ |
| 424 | break; |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) { |
| 429 | return FAILURE; |
| 430 | } |
| 431 | |
| 432 | /* Step 2: */ |
| 433 | bControl = 0; |
| 434 | bControl |= LBCIF_CONTROL_LBCIF_ENABLE; |
| 435 | |
| 436 | if (unAddressingMode == DUAL_BYTE) { |
| 437 | bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR; |
| 438 | } |
| 439 | |
| 440 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET, |
| 441 | bControl)) { |
| 442 | return FAILURE; |
| 443 | } |
| 444 | |
| 445 | /* Step 3: */ |
| 446 | unAddress |= (unAddressingMode == DUAL_BYTE) ? |
| 447 | (unEepromId << 16) : (unEepromId << 8); |
| 448 | |
| 449 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET, |
| 450 | unAddress)) { |
| 451 | return FAILURE; |
| 452 | } |
| 453 | |
| 454 | /* Step 4: */ |
| 455 | for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) { |
| 456 | /* Read registers grouped in DWORD1 */ |
| 457 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET, |
| 458 | &unDword1)) { |
| 459 | nError = 1; |
| 460 | break; |
| 461 | } |
| 462 | |
| 463 | bStatus = EXTRACT_STATUS_REGISTER(unDword1); |
| 464 | |
| 465 | if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL |
| 466 | && bStatus & LBCIF_STATUS_I2C_IDLE) { |
| 467 | /* I2C read complete */ |
| 468 | break; |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) { |
| 473 | return FAILURE; |
| 474 | } |
| 475 | |
| 476 | /* Step 6: */ |
| 477 | *pbData = EXTRACT_DATA_REGISTER(unDword1); |
| 478 | |
| 479 | return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS; |
| 480 | } |