David Kiliani | 3fedd14 | 2008-11-01 00:39:12 +0100 | [diff] [blame] | 1 | /** |
| 2 | * @file me4600_ao_reg.h |
| 3 | * |
| 4 | * @brief ME-4000 analog output subdevice register definitions. |
| 5 | * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de) |
| 6 | * @author Guenter Gebhardt |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de) |
| 11 | * |
| 12 | * This file is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | */ |
| 26 | |
| 27 | #ifndef _ME4600_AO_REG_H_ |
| 28 | #define _ME4600_AO_REG_H_ |
| 29 | |
| 30 | #ifdef __KERNEL__ |
| 31 | |
| 32 | #define ME4600_AO_00_CTRL_REG 0x00 // R/W |
| 33 | #define ME4600_AO_00_STATUS_REG 0x04 // R/_ |
| 34 | #define ME4600_AO_00_FIFO_REG 0x08 // _/W |
| 35 | #define ME4600_AO_00_SINGLE_REG 0x0C // R/W |
| 36 | #define ME4600_AO_00_TIMER_REG 0x10 // _/W |
| 37 | |
| 38 | #define ME4600_AO_01_CTRL_REG 0x18 // R/W |
| 39 | #define ME4600_AO_01_STATUS_REG 0x1C // R/_ |
| 40 | #define ME4600_AO_01_FIFO_REG 0x20 // _/W |
| 41 | #define ME4600_AO_01_SINGLE_REG 0x24 // R/W |
| 42 | #define ME4600_AO_01_TIMER_REG 0x28 // _/W |
| 43 | |
| 44 | #define ME4600_AO_02_CTRL_REG 0x30 // R/W |
| 45 | #define ME4600_AO_02_STATUS_REG 0x34 // R/_ |
| 46 | #define ME4600_AO_02_FIFO_REG 0x38 // _/W |
| 47 | #define ME4600_AO_02_SINGLE_REG 0x3C // R/W |
| 48 | #define ME4600_AO_02_TIMER_REG 0x40 // _/W |
| 49 | |
| 50 | #define ME4600_AO_03_CTRL_REG 0x48 // R/W |
| 51 | #define ME4600_AO_03_STATUS_REG 0x4C // R/_ |
| 52 | #define ME4600_AO_03_FIFO_REG 0x50 // _/W |
| 53 | #define ME4600_AO_03_SINGLE_REG 0x54 // R/W |
| 54 | #define ME4600_AO_03_TIMER_REG 0x58 // _/W |
| 55 | |
| 56 | #define ME4600_AO_DEMUX_ADJUST_REG 0xBC // -/W |
| 57 | #define ME4600_AO_DEMUX_ADJUST_VALUE 0x4C |
| 58 | |
| 59 | #ifdef BOSCH |
| 60 | # define ME4600_AO_BOSCH_REG 0xC4 |
| 61 | |
| 62 | # define ME4600_AO_LOADSETREG_XX 0xB4 // R/W |
| 63 | |
| 64 | # define ME4600_AO_CTRL_BIT_MODE_0 0x001 |
| 65 | # define ME4600_AO_CTRL_BIT_MODE_1 0x002 |
| 66 | # define ME4600_AO_CTRL_MASK_MODE 0x003 |
| 67 | |
| 68 | #else //~BOSCH |
| 69 | |
| 70 | #define ME4600_AO_SYNC_REG 0xB4 // R/W ///ME4600_AO_SYNC_REG <==> ME4600_AO_PRELOAD_REG <==> ME4600_AO_LOADSETREG_XX |
| 71 | |
| 72 | # define ME4600_AO_MODE_SINGLE 0x00000000 |
| 73 | # define ME4600_AO_MODE_WRAPAROUND 0x00000001 |
| 74 | # define ME4600_AO_MODE_CONTINUOUS 0x00000002 |
| 75 | # define ME4600_AO_CTRL_MODE_MASK (ME4600_AO_MODE_WRAPAROUND | ME4600_AO_MODE_CONTINUOUS) |
| 76 | #endif //BOSCH |
| 77 | |
| 78 | #define ME4600_AO_CTRL_BIT_MODE_WRAPAROUND ME4600_AO_MODE_WRAPAROUND |
| 79 | #define ME4600_AO_CTRL_BIT_MODE_CONTINOUS ME4600_AO_MODE_CONTINUOUS |
| 80 | #define ME4600_AO_CTRL_BIT_STOP 0x00000004 |
| 81 | #define ME4600_AO_CTRL_BIT_ENABLE_FIFO 0x00000008 |
| 82 | #define ME4600_AO_CTRL_BIT_ENABLE_EX_TRIG 0x00000010 |
| 83 | #define ME4600_AO_CTRL_BIT_EX_TRIG_EDGE 0x00000020 |
| 84 | #define ME4600_AO_CTRL_BIT_IMMEDIATE_STOP 0x00000080 |
| 85 | #define ME4600_AO_CTRL_BIT_ENABLE_DO 0x00000100 |
| 86 | #define ME4600_AO_CTRL_BIT_ENABLE_IRQ 0x00000200 |
| 87 | #define ME4600_AO_CTRL_BIT_RESET_IRQ 0x00000400 |
| 88 | #define ME4600_AO_CTRL_BIT_EX_TRIG_EDGE_BOTH 0x00000800 |
| 89 | /* |
| 90 | #define ME4600_AO_SYNC_HOLD_0 0x00000001 |
| 91 | #define ME4600_AO_SYNC_HOLD_1 0x00000002 |
| 92 | #define ME4600_AO_SYNC_HOLD_2 0x00000004 |
| 93 | #define ME4600_AO_SYNC_HOLD_3 0x00000008 |
| 94 | */ |
| 95 | #define ME4600_AO_SYNC_HOLD 0x00000001 |
| 96 | |
| 97 | /* |
| 98 | #define ME4600_AO_SYNC_EXT_TRIG_0 0x00010000 |
| 99 | #define ME4600_AO_SYNC_EXT_TRIG_1 0x00020000 |
| 100 | #define ME4600_AO_SYNC_EXT_TRIG_2 0x00040000 |
| 101 | #define ME4600_AO_SYNC_EXT_TRIG_3 0x00080000 |
| 102 | */ |
| 103 | #define ME4600_AO_SYNC_EXT_TRIG 0x00010000 |
| 104 | |
| 105 | #define ME4600_AO_EXT_TRIG 0x80000000 |
| 106 | |
| 107 | #define ME4600_AO_STATUS_BIT_FSM 0x00000001 |
| 108 | #define ME4600_AO_STATUS_BIT_FF 0x00000002 |
| 109 | #define ME4600_AO_STATUS_BIT_HF 0x00000004 |
| 110 | #define ME4600_AO_STATUS_BIT_EF 0x00000008 |
| 111 | |
| 112 | #endif |
| 113 | #endif |