David Kiliani | 3fedd14 | 2008-11-01 00:39:12 +0100 | [diff] [blame] | 1 | /** |
| 2 | * @file me8254_reg.h |
| 3 | * |
| 4 | * @brief 8254 counter register definitions. |
| 5 | * @note Copyright (C) 2006 Meilhaus Electronic GmbH (support@meilhaus.de) |
| 6 | * @author Guenter Gebhardt |
| 7 | */ |
| 8 | |
| 9 | #ifndef _ME8254_REG_H_ |
| 10 | #define _ME8254_REG_H_ |
| 11 | |
| 12 | #ifdef __KERNEL__ |
| 13 | |
| 14 | /* ME1400 A/B register offsets */ |
| 15 | #define ME1400AB_8254_A_0_VAL_REG 0x0004 /**< Offset of 8254 A counter 0 value register. */ |
| 16 | #define ME1400AB_8254_A_1_VAL_REG 0x0005 /**< Offset of 8254 A counter 1 value register. */ |
| 17 | #define ME1400AB_8254_A_2_VAL_REG 0x0006 /**< Offset of 8254 A counter 2 value register. */ |
| 18 | #define ME1400AB_8254_A_CTRL_REG 0x0007 /**< Offset of 8254 A control register. */ |
| 19 | |
| 20 | #define ME1400AB_8254_B_0_VAL_REG 0x000C /**< Offset of 8254 B counter 0 value register. */ |
| 21 | #define ME1400AB_8254_B_1_VAL_REG 0x000D /**< Offset of 8254 B counter 1 value register. */ |
| 22 | #define ME1400AB_8254_B_2_VAL_REG 0x000E /**< Offset of 8254 B counter 2 value register. */ |
| 23 | #define ME1400AB_8254_B_CTRL_REG 0x000F /**< Offset of 8254 B control register. */ |
| 24 | |
| 25 | #define ME1400AB_CLK_SRC_REG 0x0010 /**< Offset of clock source register. */ |
| 26 | |
| 27 | /* ME1400 C register offsets */ |
| 28 | #define ME1400C_8254_A_0_VAL_REG 0x0004 /**< Offset of 8254 A counter 0 value register. */ |
| 29 | #define ME1400C_8254_A_1_VAL_REG 0x0005 /**< Offset of 8254 A counter 0 value register. */ |
| 30 | #define ME1400C_8254_A_2_VAL_REG 0x0006 /**< Offset of 8254 A counter 0 value register. */ |
| 31 | #define ME1400C_8254_A_CTRL_REG 0x0007 /**< Offset of 8254 A control register. */ |
| 32 | |
| 33 | #define ME1400C_8254_B_0_VAL_REG 0x000C /**< Offset of 8254 B counter 0 value register. */ |
| 34 | #define ME1400C_8254_B_1_VAL_REG 0x000D /**< Offset of 8254 B counter 0 value register. */ |
| 35 | #define ME1400C_8254_B_2_VAL_REG 0x000E /**< Offset of 8254 B counter 0 value register. */ |
| 36 | #define ME1400C_8254_B_CTRL_REG 0x000F /**< Offset of 8254 B control register. */ |
| 37 | |
| 38 | #define ME1400C_8254_C_0_VAL_REG 0x0010 /**< Offset of 8254 C counter 0 value register. */ |
| 39 | #define ME1400C_8254_C_1_VAL_REG 0x0011 /**< Offset of 8254 C counter 0 value register. */ |
| 40 | #define ME1400C_8254_C_2_VAL_REG 0x0012 /**< Offset of 8254 C counter 0 value register. */ |
| 41 | #define ME1400C_8254_C_CTRL_REG 0x0013 /**< Offset of 8254 C control register. */ |
| 42 | |
| 43 | #define ME1400C_8254_D_0_VAL_REG 0x0014 /**< Offset of 8254 D counter 0 value register. */ |
| 44 | #define ME1400C_8254_D_1_VAL_REG 0x0015 /**< Offset of 8254 D counter 0 value register. */ |
| 45 | #define ME1400C_8254_D_2_VAL_REG 0x0016 /**< Offset of 8254 D counter 0 value register. */ |
| 46 | #define ME1400C_8254_D_CTRL_REG 0x0017 /**< Offset of 8254 D control register. */ |
| 47 | |
| 48 | #define ME1400C_8254_E_0_VAL_REG 0x0018 /**< Offset of 8254 E counter 0 value register. */ |
| 49 | #define ME1400C_8254_E_1_VAL_REG 0x0019 /**< Offset of 8254 E counter 0 value register. */ |
| 50 | #define ME1400C_8254_E_2_VAL_REG 0x001A /**< Offset of 8254 E counter 0 value register. */ |
| 51 | #define ME1400C_8254_E_CTRL_REG 0x001B /**< Offset of 8254 E control register. */ |
| 52 | |
| 53 | #define ME1400C_CLK_SRC_0_REG 0x001C /**< Offset of clock source register 0. */ |
| 54 | #define ME1400C_CLK_SRC_1_REG 0x001D /**< Offset of clock source register 1. */ |
| 55 | #define ME1400C_CLK_SRC_2_REG 0x001E /**< Offset of clock source register 2. */ |
| 56 | |
| 57 | /* ME1400 D register offsets */ |
| 58 | #define ME1400D_8254_A_0_VAL_REG 0x0044 /**< Offset of 8254 A counter 0 value register. */ |
| 59 | #define ME1400D_8254_A_1_VAL_REG 0x0045 /**< Offset of 8254 A counter 0 value register. */ |
| 60 | #define ME1400D_8254_A_2_VAL_REG 0x0046 /**< Offset of 8254 A counter 0 value register. */ |
| 61 | #define ME1400D_8254_A_CTRL_REG 0x0047 /**< Offset of 8254 A control register. */ |
| 62 | |
| 63 | #define ME1400D_8254_B_0_VAL_REG 0x004C /**< Offset of 8254 B counter 0 value register. */ |
| 64 | #define ME1400D_8254_B_1_VAL_REG 0x004D /**< Offset of 8254 B counter 0 value register. */ |
| 65 | #define ME1400D_8254_B_2_VAL_REG 0x004E /**< Offset of 8254 B counter 0 value register. */ |
| 66 | #define ME1400D_8254_B_CTRL_REG 0x004F /**< Offset of 8254 B control register. */ |
| 67 | |
| 68 | #define ME1400D_8254_C_0_VAL_REG 0x0050 /**< Offset of 8254 C counter 0 value register. */ |
| 69 | #define ME1400D_8254_C_1_VAL_REG 0x0051 /**< Offset of 8254 C counter 0 value register. */ |
| 70 | #define ME1400D_8254_C_2_VAL_REG 0x0052 /**< Offset of 8254 C counter 0 value register. */ |
| 71 | #define ME1400D_8254_C_CTRL_REG 0x0053 /**< Offset of 8254 C control register. */ |
| 72 | |
| 73 | #define ME1400D_8254_D_0_VAL_REG 0x0054 /**< Offset of 8254 D counter 0 value register. */ |
| 74 | #define ME1400D_8254_D_1_VAL_REG 0x0055 /**< Offset of 8254 D counter 0 value register. */ |
| 75 | #define ME1400D_8254_D_2_VAL_REG 0x0056 /**< Offset of 8254 D counter 0 value register. */ |
| 76 | #define ME1400D_8254_D_CTRL_REG 0x0057 /**< Offset of 8254 D control register. */ |
| 77 | |
| 78 | #define ME1400D_8254_E_0_VAL_REG 0x0058 /**< Offset of 8254 E counter 0 value register. */ |
| 79 | #define ME1400D_8254_E_1_VAL_REG 0x0059 /**< Offset of 8254 E counter 0 value register. */ |
| 80 | #define ME1400D_8254_E_2_VAL_REG 0x005A /**< Offset of 8254 E counter 0 value register. */ |
| 81 | #define ME1400D_8254_E_CTRL_REG 0x005B /**< Offset of 8254 E control register. */ |
| 82 | |
| 83 | #define ME1400D_CLK_SRC_0_REG 0x005C /**< Offset of clock source register 0. */ |
| 84 | #define ME1400D_CLK_SRC_1_REG 0x005D /**< Offset of clock source register 1. */ |
| 85 | #define ME1400D_CLK_SRC_2_REG 0x005E /**< Offset of clock source register 2. */ |
| 86 | |
| 87 | /* ME4600 register offsets */ |
| 88 | #define ME4600_8254_0_VAL_REG 0x0000 /**< Offset of 8254 A counter 0 value register. */ |
| 89 | #define ME4600_8254_1_VAL_REG 0x0001 /**< Offset of 8254 A counter 0 value register. */ |
| 90 | #define ME4600_8254_2_VAL_REG 0x0002 /**< Offset of 8254 A counter 0 value register. */ |
| 91 | #define ME4600_8254_CTRL_REG 0x0003 /**< Offset of 8254 A control register. */ |
| 92 | |
| 93 | /* Command words for 8254 control register */ |
| 94 | #define ME8254_CTRL_SC0 0x00 /**< Counter 0 selection. */ |
| 95 | #define ME8254_CTRL_SC1 0x40 /**< Counter 1 selection. */ |
| 96 | #define ME8254_CTRL_SC2 0x80 /**< Counter 2 selection. */ |
| 97 | |
| 98 | #define ME8254_CTRL_TLO 0x00 /**< Counter latching operation. */ |
| 99 | #define ME8254_CTRL_LSB 0x10 /**< Only read LSB. */ |
| 100 | #define ME8254_CTRL_MSB 0x20 /**< Only read MSB. */ |
| 101 | #define ME8254_CTRL_LM 0x30 /**< First read LSB, then MSB. */ |
| 102 | |
| 103 | #define ME8254_CTRL_M0 0x00 /**< Mode 0 selection. */ |
| 104 | #define ME8254_CTRL_M1 0x02 /**< Mode 1 selection. */ |
| 105 | #define ME8254_CTRL_M2 0x04 /**< Mode 2 selection. */ |
| 106 | #define ME8254_CTRL_M3 0x06 /**< Mode 3 selection. */ |
| 107 | #define ME8254_CTRL_M4 0x08 /**< Mode 4 selection. */ |
| 108 | #define ME8254_CTRL_M5 0x0A /**< Mode 5 selection. */ |
| 109 | |
| 110 | #define ME8254_CTRL_BIN 0x00 /**< Binary counter. */ |
| 111 | #define ME8254_CTRL_BCD 0x01 /**< BCD counter. */ |
| 112 | |
| 113 | /* ME-1400 A/B clock source register bits */ |
| 114 | #define ME1400AB_8254_A_0_CLK_SRC_1MHZ (0 << 7) /**< 1MHz clock. */ |
| 115 | #define ME1400AB_8254_A_0_CLK_SRC_10MHZ (1 << 7) /**< 10MHz clock. */ |
| 116 | #define ME1400AB_8254_A_0_CLK_SRC_PIN (0 << 6) /**< CLK 0 to SUB-D. */ |
| 117 | #define ME1400AB_8254_A_0_CLK_SRC_QUARZ (1 << 6) /**< Connect CLK 0 with quarz. */ |
| 118 | |
| 119 | #define ME1400AB_8254_A_1_CLK_SRC_PIN (0 << 5) /**< CLK 1 to SUB-D. */ |
| 120 | #define ME1400AB_8254_A_1_CLK_SRC_PREV (1 << 5) /**< Connect OUT 0 with CLK 1. */ |
| 121 | |
| 122 | #define ME1400AB_8254_A_2_CLK_SRC_PIN (0 << 4) /**< CLK 2 to SUB-D. */ |
| 123 | #define ME1400AB_8254_A_2_CLK_SRC_PREV (1 << 4) /**< Connect OUT 1 with CLK 2. */ |
| 124 | |
| 125 | #define ME1400AB_8254_B_0_CLK_SRC_1MHZ (0 << 3) /**< 1MHz clock. */ |
| 126 | #define ME1400AB_8254_B_0_CLK_SRC_10MHZ (1 << 3) /**< 10MHz clock. */ |
| 127 | #define ME1400AB_8254_B_0_CLK_SRC_PIN (0 << 2) /**< CLK 0 to SUB-D. */ |
| 128 | #define ME1400AB_8254_B_0_CLK_SRC_QUARZ (1 << 2) /**< Connect CLK 0 with quarz. */ |
| 129 | |
| 130 | #define ME1400AB_8254_B_1_CLK_SRC_PIN (0 << 1) /**< CLK 1 to SUB-D. */ |
| 131 | #define ME1400AB_8254_B_1_CLK_SRC_PREV (1 << 1) /**< Connect OUT 0 with CLK 1. */ |
| 132 | |
| 133 | #define ME1400AB_8254_B_2_CLK_SRC_PIN (0 << 0) /**< CLK 2 to SUB-D. */ |
| 134 | #define ME1400AB_8254_B_2_CLK_SRC_PREV (1 << 0) /**< Connect OUT 1 with CLK 2. */ |
| 135 | |
| 136 | /* ME-1400 C/D clock source registers bits */ |
| 137 | #define ME1400CD_8254_ACE_0_CLK_SRC_MASK 0x03 /**< Masks all CLK source bits. */ |
| 138 | #define ME1400CD_8254_ACE_0_CLK_SRC_PIN 0x00 /**< Connect CLK to SUB-D. */ |
| 139 | #define ME1400CD_8254_ACE_0_CLK_SRC_1MHZ 0x01 /**< Connect CLK to 1MHz. */ |
| 140 | #define ME1400CD_8254_ACE_0_CLK_SRC_10MHZ 0x02 /**< Connect CLK to 10MHz. */ |
| 141 | #define ME1400CD_8254_ACE_0_CLK_SRC_PREV 0x03 /**< Connect CLK to previous counter output on ME-1400 D extension. */ |
| 142 | |
| 143 | #define ME1400CD_8254_ACE_1_CLK_SRC_MASK 0x04 /**< Masks all CLK source bits. */ |
| 144 | #define ME1400CD_8254_ACE_1_CLK_SRC_PIN 0x00 /**< Connect CLK to SUB-D. */ |
| 145 | #define ME1400CD_8254_ACE_1_CLK_SRC_PREV 0x04 /**< Connect CLK to previous counter output. */ |
| 146 | |
| 147 | #define ME1400CD_8254_ACE_2_CLK_SRC_MASK 0x08 /**< Masks all CLK source bits. */ |
| 148 | #define ME1400CD_8254_ACE_2_CLK_SRC_PIN 0x00 /**< Connect to SUB-D. */ |
| 149 | #define ME1400CD_8254_ACE_2_CLK_SRC_PREV 0x08 /**< Connect CLK to previous counter output. */ |
| 150 | |
| 151 | #define ME1400CD_8254_BD_0_CLK_SRC_MASK 0x30 /**< Masks all CLK source bits. */ |
| 152 | #define ME1400CD_8254_BD_0_CLK_SRC_PIN 0x00 /**< Connect CLK to SUB-D. */ |
| 153 | #define ME1400CD_8254_BD_0_CLK_SRC_1MHZ 0x10 /**< Connect CLK to 1MHz. */ |
| 154 | #define ME1400CD_8254_BD_0_CLK_SRC_10MHZ 0x20 /**< Connect CLK to 10MHz. */ |
| 155 | #define ME1400CD_8254_BD_0_CLK_SRC_PREV 0x30 /**< Connect CLK to previous counter output. */ |
| 156 | |
| 157 | #define ME1400CD_8254_BD_1_CLK_SRC_MASK 0x40 /**< Masks all CLK source bits. */ |
| 158 | #define ME1400CD_8254_BD_1_CLK_SRC_PIN 0x00 /**< Connect CLK to SUB-D. */ |
| 159 | #define ME1400CD_8254_BD_1_CLK_SRC_PREV 0x40 /**< Connect CLK to previous counter output. */ |
| 160 | |
| 161 | #define ME1400CD_8254_BD_2_CLK_SRC_MASK 0x80 /**< Masks all CLK source bits. */ |
| 162 | #define ME1400CD_8254_BD_2_CLK_SRC_PIN 0x00 /**< Connect CLK to SUB-D. */ |
| 163 | #define ME1400CD_8254_BD_2_CLK_SRC_PREV 0x80 /**< Connect CLK to previous counter output. */ |
| 164 | |
| 165 | /* ME-8100 counter registers */ |
| 166 | #define ME8100_COUNTER_REG_0 0x18 //(r,w) |
| 167 | #define ME8100_COUNTER_REG_1 0x1A //(r,w) |
| 168 | #define ME8100_COUNTER_REG_2 0x1C //(r,w) |
| 169 | #define ME8100_COUNTER_CTRL_REG 0x1E //(r,w) |
| 170 | |
| 171 | #endif |
| 172 | #endif |