Andre Silva | bd89782 | 2011-06-10 13:08:14 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | */ |
| 4 | |
| 5 | /* |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/gpio.h> |
| 25 | #include <linux/smsc911x.h> |
| 26 | |
| 27 | #include <mach/common.h> |
| 28 | #include <mach/hardware.h> |
| 29 | #include <mach/iomux-mx53.h> |
| 30 | |
| 31 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/time.h> |
| 34 | |
| 35 | #include "crm_regs.h" |
| 36 | #include "devices-imx53.h" |
| 37 | |
| 38 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) |
Andre Silva | e3a58be | 2011-06-13 14:31:57 -0300 | [diff] [blame^] | 39 | #define ARD_SD1_CD IMX_GPIO_NR(1, 1) |
| 40 | #define ARD_SD1_WP IMX_GPIO_NR(1, 9) |
Andre Silva | bd89782 | 2011-06-10 13:08:14 -0300 | [diff] [blame] | 41 | |
| 42 | static iomux_v3_cfg_t mx53_ard_pads[] = { |
| 43 | /* UART1 */ |
| 44 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX, |
| 45 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX, |
| 46 | /* WEIM for CS1 */ |
| 47 | MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ |
| 48 | MX53_PAD_EIM_D16__EMI_WEIM_D_16, |
| 49 | MX53_PAD_EIM_D17__EMI_WEIM_D_17, |
| 50 | MX53_PAD_EIM_D18__EMI_WEIM_D_18, |
| 51 | MX53_PAD_EIM_D19__EMI_WEIM_D_19, |
| 52 | MX53_PAD_EIM_D20__EMI_WEIM_D_20, |
| 53 | MX53_PAD_EIM_D21__EMI_WEIM_D_21, |
| 54 | MX53_PAD_EIM_D22__EMI_WEIM_D_22, |
| 55 | MX53_PAD_EIM_D23__EMI_WEIM_D_23, |
| 56 | MX53_PAD_EIM_D24__EMI_WEIM_D_24, |
| 57 | MX53_PAD_EIM_D25__EMI_WEIM_D_25, |
| 58 | MX53_PAD_EIM_D26__EMI_WEIM_D_26, |
| 59 | MX53_PAD_EIM_D27__EMI_WEIM_D_27, |
| 60 | MX53_PAD_EIM_D28__EMI_WEIM_D_28, |
| 61 | MX53_PAD_EIM_D29__EMI_WEIM_D_29, |
| 62 | MX53_PAD_EIM_D30__EMI_WEIM_D_30, |
| 63 | MX53_PAD_EIM_D31__EMI_WEIM_D_31, |
| 64 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, |
| 65 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, |
| 66 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, |
| 67 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, |
| 68 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, |
| 69 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, |
| 70 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, |
| 71 | MX53_PAD_EIM_OE__EMI_WEIM_OE, |
| 72 | MX53_PAD_EIM_RW__EMI_WEIM_RW, |
| 73 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, |
Andre Silva | e3a58be | 2011-06-13 14:31:57 -0300 | [diff] [blame^] | 74 | /* SDHC1 */ |
| 75 | MX53_PAD_SD1_CMD__ESDHC1_CMD, |
| 76 | MX53_PAD_SD1_CLK__ESDHC1_CLK, |
| 77 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, |
| 78 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, |
| 79 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, |
| 80 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, |
| 81 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4, |
| 82 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5, |
| 83 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6, |
| 84 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7, |
| 85 | MX53_PAD_GPIO_1__GPIO1_1, |
| 86 | MX53_PAD_GPIO_9__GPIO1_9, |
Andre Silva | bd89782 | 2011-06-10 13:08:14 -0300 | [diff] [blame] | 87 | }; |
| 88 | |
| 89 | static struct resource ard_smsc911x_resources[] = { |
| 90 | { |
| 91 | .start = MX53_CS1_64MB_BASE_ADDR, |
| 92 | .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, |
| 93 | .flags = IORESOURCE_MEM, |
| 94 | }, |
| 95 | { |
| 96 | .start = gpio_to_irq(ARD_ETHERNET_INT_B), |
| 97 | .end = gpio_to_irq(ARD_ETHERNET_INT_B), |
| 98 | .flags = IORESOURCE_IRQ, |
| 99 | }, |
| 100 | }; |
| 101 | |
| 102 | struct smsc911x_platform_config ard_smsc911x_config = { |
| 103 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, |
| 104 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, |
| 105 | .flags = SMSC911X_USE_32BIT, |
| 106 | }; |
| 107 | |
| 108 | static struct platform_device ard_smsc_lan9220_device = { |
| 109 | .name = "smsc911x", |
| 110 | .id = -1, |
| 111 | .num_resources = ARRAY_SIZE(ard_smsc911x_resources), |
| 112 | .resource = ard_smsc911x_resources, |
| 113 | .dev = { |
| 114 | .platform_data = &ard_smsc911x_config, |
| 115 | }, |
| 116 | }; |
| 117 | |
Andre Silva | e3a58be | 2011-06-13 14:31:57 -0300 | [diff] [blame^] | 118 | static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { |
| 119 | .cd_gpio = ARD_SD1_CD, |
| 120 | .wp_gpio = ARD_SD1_WP, |
| 121 | }; |
| 122 | |
Andre Silva | bd89782 | 2011-06-10 13:08:14 -0300 | [diff] [blame] | 123 | static void __init mx53_ard_io_init(void) |
| 124 | { |
| 125 | mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, |
| 126 | ARRAY_SIZE(mx53_ard_pads)); |
| 127 | |
| 128 | gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); |
| 129 | gpio_direction_input(ARD_ETHERNET_INT_B); |
| 130 | } |
| 131 | |
| 132 | /* Config CS1 settings for ethernet controller */ |
| 133 | static int weim_cs_config(void) |
| 134 | { |
| 135 | u32 reg; |
| 136 | void __iomem *weim_base, *iomuxc_base; |
| 137 | |
| 138 | weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); |
| 139 | if (!weim_base) |
| 140 | return -ENOMEM; |
| 141 | |
| 142 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); |
| 143 | if (!iomuxc_base) |
| 144 | return -ENOMEM; |
| 145 | |
| 146 | /* CS1 timings for LAN9220 */ |
| 147 | writel(0x20001, (weim_base + 0x18)); |
| 148 | writel(0x0, (weim_base + 0x1C)); |
| 149 | writel(0x16000202, (weim_base + 0x20)); |
| 150 | writel(0x00000002, (weim_base + 0x24)); |
| 151 | writel(0x16002082, (weim_base + 0x28)); |
| 152 | writel(0x00000000, (weim_base + 0x2C)); |
| 153 | writel(0x00000000, (weim_base + 0x90)); |
| 154 | |
| 155 | /* specify 64 MB on CS1 and CS0 on GPR1 */ |
| 156 | reg = readl(iomuxc_base + 0x4); |
| 157 | reg &= ~0x3F; |
| 158 | reg |= 0x1B; |
| 159 | writel(reg, (iomuxc_base + 0x4)); |
| 160 | |
| 161 | iounmap(iomuxc_base); |
| 162 | iounmap(weim_base); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static struct platform_device *devices[] __initdata = { |
| 168 | &ard_smsc_lan9220_device, |
| 169 | }; |
| 170 | |
| 171 | static void __init mx53_ard_board_init(void) |
| 172 | { |
| 173 | imx53_soc_init(); |
| 174 | imx53_add_imx_uart(0, NULL); |
| 175 | |
| 176 | mx53_ard_io_init(); |
| 177 | weim_cs_config(); |
| 178 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
Andre Silva | e3a58be | 2011-06-13 14:31:57 -0300 | [diff] [blame^] | 179 | |
| 180 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); |
Andre Silva | bd89782 | 2011-06-10 13:08:14 -0300 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void __init mx53_ard_timer_init(void) |
| 184 | { |
| 185 | mx53_clocks_init(32768, 24000000, 22579200, 0); |
| 186 | } |
| 187 | |
| 188 | static struct sys_timer mx53_ard_timer = { |
| 189 | .init = mx53_ard_timer_init, |
| 190 | }; |
| 191 | |
| 192 | MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") |
| 193 | .map_io = mx53_map_io, |
| 194 | .init_early = imx53_init_early, |
| 195 | .init_irq = mx53_init_irq, |
| 196 | .timer = &mx53_ard_timer, |
| 197 | .init_machine = mx53_ard_board_init, |
| 198 | MACHINE_END |