Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * BRIEF MODULE DESCRIPTION |
| 4 | * Include file for Alchemy Semiconductor's Au1550 Descriptor |
| 5 | * Based DMA Controller. |
| 6 | * |
| 7 | * Copyright 2004 Embedded Edge, LLC |
| 8 | * dan@embeddededge.com |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License along |
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 29 | */ |
| 30 | |
| 31 | /* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first |
| 32 | * seen in the AU1550 part. |
| 33 | */ |
| 34 | #ifndef _AU1000_DBDMA_H_ |
| 35 | #define _AU1000_DBDMA_H_ |
| 36 | |
| 37 | #include <linux/config.h> |
| 38 | |
| 39 | #ifndef _LANGUAGE_ASSEMBLY |
| 40 | |
| 41 | /* The DMA base addresses. |
| 42 | * The Channels are every 256 bytes (0x0100) from the channel 0 base. |
| 43 | * Interrupt status/enable is bits 15:0 for channels 15 to zero. |
| 44 | */ |
| 45 | #define DDMA_GLOBAL_BASE 0xb4003000 |
| 46 | #define DDMA_CHANNEL_BASE 0xb4002000 |
| 47 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 48 | typedef volatile struct dbdma_global { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | u32 ddma_config; |
| 50 | u32 ddma_intstat; |
| 51 | u32 ddma_throttle; |
| 52 | u32 ddma_inten; |
| 53 | } dbdma_global_t; |
| 54 | |
| 55 | /* General Configuration. |
| 56 | */ |
| 57 | #define DDMA_CONFIG_AF (1 << 2) |
| 58 | #define DDMA_CONFIG_AH (1 << 1) |
| 59 | #define DDMA_CONFIG_AL (1 << 0) |
| 60 | |
| 61 | #define DDMA_THROTTLE_EN (1 << 31) |
| 62 | |
| 63 | /* The structure of a DMA Channel. |
| 64 | */ |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 65 | typedef volatile struct au1xxx_dma_channel { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | u32 ddma_cfg; /* See below */ |
| 67 | u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ |
| 68 | u32 ddma_statptr; /* word aligned pointer to status word */ |
| 69 | u32 ddma_dbell; /* A write activates channel operation */ |
| 70 | u32 ddma_irq; /* If bit 0 set, interrupt pending */ |
| 71 | u32 ddma_stat; /* See below */ |
| 72 | u32 ddma_bytecnt; /* Byte count, valid only when chan idle */ |
| 73 | /* Remainder, up to the 256 byte boundary, is reserved. |
| 74 | */ |
| 75 | } au1x_dma_chan_t; |
| 76 | |
| 77 | #define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */ |
| 78 | #define DDMA_CFG_SP (1 << 8) /* source DMA polarity */ |
| 79 | #define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */ |
| 80 | #define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */ |
| 81 | #define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */ |
| 82 | #define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */ |
| 83 | #define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */ |
| 84 | #define DDMA_CFG_SBE (1 << 2) /* Source big endian */ |
| 85 | #define DDMA_CFG_DBE (1 << 1) /* Destination big endian */ |
| 86 | #define DDMA_CFG_EN (1 << 0) /* Channel enable */ |
| 87 | |
| 88 | /* Always set when descriptor processing done, regardless of |
| 89 | * interrupt enable state. Reflected in global intstat, don't |
| 90 | * clear this until global intstat is read/used. |
| 91 | */ |
| 92 | #define DDMA_IRQ_IN (1 << 0) |
| 93 | |
| 94 | #define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */ |
| 95 | #define DDMA_STAT_V (1 << 1) /* Descriptor valid */ |
| 96 | #define DDMA_STAT_H (1 << 0) /* Channel Halted */ |
| 97 | |
| 98 | /* "Standard" DDMA Descriptor. |
| 99 | * Must be 32-byte aligned. |
| 100 | */ |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 101 | typedef volatile struct au1xxx_ddma_desc { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | u32 dscr_cmd0; /* See below */ |
| 103 | u32 dscr_cmd1; /* See below */ |
| 104 | u32 dscr_source0; /* source phys address */ |
| 105 | u32 dscr_source1; /* See below */ |
| 106 | u32 dscr_dest0; /* Destination address */ |
| 107 | u32 dscr_dest1; /* See below */ |
| 108 | u32 dscr_stat; /* completion status */ |
| 109 | u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 110 | /* First 32bytes are HW specific!!! |
| 111 | Lets have some SW data following.. make sure its 32bytes |
| 112 | */ |
| 113 | u32 sw_status; |
| 114 | u32 sw_context; |
| 115 | u32 sw_reserved[6]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | } au1x_ddma_desc_t; |
| 117 | |
| 118 | #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ |
| 119 | #define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */ |
| 120 | #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */ |
| 121 | #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */ |
| 122 | #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */ |
| 123 | #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */ |
| 124 | #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */ |
| 125 | #define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */ |
| 126 | #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */ |
| 127 | #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */ |
| 128 | #define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */ |
| 129 | #define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */ |
| 130 | #define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */ |
| 131 | #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ |
| 132 | #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ |
| 133 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 134 | #define SW_STATUS_INUSE (1<<0) |
| 135 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | /* Command 0 device IDs. |
| 137 | */ |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 138 | #ifdef CONFIG_SOC_AU1550 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | #define DSCR_CMD0_UART0_TX 0 |
| 140 | #define DSCR_CMD0_UART0_RX 1 |
| 141 | #define DSCR_CMD0_UART3_TX 2 |
| 142 | #define DSCR_CMD0_UART3_RX 3 |
| 143 | #define DSCR_CMD0_DMA_REQ0 4 |
| 144 | #define DSCR_CMD0_DMA_REQ1 5 |
| 145 | #define DSCR_CMD0_DMA_REQ2 6 |
| 146 | #define DSCR_CMD0_DMA_REQ3 7 |
| 147 | #define DSCR_CMD0_USBDEV_RX0 8 |
| 148 | #define DSCR_CMD0_USBDEV_TX0 9 |
| 149 | #define DSCR_CMD0_USBDEV_TX1 10 |
| 150 | #define DSCR_CMD0_USBDEV_TX2 11 |
| 151 | #define DSCR_CMD0_USBDEV_RX3 12 |
| 152 | #define DSCR_CMD0_USBDEV_RX4 13 |
| 153 | #define DSCR_CMD0_PSC0_TX 14 |
| 154 | #define DSCR_CMD0_PSC0_RX 15 |
| 155 | #define DSCR_CMD0_PSC1_TX 16 |
| 156 | #define DSCR_CMD0_PSC1_RX 17 |
| 157 | #define DSCR_CMD0_PSC2_TX 18 |
| 158 | #define DSCR_CMD0_PSC2_RX 19 |
| 159 | #define DSCR_CMD0_PSC3_TX 20 |
| 160 | #define DSCR_CMD0_PSC3_RX 21 |
| 161 | #define DSCR_CMD0_PCI_WRITE 22 |
| 162 | #define DSCR_CMD0_NAND_FLASH 23 |
| 163 | #define DSCR_CMD0_MAC0_RX 24 |
| 164 | #define DSCR_CMD0_MAC0_TX 25 |
| 165 | #define DSCR_CMD0_MAC1_RX 26 |
| 166 | #define DSCR_CMD0_MAC1_TX 27 |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 167 | #endif /* CONFIG_SOC_AU1550 */ |
| 168 | |
| 169 | #ifdef CONFIG_SOC_AU1200 |
| 170 | #define DSCR_CMD0_UART0_TX 0 |
| 171 | #define DSCR_CMD0_UART0_RX 1 |
| 172 | #define DSCR_CMD0_UART1_TX 2 |
| 173 | #define DSCR_CMD0_UART1_RX 3 |
| 174 | #define DSCR_CMD0_DMA_REQ0 4 |
| 175 | #define DSCR_CMD0_DMA_REQ1 5 |
| 176 | #define DSCR_CMD0_MAE_BE 6 |
| 177 | #define DSCR_CMD0_MAE_FE 7 |
| 178 | #define DSCR_CMD0_SDMS_TX0 8 |
| 179 | #define DSCR_CMD0_SDMS_RX0 9 |
| 180 | #define DSCR_CMD0_SDMS_TX1 10 |
| 181 | #define DSCR_CMD0_SDMS_RX1 11 |
| 182 | #define DSCR_CMD0_AES_TX 13 |
| 183 | #define DSCR_CMD0_AES_RX 12 |
| 184 | #define DSCR_CMD0_PSC0_TX 14 |
| 185 | #define DSCR_CMD0_PSC0_RX 15 |
| 186 | #define DSCR_CMD0_PSC1_TX 16 |
| 187 | #define DSCR_CMD0_PSC1_RX 17 |
| 188 | #define DSCR_CMD0_CIM_RXA 18 |
| 189 | #define DSCR_CMD0_CIM_RXB 19 |
| 190 | #define DSCR_CMD0_CIM_RXC 20 |
| 191 | #define DSCR_CMD0_MAE_BOTH 21 |
| 192 | #define DSCR_CMD0_LCD 22 |
| 193 | #define DSCR_CMD0_NAND_FLASH 23 |
| 194 | #define DSCR_CMD0_PSC0_SYNC 24 |
| 195 | #define DSCR_CMD0_PSC1_SYNC 25 |
| 196 | #define DSCR_CMD0_CIM_SYNC 26 |
| 197 | #endif /* CONFIG_SOC_AU1200 */ |
| 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | #define DSCR_CMD0_THROTTLE 30 |
| 200 | #define DSCR_CMD0_ALWAYS 31 |
| 201 | #define DSCR_NDEV_IDS 32 |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 202 | /* THis macro is used to find/create custom device types */ |
| 203 | #define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) |
| 204 | #define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) |
| 205 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | |
| 207 | #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) |
| 208 | #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) |
| 209 | |
| 210 | /* Source/Destination transfer width. |
| 211 | */ |
| 212 | #define DSCR_CMD0_BYTE 0 |
| 213 | #define DSCR_CMD0_HALFWORD 1 |
| 214 | #define DSCR_CMD0_WORD 2 |
| 215 | |
| 216 | #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) |
| 217 | #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) |
| 218 | |
| 219 | /* DDMA Descriptor Type. |
| 220 | */ |
| 221 | #define DSCR_CMD0_STANDARD 0 |
| 222 | #define DSCR_CMD0_LITERAL 1 |
| 223 | #define DSCR_CMD0_CMP_BRANCH 2 |
| 224 | |
| 225 | #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) |
| 226 | |
| 227 | /* Status Instruction. |
| 228 | */ |
| 229 | #define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */ |
| 230 | #define DSCR_CMD0_ST_CURRENT 1 /* Write current status */ |
| 231 | #define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */ |
| 232 | #define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */ |
| 233 | |
| 234 | #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) |
| 235 | |
| 236 | /* Descriptor Command 1 |
| 237 | */ |
| 238 | #define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */ |
| 239 | #define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */ |
| 240 | #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ |
| 241 | #define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */ |
| 242 | |
| 243 | /* Flag description. |
| 244 | */ |
| 245 | #define DSCR_CMD1_FL_MEM_STRIDE0 0 |
| 246 | #define DSCR_CMD1_FL_MEM_STRIDE1 1 |
| 247 | #define DSCR_CMD1_FL_MEM_STRIDE2 2 |
| 248 | |
| 249 | #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) |
| 250 | |
| 251 | /* Source1, 1-dimensional stride. |
| 252 | */ |
| 253 | #define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */ |
| 254 | #define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */ |
| 255 | #define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */ |
| 256 | #define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14) |
| 257 | #define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */ |
| 258 | #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) |
| 259 | |
| 260 | /* Dest1, 1-dimensional stride. |
| 261 | */ |
| 262 | #define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */ |
| 263 | #define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */ |
| 264 | #define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */ |
| 265 | #define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14) |
| 266 | #define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */ |
| 267 | #define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0) |
| 268 | |
| 269 | #define DSCR_xTS_SIZE1 0 |
| 270 | #define DSCR_xTS_SIZE2 1 |
| 271 | #define DSCR_xTS_SIZE4 2 |
| 272 | #define DSCR_xTS_SIZE8 3 |
| 273 | #define DSCR_SRC1_STS(x) (((x) & 3) << 30) |
| 274 | #define DSCR_DEST1_DTS(x) (((x) & 3) << 30) |
| 275 | |
| 276 | #define DSCR_xAM_INCREMENT 0 |
| 277 | #define DSCR_xAM_DECREMENT 1 |
| 278 | #define DSCR_xAM_STATIC 2 |
| 279 | #define DSCR_xAM_BURST 3 |
| 280 | #define DSCR_SRC1_SAM(x) (((x) & 3) << 28) |
| 281 | #define DSCR_DEST1_DAM(x) (((x) & 3) << 28) |
| 282 | |
| 283 | /* The next descriptor pointer. |
| 284 | */ |
| 285 | #define DSCR_NXTPTR_MASK (0x07ffffff) |
| 286 | #define DSCR_NXTPTR(x) ((x) >> 5) |
| 287 | #define DSCR_GET_NXTPTR(x) ((x) << 5) |
| 288 | #define DSCR_NXTPTR_MS (1 << 27) |
| 289 | |
| 290 | /* The number of DBDMA channels. |
| 291 | */ |
| 292 | #define NUM_DBDMA_CHANS 16 |
| 293 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 294 | /* |
| 295 | * Ddma API definitions |
| 296 | * FIXME: may not fit to this header file |
| 297 | */ |
| 298 | typedef struct dbdma_device_table { |
| 299 | u32 dev_id; |
| 300 | u32 dev_flags; |
| 301 | u32 dev_tsize; |
| 302 | u32 dev_devwidth; |
| 303 | u32 dev_physaddr; /* If FIFO */ |
| 304 | u32 dev_intlevel; |
| 305 | u32 dev_intpolarity; |
| 306 | } dbdev_tab_t; |
| 307 | |
| 308 | |
| 309 | typedef struct dbdma_chan_config { |
| 310 | spinlock_t lock; |
| 311 | |
| 312 | u32 chan_flags; |
| 313 | u32 chan_index; |
| 314 | dbdev_tab_t *chan_src; |
| 315 | dbdev_tab_t *chan_dest; |
| 316 | au1x_dma_chan_t *chan_ptr; |
| 317 | au1x_ddma_desc_t *chan_desc_base; |
| 318 | au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; |
| 319 | void *chan_callparam; |
| 320 | void (*chan_callback)(int, void *, struct pt_regs *); |
| 321 | } chan_tab_t; |
| 322 | |
| 323 | #define DEV_FLAGS_INUSE (1 << 0) |
| 324 | #define DEV_FLAGS_ANYUSE (1 << 1) |
| 325 | #define DEV_FLAGS_OUT (1 << 2) |
| 326 | #define DEV_FLAGS_IN (1 << 3) |
| 327 | #define DEV_FLAGS_BURSTABLE (1 << 4) |
| 328 | #define DEV_FLAGS_SYNC (1 << 5) |
| 329 | /* end Ddma API definitions */ |
| 330 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | /* External functions for drivers to use. |
| 332 | */ |
| 333 | /* Use this to allocate a dbdma channel. The device ids are one of the |
| 334 | * DSCR_CMD0 devices IDs, which is usually redefined to a more |
| 335 | * meaningful name. The 'callback' is called during dma completion |
| 336 | * interrupt. |
| 337 | */ |
| 338 | u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, |
| 339 | void (*callback)(int, void *, struct pt_regs *), void *callparam); |
| 340 | |
| 341 | #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS |
| 342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | /* Set the device width of a in/out fifo. |
| 344 | */ |
| 345 | u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); |
| 346 | |
| 347 | /* Allocate a ring of descriptors for dbdma. |
| 348 | */ |
| 349 | u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); |
| 350 | |
| 351 | /* Put buffers on source/destination descriptors. |
| 352 | */ |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 353 | u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); |
| 354 | u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | |
| 356 | /* Get a buffer from the destination descriptor. |
| 357 | */ |
| 358 | u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); |
| 359 | |
| 360 | void au1xxx_dbdma_stop(u32 chanid); |
| 361 | void au1xxx_dbdma_start(u32 chanid); |
| 362 | void au1xxx_dbdma_reset(u32 chanid); |
| 363 | u32 au1xxx_get_dma_residue(u32 chanid); |
| 364 | |
| 365 | void au1xxx_dbdma_chan_free(u32 chanid); |
| 366 | void au1xxx_dbdma_dump(u32 chanid); |
| 367 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame^] | 368 | u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ); |
| 369 | |
| 370 | u32 au1xxx_ddma_add_device( dbdev_tab_t *dev ); |
| 371 | |
| 372 | /* |
| 373 | Some compatibilty macros -- |
| 374 | Needed to make changes to API without breaking existing drivers |
| 375 | */ |
| 376 | #define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) |
| 377 | #define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) |
| 378 | |
| 379 | #define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) |
| 380 | #define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) |
| 381 | |
| 382 | /* |
| 383 | * Flags for the put_source/put_dest functions. |
| 384 | */ |
| 385 | #define DDMA_FLAGS_IE (1<<0) |
| 386 | #define DDMA_FLAGS_NOIE (1<<1) |
| 387 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 389 | #endif /* _AU1000_DBDMA_H_ */ |