Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 1 | /* |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 3 | * |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 9 | #include <linux/bitops.h> |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 10 | #include <linux/debugfs.h> |
Thierry Reding | bc5e6de | 2013-01-21 11:09:06 +0100 | [diff] [blame] | 11 | #include <linux/err.h> |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 12 | #include <linux/iommu.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 13 | #include <linux/kernel.h> |
Hiroshi Doyu | 0760e8f | 2012-06-25 14:23:55 +0300 | [diff] [blame] | 14 | #include <linux/of.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 15 | #include <linux/of_device.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/slab.h> |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 18 | |
| 19 | #include <soc/tegra/ahb.h> |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 20 | #include <soc/tegra/mc.h> |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 21 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 22 | struct tegra_smmu { |
| 23 | void __iomem *regs; |
| 24 | struct device *dev; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 25 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 26 | struct tegra_mc *mc; |
| 27 | const struct tegra_smmu_soc *soc; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 28 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 29 | unsigned long pfn_mask; |
| 30 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 31 | unsigned long *asids; |
| 32 | struct mutex lock; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 33 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 34 | struct list_head list; |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 35 | |
| 36 | struct dentry *debugfs; |
Stephen Warren | e6bc593 | 2012-09-04 16:36:15 -0600 | [diff] [blame] | 37 | }; |
| 38 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 39 | struct tegra_smmu_as { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 40 | struct iommu_domain domain; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 41 | struct tegra_smmu *smmu; |
| 42 | unsigned int use_count; |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 43 | u32 *count; |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 44 | struct page **pts; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 45 | struct page *pd; |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 46 | dma_addr_t pd_dma; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 47 | unsigned id; |
| 48 | u32 attr; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 49 | }; |
| 50 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 51 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
| 52 | { |
| 53 | return container_of(dom, struct tegra_smmu_as, domain); |
| 54 | } |
| 55 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 56 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
| 57 | unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 58 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 59 | writel(value, smmu->regs + offset); |
Joerg Roedel | fe1229b | 2013-02-04 20:40:58 +0100 | [diff] [blame] | 60 | } |
| 61 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 62 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 63 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 64 | return readl(smmu->regs + offset); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 65 | } |
| 66 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 67 | #define SMMU_CONFIG 0x010 |
| 68 | #define SMMU_CONFIG_ENABLE (1 << 0) |
| 69 | |
| 70 | #define SMMU_TLB_CONFIG 0x14 |
| 71 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) |
| 72 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) |
| 73 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) |
| 74 | |
| 75 | #define SMMU_PTC_CONFIG 0x18 |
| 76 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) |
| 77 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) |
| 78 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) |
| 79 | |
| 80 | #define SMMU_PTB_ASID 0x01c |
| 81 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) |
| 82 | |
| 83 | #define SMMU_PTB_DATA 0x020 |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 84 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 85 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 86 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 87 | |
| 88 | #define SMMU_TLB_FLUSH 0x030 |
| 89 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) |
| 90 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) |
| 91 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) |
| 92 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) |
| 93 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
| 94 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) |
| 95 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ |
| 96 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) |
| 97 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) |
| 98 | |
| 99 | #define SMMU_PTC_FLUSH 0x034 |
| 100 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) |
| 101 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) |
| 102 | |
| 103 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
| 104 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 |
| 105 | |
| 106 | /* per-SWGROUP SMMU_*_ASID register */ |
| 107 | #define SMMU_ASID_ENABLE (1 << 31) |
| 108 | #define SMMU_ASID_MASK 0x7f |
| 109 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) |
| 110 | |
| 111 | /* page table definitions */ |
| 112 | #define SMMU_NUM_PDE 1024 |
| 113 | #define SMMU_NUM_PTE 1024 |
| 114 | |
| 115 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
| 116 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) |
| 117 | |
| 118 | #define SMMU_PDE_SHIFT 22 |
| 119 | #define SMMU_PTE_SHIFT 12 |
| 120 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 121 | #define SMMU_PD_READABLE (1 << 31) |
| 122 | #define SMMU_PD_WRITABLE (1 << 30) |
| 123 | #define SMMU_PD_NONSECURE (1 << 29) |
| 124 | |
| 125 | #define SMMU_PDE_READABLE (1 << 31) |
| 126 | #define SMMU_PDE_WRITABLE (1 << 30) |
| 127 | #define SMMU_PDE_NONSECURE (1 << 29) |
| 128 | #define SMMU_PDE_NEXT (1 << 28) |
| 129 | |
| 130 | #define SMMU_PTE_READABLE (1 << 31) |
| 131 | #define SMMU_PTE_WRITABLE (1 << 30) |
| 132 | #define SMMU_PTE_NONSECURE (1 << 29) |
| 133 | |
| 134 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
| 135 | SMMU_PDE_NONSECURE) |
| 136 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ |
| 137 | SMMU_PTE_NONSECURE) |
| 138 | |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame] | 139 | static unsigned int iova_pd_index(unsigned long iova) |
| 140 | { |
| 141 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); |
| 142 | } |
| 143 | |
| 144 | static unsigned int iova_pt_index(unsigned long iova) |
| 145 | { |
| 146 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); |
| 147 | } |
| 148 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 149 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
Russell King | 4b3c7d1 | 2015-07-27 13:29:36 +0100 | [diff] [blame] | 150 | { |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 151 | addr >>= 12; |
| 152 | return (addr & smmu->pfn_mask) == addr; |
| 153 | } |
Russell King | 4b3c7d1 | 2015-07-27 13:29:36 +0100 | [diff] [blame] | 154 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 155 | static dma_addr_t smmu_pde_to_dma(u32 pde) |
| 156 | { |
| 157 | return pde << 12; |
Russell King | 4b3c7d1 | 2015-07-27 13:29:36 +0100 | [diff] [blame] | 158 | } |
| 159 | |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 160 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
| 161 | { |
| 162 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); |
| 163 | } |
| 164 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 165 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 166 | unsigned long offset) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 167 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 168 | u32 value; |
Hiroshi Doyu | a6870e9 | 2013-01-31 10:14:10 +0200 | [diff] [blame] | 169 | |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 170 | offset &= ~(smmu->mc->soc->atom_size - 1); |
Hiroshi Doyu | a6870e9 | 2013-01-31 10:14:10 +0200 | [diff] [blame] | 171 | |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 172 | if (smmu->mc->soc->num_address_bits > 32) { |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 173 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 174 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 175 | #else |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 176 | value = 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 177 | #endif |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 178 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 179 | } |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 180 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 181 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 182 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
| 183 | } |
| 184 | |
| 185 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
| 186 | { |
| 187 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
| 188 | } |
| 189 | |
| 190 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
| 191 | unsigned long asid) |
| 192 | { |
| 193 | u32 value; |
| 194 | |
| 195 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 196 | SMMU_TLB_FLUSH_VA_MATCH_ALL; |
| 197 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 198 | } |
| 199 | |
| 200 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
| 201 | unsigned long asid, |
| 202 | unsigned long iova) |
| 203 | { |
| 204 | u32 value; |
| 205 | |
| 206 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 207 | SMMU_TLB_FLUSH_VA_SECTION(iova); |
| 208 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 209 | } |
| 210 | |
| 211 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
| 212 | unsigned long asid, |
| 213 | unsigned long iova) |
| 214 | { |
| 215 | u32 value; |
| 216 | |
| 217 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
| 218 | SMMU_TLB_FLUSH_VA_GROUP(iova); |
| 219 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
| 220 | } |
| 221 | |
| 222 | static inline void smmu_flush(struct tegra_smmu *smmu) |
| 223 | { |
| 224 | smmu_readl(smmu, SMMU_CONFIG); |
| 225 | } |
| 226 | |
| 227 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
| 228 | { |
| 229 | unsigned long id; |
| 230 | |
| 231 | mutex_lock(&smmu->lock); |
| 232 | |
| 233 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
| 234 | if (id >= smmu->soc->num_asids) { |
| 235 | mutex_unlock(&smmu->lock); |
| 236 | return -ENOSPC; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 237 | } |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 238 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 239 | set_bit(id, smmu->asids); |
| 240 | *idp = id; |
Hiroshi DOYU | 9e971a0 | 2012-07-02 14:26:38 +0300 | [diff] [blame] | 241 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 242 | mutex_unlock(&smmu->lock); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 246 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 247 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 248 | mutex_lock(&smmu->lock); |
| 249 | clear_bit(id, smmu->asids); |
| 250 | mutex_unlock(&smmu->lock); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 251 | } |
| 252 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 253 | static bool tegra_smmu_capable(enum iommu_cap cap) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 254 | { |
Joerg Roedel | 7c2aa64 | 2014-09-05 10:51:37 +0200 | [diff] [blame] | 255 | return false; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 256 | } |
| 257 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 258 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 259 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 260 | struct tegra_smmu_as *as; |
| 261 | unsigned int i; |
| 262 | uint32_t *pd; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 263 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 264 | if (type != IOMMU_DOMAIN_UNMANAGED) |
| 265 | return NULL; |
| 266 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 267 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
| 268 | if (!as) |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 269 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 270 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 271 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 272 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 273 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
| 274 | if (!as->pd) { |
| 275 | kfree(as); |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 276 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 277 | } |
| 278 | |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 279 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 280 | if (!as->count) { |
| 281 | __free_page(as->pd); |
| 282 | kfree(as); |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 283 | return NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 284 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 285 | |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 286 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
| 287 | if (!as->pts) { |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 288 | kfree(as->count); |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 289 | __free_page(as->pd); |
| 290 | kfree(as); |
| 291 | return NULL; |
| 292 | } |
| 293 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 294 | /* clear PDEs */ |
| 295 | pd = page_address(as->pd); |
| 296 | SetPageReserved(as->pd); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 297 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 298 | for (i = 0; i < SMMU_NUM_PDE; i++) |
| 299 | pd[i] = 0; |
Hiroshi Doyu | d2453b2 | 2012-07-30 08:39:18 +0300 | [diff] [blame] | 300 | |
Thierry Reding | 471d914 | 2015-03-27 11:07:25 +0100 | [diff] [blame] | 301 | /* setup aperture */ |
Joerg Roedel | 7f65ef0 | 2015-04-02 13:33:19 +0200 | [diff] [blame] | 302 | as->domain.geometry.aperture_start = 0; |
| 303 | as->domain.geometry.aperture_end = 0xffffffff; |
| 304 | as->domain.geometry.force_aperture = true; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 305 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 306 | return &as->domain; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 307 | } |
| 308 | |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 309 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 310 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 311 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 312 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 313 | /* TODO: free page directory and page tables */ |
| 314 | ClearPageReserved(as->pd); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 315 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 316 | kfree(as); |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 317 | } |
| 318 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 319 | static const struct tegra_smmu_swgroup * |
| 320 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 321 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 322 | const struct tegra_smmu_swgroup *group = NULL; |
| 323 | unsigned int i; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 324 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 325 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
| 326 | if (smmu->soc->swgroups[i].swgroup == swgroup) { |
| 327 | group = &smmu->soc->swgroups[i]; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 328 | break; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 329 | } |
| 330 | } |
| 331 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 332 | return group; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 333 | } |
| 334 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 335 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
| 336 | unsigned int asid) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 337 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 338 | const struct tegra_smmu_swgroup *group; |
| 339 | unsigned int i; |
| 340 | u32 value; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 341 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 342 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 343 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 344 | |
| 345 | if (client->swgroup != swgroup) |
| 346 | continue; |
| 347 | |
| 348 | value = smmu_readl(smmu, client->smmu.reg); |
| 349 | value |= BIT(client->smmu.bit); |
| 350 | smmu_writel(smmu, value, client->smmu.reg); |
| 351 | } |
| 352 | |
| 353 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
| 354 | if (group) { |
| 355 | value = smmu_readl(smmu, group->reg); |
| 356 | value &= ~SMMU_ASID_MASK; |
| 357 | value |= SMMU_ASID_VALUE(asid); |
| 358 | value |= SMMU_ASID_ENABLE; |
| 359 | smmu_writel(smmu, value, group->reg); |
| 360 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 361 | } |
| 362 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 363 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
| 364 | unsigned int asid) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 365 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 366 | const struct tegra_smmu_swgroup *group; |
| 367 | unsigned int i; |
| 368 | u32 value; |
| 369 | |
| 370 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
| 371 | if (group) { |
| 372 | value = smmu_readl(smmu, group->reg); |
| 373 | value &= ~SMMU_ASID_MASK; |
| 374 | value |= SMMU_ASID_VALUE(asid); |
| 375 | value &= ~SMMU_ASID_ENABLE; |
| 376 | smmu_writel(smmu, value, group->reg); |
| 377 | } |
| 378 | |
| 379 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 380 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 381 | |
| 382 | if (client->swgroup != swgroup) |
| 383 | continue; |
| 384 | |
| 385 | value = smmu_readl(smmu, client->smmu.reg); |
| 386 | value &= ~BIT(client->smmu.bit); |
| 387 | smmu_writel(smmu, value, client->smmu.reg); |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
| 392 | struct tegra_smmu_as *as) |
| 393 | { |
| 394 | u32 value; |
Hiroshi Doyu | 0760e8f | 2012-06-25 14:23:55 +0300 | [diff] [blame] | 395 | int err; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 396 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 397 | if (as->use_count > 0) { |
| 398 | as->use_count++; |
| 399 | return 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 400 | } |
| 401 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 402 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
| 403 | DMA_TO_DEVICE); |
| 404 | if (dma_mapping_error(smmu->dev, as->pd_dma)) |
| 405 | return -ENOMEM; |
| 406 | |
| 407 | /* We can't handle 64-bit DMA addresses */ |
| 408 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { |
| 409 | err = -ENOMEM; |
| 410 | goto err_unmap; |
| 411 | } |
| 412 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 413 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
| 414 | if (err < 0) |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 415 | goto err_unmap; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 416 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 417 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 418 | smmu_flush_tlb_asid(smmu, as->id); |
| 419 | |
| 420 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 421 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 422 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
| 423 | smmu_flush(smmu); |
| 424 | |
| 425 | as->smmu = smmu; |
| 426 | as->use_count++; |
| 427 | |
| 428 | return 0; |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 429 | |
| 430 | err_unmap: |
| 431 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); |
| 432 | return err; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
| 436 | struct tegra_smmu_as *as) |
| 437 | { |
| 438 | if (--as->use_count > 0) |
| 439 | return; |
| 440 | |
| 441 | tegra_smmu_free_asid(smmu, as->id); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 442 | |
| 443 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); |
| 444 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 445 | as->smmu = NULL; |
| 446 | } |
| 447 | |
| 448 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
| 449 | struct device *dev) |
| 450 | { |
| 451 | struct tegra_smmu *smmu = dev->archdata.iommu; |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 452 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 453 | struct device_node *np = dev->of_node; |
| 454 | struct of_phandle_args args; |
| 455 | unsigned int index = 0; |
| 456 | int err = 0; |
| 457 | |
| 458 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 459 | &args)) { |
| 460 | unsigned int swgroup = args.args[0]; |
| 461 | |
| 462 | if (args.np != smmu->dev->of_node) { |
| 463 | of_node_put(args.np); |
| 464 | continue; |
| 465 | } |
| 466 | |
| 467 | of_node_put(args.np); |
| 468 | |
| 469 | err = tegra_smmu_as_prepare(smmu, as); |
| 470 | if (err < 0) |
| 471 | return err; |
| 472 | |
| 473 | tegra_smmu_enable(smmu, swgroup, as->id); |
| 474 | index++; |
| 475 | } |
| 476 | |
| 477 | if (index == 0) |
| 478 | return -ENODEV; |
| 479 | |
| 480 | return 0; |
| 481 | } |
| 482 | |
| 483 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
| 484 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 485 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 486 | struct device_node *np = dev->of_node; |
| 487 | struct tegra_smmu *smmu = as->smmu; |
| 488 | struct of_phandle_args args; |
| 489 | unsigned int index = 0; |
| 490 | |
| 491 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 492 | &args)) { |
| 493 | unsigned int swgroup = args.args[0]; |
| 494 | |
| 495 | if (args.np != smmu->dev->of_node) { |
| 496 | of_node_put(args.np); |
| 497 | continue; |
| 498 | } |
| 499 | |
| 500 | of_node_put(args.np); |
| 501 | |
| 502 | tegra_smmu_disable(smmu, swgroup, as->id); |
| 503 | tegra_smmu_as_unprepare(smmu, as); |
| 504 | index++; |
| 505 | } |
| 506 | } |
| 507 | |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 508 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
| 509 | { |
| 510 | u32 *pt = page_address(pt_page); |
| 511 | |
| 512 | return pt + iova_pt_index(iova); |
| 513 | } |
| 514 | |
| 515 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 516 | dma_addr_t *dmap) |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 517 | { |
| 518 | unsigned int pd_index = iova_pd_index(iova); |
| 519 | struct page *pt_page; |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 520 | u32 *pd; |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 521 | |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 522 | pt_page = as->pts[pd_index]; |
| 523 | if (!pt_page) |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 524 | return NULL; |
| 525 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 526 | pd = page_address(as->pd); |
| 527 | *dmap = smmu_pde_to_dma(pd[pd_index]); |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 528 | |
| 529 | return tegra_smmu_pte_offset(pt_page, iova); |
| 530 | } |
| 531 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 532 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 533 | dma_addr_t *dmap) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 534 | { |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 535 | u32 *pd = page_address(as->pd), *pt; |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame] | 536 | unsigned int pde = iova_pd_index(iova); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 537 | struct tegra_smmu *smmu = as->smmu; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 538 | unsigned int i; |
| 539 | |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 540 | if (!as->pts[pde]) { |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 541 | struct page *page; |
| 542 | dma_addr_t dma; |
| 543 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 544 | page = alloc_page(GFP_KERNEL | __GFP_DMA); |
| 545 | if (!page) |
| 546 | return NULL; |
| 547 | |
| 548 | pt = page_address(page); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 549 | |
| 550 | for (i = 0; i < SMMU_NUM_PTE; i++) |
| 551 | pt[i] = 0; |
| 552 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 553 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
| 554 | DMA_TO_DEVICE); |
| 555 | if (dma_mapping_error(smmu->dev, dma)) { |
| 556 | __free_page(page); |
| 557 | return NULL; |
| 558 | } |
| 559 | |
| 560 | if (!smmu_dma_addr_valid(smmu, dma)) { |
| 561 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, |
| 562 | DMA_TO_DEVICE); |
| 563 | __free_page(page); |
| 564 | return NULL; |
| 565 | } |
| 566 | |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 567 | as->pts[pde] = page; |
| 568 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 569 | SetPageReserved(page); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 570 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 571 | pd[pde] = SMMU_MK_PDE(dma, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 572 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 573 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, |
| 574 | pde << 2, 4, DMA_TO_DEVICE); |
| 575 | smmu_flush_ptc(smmu, as->pd_dma, pde << 2); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 576 | smmu_flush_tlb_section(smmu, as->id, iova); |
| 577 | smmu_flush(smmu); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 578 | |
| 579 | *dmap = dma; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 580 | } else { |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 581 | *dmap = smmu_pde_to_dma(pd[pde]); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 582 | } |
| 583 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 584 | pt = tegra_smmu_pte_offset(as->pts[pde], iova); |
Russell King | 0b42c7c | 2015-07-27 13:29:21 +0100 | [diff] [blame] | 585 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 586 | /* Keep track of entries in this page table. */ |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 587 | if (*pt == 0) |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 588 | as->count[pde]++; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 589 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 590 | return pt; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 591 | } |
| 592 | |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 593 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 594 | { |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 595 | struct tegra_smmu *smmu = as->smmu; |
Russell King | 34d35f8 | 2015-07-27 13:29:16 +0100 | [diff] [blame] | 596 | unsigned int pde = iova_pd_index(iova); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 597 | u32 *pd = page_address(as->pd); |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 598 | struct page *page = as->pts[pde]; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 599 | |
| 600 | /* |
| 601 | * When no entries in this page table are used anymore, return the |
| 602 | * memory page to the system. |
| 603 | */ |
Russell King | 32924c7 | 2015-07-27 13:29:31 +0100 | [diff] [blame] | 604 | if (--as->count[pde] == 0) { |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 605 | unsigned int offset = pde * sizeof(*pd); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 606 | dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 607 | |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 608 | /* Clear the page directory entry first */ |
| 609 | pd[pde] = 0; |
| 610 | |
| 611 | /* Flush the page directory entry */ |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 612 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, |
| 613 | sizeof(*pd), DMA_TO_DEVICE); |
| 614 | smmu_flush_ptc(smmu, as->pd_dma, offset); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 615 | smmu_flush_tlb_section(smmu, as->id, iova); |
| 616 | smmu_flush(smmu); |
| 617 | |
| 618 | /* Finally, free the page */ |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 619 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 620 | ClearPageReserved(page); |
| 621 | __free_page(page); |
Russell King | 853520f | 2015-07-27 13:29:26 +0100 | [diff] [blame] | 622 | as->pts[pde] = NULL; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 623 | } |
| 624 | } |
| 625 | |
Russell King | 8482ee5 | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 626 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 627 | u32 *pte, dma_addr_t pte_dma, u32 val) |
Russell King | 8482ee5 | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 628 | { |
| 629 | struct tegra_smmu *smmu = as->smmu; |
| 630 | unsigned long offset = offset_in_page(pte); |
| 631 | |
| 632 | *pte = val; |
| 633 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 634 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
| 635 | 4, DMA_TO_DEVICE); |
| 636 | smmu_flush_ptc(smmu, pte_dma, offset); |
Russell King | 8482ee5 | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 637 | smmu_flush_tlb_group(smmu, as->id, iova); |
| 638 | smmu_flush(smmu); |
| 639 | } |
| 640 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 641 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
| 642 | phys_addr_t paddr, size_t size, int prot) |
| 643 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 644 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 645 | dma_addr_t pte_dma; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 646 | u32 *pte; |
| 647 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 648 | pte = as_get_pte(as, iova, &pte_dma); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 649 | if (!pte) |
Hiroshi Doyu | 0547c2f | 2012-06-25 14:23:57 +0300 | [diff] [blame] | 650 | return -ENOMEM; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 651 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 652 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
Russell King | 8482ee5 | 2015-07-27 13:29:10 +0100 | [diff] [blame] | 653 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 654 | |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 655 | return 0; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 656 | } |
| 657 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 658 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 659 | size_t size) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 660 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 661 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 662 | dma_addr_t pte_dma; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 663 | u32 *pte; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 664 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 665 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 666 | if (!pte || !*pte) |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 667 | return 0; |
Hiroshi Doyu | 39abf8a | 2012-08-02 11:46:40 +0300 | [diff] [blame] | 668 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 669 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
Russell King | b98e34f | 2015-07-27 13:29:05 +0100 | [diff] [blame] | 670 | tegra_smmu_pte_put_use(as, iova); |
| 671 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 672 | return size; |
| 673 | } |
| 674 | |
| 675 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
| 676 | dma_addr_t iova) |
| 677 | { |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 678 | struct tegra_smmu_as *as = to_smmu_as(domain); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 679 | unsigned long pfn; |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 680 | dma_addr_t pte_dma; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 681 | u32 *pte; |
| 682 | |
Russell King | e3c9719 | 2015-07-27 13:29:52 +0100 | [diff] [blame^] | 683 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
Russell King | 9113785 | 2015-07-27 13:29:00 +0100 | [diff] [blame] | 684 | if (!pte || !*pte) |
| 685 | return 0; |
| 686 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 687 | pfn = *pte & as->smmu->pfn_mask; |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 688 | |
| 689 | return PFN_PHYS(pfn); |
| 690 | } |
| 691 | |
| 692 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
| 693 | { |
| 694 | struct platform_device *pdev; |
| 695 | struct tegra_mc *mc; |
| 696 | |
| 697 | pdev = of_find_device_by_node(np); |
| 698 | if (!pdev) |
| 699 | return NULL; |
| 700 | |
| 701 | mc = platform_get_drvdata(pdev); |
| 702 | if (!mc) |
| 703 | return NULL; |
| 704 | |
| 705 | return mc->smmu; |
| 706 | } |
| 707 | |
| 708 | static int tegra_smmu_add_device(struct device *dev) |
| 709 | { |
| 710 | struct device_node *np = dev->of_node; |
| 711 | struct of_phandle_args args; |
| 712 | unsigned int index = 0; |
| 713 | |
| 714 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
| 715 | &args) == 0) { |
| 716 | struct tegra_smmu *smmu; |
| 717 | |
| 718 | smmu = tegra_smmu_find(args.np); |
| 719 | if (smmu) { |
| 720 | /* |
| 721 | * Only a single IOMMU master interface is currently |
| 722 | * supported by the Linux kernel, so abort after the |
| 723 | * first match. |
| 724 | */ |
| 725 | dev->archdata.iommu = smmu; |
| 726 | break; |
| 727 | } |
| 728 | |
| 729 | index++; |
| 730 | } |
| 731 | |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 732 | return 0; |
| 733 | } |
| 734 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 735 | static void tegra_smmu_remove_device(struct device *dev) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 736 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 737 | dev->archdata.iommu = NULL; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 738 | } |
| 739 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 740 | static const struct iommu_ops tegra_smmu_ops = { |
| 741 | .capable = tegra_smmu_capable, |
Joerg Roedel | d5f1a81 | 2015-03-26 13:43:12 +0100 | [diff] [blame] | 742 | .domain_alloc = tegra_smmu_domain_alloc, |
| 743 | .domain_free = tegra_smmu_domain_free, |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 744 | .attach_dev = tegra_smmu_attach_dev, |
| 745 | .detach_dev = tegra_smmu_detach_dev, |
| 746 | .add_device = tegra_smmu_add_device, |
| 747 | .remove_device = tegra_smmu_remove_device, |
| 748 | .map = tegra_smmu_map, |
| 749 | .unmap = tegra_smmu_unmap, |
| 750 | .map_sg = default_iommu_map_sg, |
| 751 | .iova_to_phys = tegra_smmu_iova_to_phys, |
| 752 | |
| 753 | .pgsize_bitmap = SZ_4K, |
| 754 | }; |
| 755 | |
| 756 | static void tegra_smmu_ahb_enable(void) |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 757 | { |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 758 | static const struct of_device_id ahb_match[] = { |
| 759 | { .compatible = "nvidia,tegra30-ahb", }, |
| 760 | { } |
| 761 | }; |
| 762 | struct device_node *ahb; |
| 763 | |
| 764 | ahb = of_find_matching_node(NULL, ahb_match); |
| 765 | if (ahb) { |
| 766 | tegra_ahb_enable_smmu(ahb); |
| 767 | of_node_put(ahb); |
| 768 | } |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 769 | } |
| 770 | |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 771 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
| 772 | { |
| 773 | struct tegra_smmu *smmu = s->private; |
| 774 | unsigned int i; |
| 775 | u32 value; |
| 776 | |
| 777 | seq_printf(s, "swgroup enabled ASID\n"); |
| 778 | seq_printf(s, "------------------------\n"); |
| 779 | |
| 780 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
| 781 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; |
| 782 | const char *status; |
| 783 | unsigned int asid; |
| 784 | |
| 785 | value = smmu_readl(smmu, group->reg); |
| 786 | |
| 787 | if (value & SMMU_ASID_ENABLE) |
| 788 | status = "yes"; |
| 789 | else |
| 790 | status = "no"; |
| 791 | |
| 792 | asid = value & SMMU_ASID_MASK; |
| 793 | |
| 794 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, |
| 795 | asid); |
| 796 | } |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
| 801 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) |
| 802 | { |
| 803 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); |
| 804 | } |
| 805 | |
| 806 | static const struct file_operations tegra_smmu_swgroups_fops = { |
| 807 | .open = tegra_smmu_swgroups_open, |
| 808 | .read = seq_read, |
| 809 | .llseek = seq_lseek, |
| 810 | .release = single_release, |
| 811 | }; |
| 812 | |
| 813 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) |
| 814 | { |
| 815 | struct tegra_smmu *smmu = s->private; |
| 816 | unsigned int i; |
| 817 | u32 value; |
| 818 | |
| 819 | seq_printf(s, "client enabled\n"); |
| 820 | seq_printf(s, "--------------------\n"); |
| 821 | |
| 822 | for (i = 0; i < smmu->soc->num_clients; i++) { |
| 823 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; |
| 824 | const char *status; |
| 825 | |
| 826 | value = smmu_readl(smmu, client->smmu.reg); |
| 827 | |
| 828 | if (value & BIT(client->smmu.bit)) |
| 829 | status = "yes"; |
| 830 | else |
| 831 | status = "no"; |
| 832 | |
| 833 | seq_printf(s, "%-12s %s\n", client->name, status); |
| 834 | } |
| 835 | |
| 836 | return 0; |
| 837 | } |
| 838 | |
| 839 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) |
| 840 | { |
| 841 | return single_open(file, tegra_smmu_clients_show, inode->i_private); |
| 842 | } |
| 843 | |
| 844 | static const struct file_operations tegra_smmu_clients_fops = { |
| 845 | .open = tegra_smmu_clients_open, |
| 846 | .read = seq_read, |
| 847 | .llseek = seq_lseek, |
| 848 | .release = single_release, |
| 849 | }; |
| 850 | |
| 851 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) |
| 852 | { |
| 853 | smmu->debugfs = debugfs_create_dir("smmu", NULL); |
| 854 | if (!smmu->debugfs) |
| 855 | return; |
| 856 | |
| 857 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, |
| 858 | &tegra_smmu_swgroups_fops); |
| 859 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, |
| 860 | &tegra_smmu_clients_fops); |
| 861 | } |
| 862 | |
| 863 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) |
| 864 | { |
| 865 | debugfs_remove_recursive(smmu->debugfs); |
| 866 | } |
| 867 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 868 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
| 869 | const struct tegra_smmu_soc *soc, |
| 870 | struct tegra_mc *mc) |
| 871 | { |
| 872 | struct tegra_smmu *smmu; |
| 873 | size_t size; |
| 874 | u32 value; |
| 875 | int err; |
Hiroshi DOYU | 7a31f6f | 2011-11-17 07:31:31 +0200 | [diff] [blame] | 876 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 877 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
| 878 | if (!soc) |
| 879 | return NULL; |
| 880 | |
| 881 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
| 882 | if (!smmu) |
| 883 | return ERR_PTR(-ENOMEM); |
| 884 | |
| 885 | /* |
| 886 | * This is a bit of a hack. Ideally we'd want to simply return this |
| 887 | * value. However the IOMMU registration process will attempt to add |
| 888 | * all devices to the IOMMU when bus_set_iommu() is called. In order |
| 889 | * not to rely on global variables to track the IOMMU instance, we |
| 890 | * set it here so that it can be looked up from the .add_device() |
| 891 | * callback via the IOMMU device's .drvdata field. |
| 892 | */ |
| 893 | mc->smmu = smmu; |
| 894 | |
| 895 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
| 896 | |
| 897 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
| 898 | if (!smmu->asids) |
| 899 | return ERR_PTR(-ENOMEM); |
| 900 | |
| 901 | mutex_init(&smmu->lock); |
| 902 | |
| 903 | smmu->regs = mc->regs; |
| 904 | smmu->soc = soc; |
| 905 | smmu->dev = dev; |
| 906 | smmu->mc = mc; |
| 907 | |
Thierry Reding | 804cb54 | 2015-03-27 11:07:27 +0100 | [diff] [blame] | 908 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
| 909 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", |
| 910 | mc->soc->num_address_bits, smmu->pfn_mask); |
| 911 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 912 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
| 913 | |
| 914 | if (soc->supports_request_limit) |
| 915 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); |
| 916 | |
| 917 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
| 918 | |
| 919 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
| 920 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); |
| 921 | |
| 922 | if (soc->supports_round_robin_arbitration) |
| 923 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; |
| 924 | |
| 925 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
| 926 | |
Russell King | b8fe038 | 2015-07-27 13:29:41 +0100 | [diff] [blame] | 927 | smmu_flush_ptc_all(smmu); |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 928 | smmu_flush_tlb(smmu); |
| 929 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); |
| 930 | smmu_flush(smmu); |
| 931 | |
| 932 | tegra_smmu_ahb_enable(); |
| 933 | |
| 934 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
| 935 | if (err < 0) |
| 936 | return ERR_PTR(err); |
| 937 | |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 938 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 939 | tegra_smmu_debugfs_init(smmu); |
| 940 | |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 941 | return smmu; |
| 942 | } |
Thierry Reding | d1313e7 | 2015-01-23 09:49:25 +0100 | [diff] [blame] | 943 | |
| 944 | void tegra_smmu_remove(struct tegra_smmu *smmu) |
| 945 | { |
| 946 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 947 | tegra_smmu_debugfs_exit(smmu); |
| 948 | } |