blob: 801423fe8143d23dbcffb40cd8215fda999b5f2d [file] [log] [blame]
Andreas Larssonddb27f32013-04-17 14:36:50 +02001/*
2 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 *
4 * 2013 (c) Aeroflex Gaisler AB
5 *
6 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
7 * IP core library.
8 *
9 * Full documentation of the GRGPIO core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
11 *
12 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13 * information on open firmware properties.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Contributors: Andreas Larsson <andreas@gaisler.com>
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/spinlock.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_platform.h>
31#include <linux/gpio.h>
32#include <linux/slab.h>
33#include <linux/err.h>
34#include <linux/basic_mmio_gpio.h>
Andreas Larsson08ffb222013-04-17 14:36:51 +020035#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/irqdomain.h>
Andreas Larssonddb27f32013-04-17 14:36:50 +020038
39#define GRGPIO_MAX_NGPIO 32
40
41#define GRGPIO_DATA 0x00
42#define GRGPIO_OUTPUT 0x04
43#define GRGPIO_DIR 0x08
44#define GRGPIO_IMASK 0x0c
45#define GRGPIO_IPOL 0x10
46#define GRGPIO_IEDGE 0x14
47#define GRGPIO_BYPASS 0x18
48#define GRGPIO_IMAP_BASE 0x20
49
Andreas Larsson08ffb222013-04-17 14:36:51 +020050/* Structure for an irq of the core - called an underlying irq */
51struct grgpio_uirq {
52 u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
53 u8 uirq; /* Underlying irq of the gpio driver */
54};
55
56/*
57 * Structure for an irq of a gpio line handed out by this driver. The index is
58 * used to map to the corresponding underlying irq.
59 */
60struct grgpio_lirq {
61 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62 u8 irq; /* irq for the gpio line */
63};
64
Andreas Larssonddb27f32013-04-17 14:36:50 +020065struct grgpio_priv {
66 struct bgpio_chip bgc;
67 void __iomem *regs;
68 struct device *dev;
Andreas Larsson08ffb222013-04-17 14:36:51 +020069
70 u32 imask; /* irq mask shadow register */
71
72 /*
73 * The grgpio core can have multiple "underlying" irqs. The gpio lines
74 * can be mapped to any one or none of these underlying irqs
75 * independently of each other. This driver sets up an irq domain and
76 * hands out separate irqs to each gpio line
77 */
78 struct irq_domain *domain;
79
80 /*
81 * This array contains information on each underlying irq, each
82 * irq of the grgpio core itself.
83 */
84 struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
85
86 /*
87 * This array contains information for each gpio line on the irqs
88 * obtains from this driver. An index value of -1 for a certain gpio
89 * line indicates that the line has no irq. Otherwise the index connects
90 * the irq to the underlying irq by pointing into the uirqs array.
91 */
92 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
Andreas Larssonddb27f32013-04-17 14:36:50 +020093};
94
95static inline struct grgpio_priv *grgpio_gc_to_priv(struct gpio_chip *gc)
96{
97 struct bgpio_chip *bgc = to_bgpio_chip(gc);
98
99 return container_of(bgc, struct grgpio_priv, bgc);
100}
101
Andreas Larsson08ffb222013-04-17 14:36:51 +0200102static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
103 int val)
104{
105 struct bgpio_chip *bgc = &priv->bgc;
106 unsigned long mask = bgc->pin2mask(bgc, offset);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200107
108 if (val)
109 priv->imask |= mask;
110 else
111 priv->imask &= ~mask;
112 bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200113}
114
115static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
116{
117 struct grgpio_priv *priv = grgpio_gc_to_priv(gc);
118
Dan Carpenterd3c21552014-12-17 02:53:59 +0300119 if (offset >= gc->ngpio)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200120 return -ENXIO;
121
122 if (priv->lirqs[offset].index < 0)
123 return -ENXIO;
124
125 return irq_create_mapping(priv->domain, offset);
126}
127
128/* -------------------- IRQ chip functions -------------------- */
129
130static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
131{
132 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
133 unsigned long flags;
134 u32 mask = BIT(d->hwirq);
135 u32 ipol;
136 u32 iedge;
137 u32 pol;
138 u32 edge;
139
140 switch (type) {
141 case IRQ_TYPE_LEVEL_LOW:
142 pol = 0;
143 edge = 0;
144 break;
145 case IRQ_TYPE_LEVEL_HIGH:
146 pol = mask;
147 edge = 0;
148 break;
149 case IRQ_TYPE_EDGE_FALLING:
150 pol = 0;
151 edge = mask;
152 break;
153 case IRQ_TYPE_EDGE_RISING:
154 pol = mask;
155 edge = mask;
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 spin_lock_irqsave(&priv->bgc.lock, flags);
162
163 ipol = priv->bgc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
164 iedge = priv->bgc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
165
166 priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
167 priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
168
169 spin_unlock_irqrestore(&priv->bgc.lock, flags);
170
171 return 0;
172}
173
174static void grgpio_irq_mask(struct irq_data *d)
175{
176 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
177 int offset = d->hwirq;
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900178 unsigned long flags;
179
180 spin_lock_irqsave(&priv->bgc.lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200181
182 grgpio_set_imask(priv, offset, 0);
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900183
184 spin_unlock_irqrestore(&priv->bgc.lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200185}
186
187static void grgpio_irq_unmask(struct irq_data *d)
188{
189 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
190 int offset = d->hwirq;
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900191 unsigned long flags;
192
193 spin_lock_irqsave(&priv->bgc.lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200194
195 grgpio_set_imask(priv, offset, 1);
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900196
197 spin_unlock_irqrestore(&priv->bgc.lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200198}
199
200static struct irq_chip grgpio_irq_chip = {
201 .name = "grgpio",
202 .irq_mask = grgpio_irq_mask,
203 .irq_unmask = grgpio_irq_unmask,
204 .irq_set_type = grgpio_irq_set_type,
205};
206
207static irqreturn_t grgpio_irq_handler(int irq, void *dev)
208{
209 struct grgpio_priv *priv = dev;
210 int ngpio = priv->bgc.gc.ngpio;
211 unsigned long flags;
212 int i;
213 int match = 0;
214
215 spin_lock_irqsave(&priv->bgc.lock, flags);
216
217 /*
218 * For each gpio line, call its interrupt handler if it its underlying
219 * irq matches the current irq that is handled.
220 */
221 for (i = 0; i < ngpio; i++) {
222 struct grgpio_lirq *lirq = &priv->lirqs[i];
223
224 if (priv->imask & BIT(i) && lirq->index >= 0 &&
225 priv->uirqs[lirq->index].uirq == irq) {
226 generic_handle_irq(lirq->irq);
227 match = 1;
228 }
229 }
230
231 spin_unlock_irqrestore(&priv->bgc.lock, flags);
232
233 if (!match)
234 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
235
236 return IRQ_HANDLED;
237}
238
239/*
240 * This function will be called as a consequence of the call to
241 * irq_create_mapping in grgpio_to_irq
242 */
Sachin Kamat61e38842013-06-18 17:07:03 +0530243static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
244 irq_hw_number_t hwirq)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200245{
246 struct grgpio_priv *priv = d->host_data;
247 struct grgpio_lirq *lirq;
248 struct grgpio_uirq *uirq;
249 unsigned long flags;
250 int offset = hwirq;
251 int ret = 0;
252
253 if (!priv)
254 return -EINVAL;
255
256 lirq = &priv->lirqs[offset];
257 if (lirq->index < 0)
258 return -EINVAL;
259
260 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
261 irq, offset);
262
263 spin_lock_irqsave(&priv->bgc.lock, flags);
264
265 /* Request underlying irq if not already requested */
266 lirq->irq = irq;
267 uirq = &priv->uirqs[lirq->index];
268 if (uirq->refcnt == 0) {
269 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
270 dev_name(priv->dev), priv);
271 if (ret) {
272 dev_err(priv->dev,
273 "Could not request underlying irq %d\n",
274 uirq->uirq);
275
276 spin_unlock_irqrestore(&priv->bgc.lock, flags);
277
278 return ret;
279 }
280 }
281 uirq->refcnt++;
282
283 spin_unlock_irqrestore(&priv->bgc.lock, flags);
284
285 /* Setup irq */
286 irq_set_chip_data(irq, priv);
287 irq_set_chip_and_handler(irq, &grgpio_irq_chip,
288 handle_simple_irq);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200289 irq_set_noprobe(irq);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200290
291 return ret;
292}
293
Sachin Kamat61e38842013-06-18 17:07:03 +0530294static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200295{
296 struct grgpio_priv *priv = d->host_data;
297 int index;
298 struct grgpio_lirq *lirq;
299 struct grgpio_uirq *uirq;
300 unsigned long flags;
301 int ngpio = priv->bgc.gc.ngpio;
302 int i;
303
Andreas Larsson08ffb222013-04-17 14:36:51 +0200304 irq_set_chip_and_handler(irq, NULL, NULL);
305 irq_set_chip_data(irq, NULL);
306
307 spin_lock_irqsave(&priv->bgc.lock, flags);
308
309 /* Free underlying irq if last user unmapped */
310 index = -1;
311 for (i = 0; i < ngpio; i++) {
312 lirq = &priv->lirqs[i];
313 if (lirq->irq == irq) {
314 grgpio_set_imask(priv, i, 0);
315 lirq->irq = 0;
316 index = lirq->index;
317 break;
318 }
319 }
320 WARN_ON(index < 0);
321
322 if (index >= 0) {
323 uirq = &priv->uirqs[lirq->index];
324 uirq->refcnt--;
325 if (uirq->refcnt == 0)
326 free_irq(uirq->uirq, priv);
327 }
328
329 spin_unlock_irqrestore(&priv->bgc.lock, flags);
330}
331
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900332static const struct irq_domain_ops grgpio_irq_domain_ops = {
Andreas Larsson08ffb222013-04-17 14:36:51 +0200333 .map = grgpio_irq_map,
334 .unmap = grgpio_irq_unmap,
335};
336
337/* ------------------------------------------------------------ */
338
Andreas Larssonddb27f32013-04-17 14:36:50 +0200339static int grgpio_probe(struct platform_device *ofdev)
340{
341 struct device_node *np = ofdev->dev.of_node;
342 void __iomem *regs;
343 struct gpio_chip *gc;
344 struct bgpio_chip *bgc;
345 struct grgpio_priv *priv;
346 struct resource *res;
347 int err;
348 u32 prop;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200349 s32 *irqmap;
350 int size;
351 int i;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200352
353 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
354 if (!priv)
355 return -ENOMEM;
356
357 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
358 regs = devm_ioremap_resource(&ofdev->dev, res);
359 if (IS_ERR(regs))
360 return PTR_ERR(regs);
361
362 bgc = &priv->bgc;
363 err = bgpio_init(bgc, &ofdev->dev, 4, regs + GRGPIO_DATA,
364 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
365 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
366 if (err) {
367 dev_err(&ofdev->dev, "bgpio_init() failed\n");
368 return err;
369 }
370
371 priv->regs = regs;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200372 priv->imask = bgc->read_reg(regs + GRGPIO_IMASK);
Andreas Larssonddb27f32013-04-17 14:36:50 +0200373 priv->dev = &ofdev->dev;
374
375 gc = &bgc->gc;
376 gc->of_node = np;
377 gc->owner = THIS_MODULE;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200378 gc->to_irq = grgpio_to_irq;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200379 gc->label = np->full_name;
380 gc->base = -1;
381
382 err = of_property_read_u32(np, "nbits", &prop);
383 if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
384 gc->ngpio = GRGPIO_MAX_NGPIO;
385 dev_dbg(&ofdev->dev,
386 "No or invalid nbits property: assume %d\n", gc->ngpio);
387 } else {
388 gc->ngpio = prop;
389 }
390
Andreas Larsson08ffb222013-04-17 14:36:51 +0200391 /*
392 * The irqmap contains the index values indicating which underlying irq,
393 * if anyone, is connected to that line
394 */
395 irqmap = (s32 *)of_get_property(np, "irqmap", &size);
396 if (irqmap) {
397 if (size < gc->ngpio) {
398 dev_err(&ofdev->dev,
399 "irqmap shorter than ngpio (%d < %d)\n",
400 size, gc->ngpio);
401 return -EINVAL;
402 }
403
404 priv->domain = irq_domain_add_linear(np, gc->ngpio,
405 &grgpio_irq_domain_ops,
406 priv);
407 if (!priv->domain) {
408 dev_err(&ofdev->dev, "Could not add irq domain\n");
409 return -EINVAL;
410 }
411
412 for (i = 0; i < gc->ngpio; i++) {
413 struct grgpio_lirq *lirq;
414 int ret;
415
416 lirq = &priv->lirqs[i];
417 lirq->index = irqmap[i];
418
419 if (lirq->index < 0)
420 continue;
421
422 ret = platform_get_irq(ofdev, lirq->index);
423 if (ret <= 0) {
424 /*
425 * Continue without irq functionality for that
426 * gpio line
427 */
428 dev_err(priv->dev,
429 "Failed to get irq for offset %d\n", i);
430 continue;
431 }
432 priv->uirqs[lirq->index].uirq = ret;
433 }
434 }
435
Andreas Larssonddb27f32013-04-17 14:36:50 +0200436 platform_set_drvdata(ofdev, priv);
437
438 err = gpiochip_add(gc);
439 if (err) {
440 dev_err(&ofdev->dev, "Could not add gpiochip\n");
Axel Lin879828c2014-12-20 22:47:07 +0800441 if (priv->domain)
442 irq_domain_remove(priv->domain);
Andreas Larssonddb27f32013-04-17 14:36:50 +0200443 return err;
444 }
445
Andreas Larsson08ffb222013-04-17 14:36:51 +0200446 dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
447 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
Andreas Larssonddb27f32013-04-17 14:36:50 +0200448
449 return 0;
450}
451
452static int grgpio_remove(struct platform_device *ofdev)
453{
454 struct grgpio_priv *priv = platform_get_drvdata(ofdev);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200455 unsigned long flags;
456 int i;
457 int ret = 0;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200458
Andreas Larsson08ffb222013-04-17 14:36:51 +0200459 spin_lock_irqsave(&priv->bgc.lock, flags);
460
461 if (priv->domain) {
462 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
463 if (priv->uirqs[i].refcnt != 0) {
464 ret = -EBUSY;
465 goto out;
466 }
467 }
468 }
469
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200470 gpiochip_remove(&priv->bgc.gc);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200471
472 if (priv->domain)
473 irq_domain_remove(priv->domain);
474
475out:
476 spin_unlock_irqrestore(&priv->bgc.lock, flags);
477
478 return ret;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200479}
480
Jingoo Hanf77b6442014-05-07 18:03:30 +0900481static const struct of_device_id grgpio_match[] = {
Andreas Larssonddb27f32013-04-17 14:36:50 +0200482 {.name = "GAISLER_GPIO"},
483 {.name = "01_01a"},
484 {},
485};
486
487MODULE_DEVICE_TABLE(of, grgpio_match);
488
489static struct platform_driver grgpio_driver = {
490 .driver = {
491 .name = "grgpio",
Andreas Larssonddb27f32013-04-17 14:36:50 +0200492 .of_match_table = grgpio_match,
493 },
494 .probe = grgpio_probe,
495 .remove = grgpio_remove,
496};
497module_platform_driver(grgpio_driver);
498
499MODULE_AUTHOR("Aeroflex Gaisler AB.");
500MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
501MODULE_LICENSE("GPL");