Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 1 | /* Copyright (C) 2003-2005 SBE, Inc. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License as published by |
| 5 | * the Free Software Foundation; either version 2 of the License, or |
| 6 | * (at your option) any later version. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Joe Perches | 694a980 | 2010-05-03 12:33:16 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 15 | |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <linux/hdlc.h> |
| 18 | #include "pmcc4_sysdep.h" |
| 19 | #include "sbecom_inline_linux.h" |
| 20 | #include "libsbew.h" |
| 21 | #include "pmcc4.h" |
| 22 | #include "comet.h" |
| 23 | #include "comet_tables.h" |
| 24 | |
| 25 | #ifdef SBE_INCLUDE_SYMBOLS |
| 26 | #define STATIC |
| 27 | #else |
| 28 | #define STATIC static |
| 29 | #endif |
| 30 | |
| 31 | |
Greg Kroah-Hartman | b8b7399 | 2010-12-10 10:46:30 -0800 | [diff] [blame] | 32 | extern int cxt1e1_log_level; |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 33 | |
| 34 | #define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */ |
| 35 | #define COMET_NUM_UNITS 5 /* Number of points per entry in table */ |
| 36 | |
| 37 | /* forward references */ |
| 38 | STATIC void SetPwrLevel (comet_t * comet); |
| 39 | STATIC void WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table); |
| 40 | STATIC void WrtXmtWaveformTbl (ci_t * ci, comet_t * comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]); |
| 41 | |
| 42 | |
| 43 | void *TWV_table[12] = { |
| 44 | TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB, |
| 45 | TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4, |
| 46 | TWVShortHaul5, |
| 47 | TWV_E1_75Ohm, /** PORT POINT - 75 Ohm not supported **/ |
| 48 | TWV_E1_120Ohm |
| 49 | }; |
| 50 | |
| 51 | |
| 52 | static int |
| 53 | lbo_tbl_lkup (int t1, int lbo) |
| 54 | { |
| 55 | if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) /* error switches to |
| 56 | * default */ |
| 57 | { |
| 58 | if (t1) |
| 59 | lbo = CFG_LBO_LH0; /* default T1 waveform table */ |
| 60 | else |
| 61 | lbo = CFG_LBO_E120; /* default E1 waveform table */ |
| 62 | } |
| 63 | return (lbo - 1); /* make index ZERO relative */ |
| 64 | } |
| 65 | |
| 66 | |
| 67 | void |
| 68 | init_comet (void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster, |
| 69 | u_int8_t moreParams) |
| 70 | { |
| 71 | u_int8_t isT1mode; |
| 72 | u_int8_t tix = CFG_LBO_LH0; /* T1 default */ |
| 73 | |
| 74 | isT1mode = IS_FRAME_ANY_T1 (port_mode); |
| 75 | /* T1 or E1 */ |
| 76 | if (isT1mode) |
| 77 | { |
| 78 | pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0); /* Select T1 Mode & PIO |
| 79 | * output enabled */ |
| 80 | tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0); /* default T1 waveform |
| 81 | * table */ |
| 82 | } else |
| 83 | { |
| 84 | pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0x81); /* Select E1 Mode & PIO |
| 85 | * output enabled */ |
| 86 | tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120); /* default E1 waveform |
| 87 | * table */ |
| 88 | } |
| 89 | |
| 90 | if (moreParams & CFG_LBO_MASK) |
| 91 | tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK); /* dial-in requested |
| 92 | * waveform table */ |
| 93 | |
| 94 | /* Tx line Intfc cfg ** Set for analog & no special patterns */ |
| 95 | pci_write_32 ((u_int32_t *) &comet->tx_line_cfg, 0x00); /* Transmit Line |
| 96 | * Interface Config. */ |
| 97 | |
| 98 | /* master test ** Ignore Test settings for now */ |
| 99 | pci_write_32 ((u_int32_t *) &comet->mtest, 0x00); /* making sure it's |
| 100 | * Default value */ |
| 101 | |
| 102 | /* Turn on Center (CENT) and everything else off */ |
| 103 | pci_write_32 ((u_int32_t *) &comet->rjat_cfg, 0x10); /* RJAT cfg */ |
| 104 | /* Set Jitter Attenuation to recommend T1 values */ |
| 105 | if (isT1mode) |
| 106 | { |
| 107 | pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0x2F); /* RJAT Divider N1 |
| 108 | * Control */ |
| 109 | pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0x2F); /* RJAT Divider N2 |
| 110 | * Control */ |
| 111 | } else |
| 112 | { |
| 113 | pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0xFF); /* RJAT Divider N1 |
| 114 | * Control */ |
| 115 | pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0xFF); /* RJAT Divider N2 |
| 116 | * Control */ |
| 117 | } |
| 118 | |
| 119 | /* Turn on Center (CENT) and everything else off */ |
| 120 | pci_write_32 ((u_int32_t *) &comet->tjat_cfg, 0x10); /* TJAT Config. */ |
| 121 | |
| 122 | /* Do not bypass jitter attenuation and bypass elastic store */ |
| 123 | pci_write_32 ((u_int32_t *) &comet->rx_opt, 0x00); /* rx opts */ |
| 124 | |
| 125 | /* TJAT ctrl & TJAT divider ctrl */ |
| 126 | /* Set Jitter Attenuation to recommended T1 values */ |
| 127 | if (isT1mode) |
| 128 | { |
| 129 | pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0x2F); /* TJAT Divider N1 |
| 130 | * Control */ |
| 131 | pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0x2F); /* TJAT Divider N2 |
| 132 | * Control */ |
| 133 | } else |
| 134 | { |
| 135 | pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0xFF); /* TJAT Divider N1 |
| 136 | * Control */ |
| 137 | pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0xFF); /* TJAT Divider N2 |
| 138 | * Control */ |
| 139 | } |
| 140 | |
| 141 | /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */ |
| 142 | if (isT1mode) |
| 143 | { /* Select 193-bit frame format */ |
| 144 | pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x00); |
| 145 | pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x00); |
| 146 | } else |
| 147 | { /* Select 256-bit frame format */ |
| 148 | pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x03); |
| 149 | pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x03); |
| 150 | pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x00); /* disable T1 data link |
| 151 | * receive */ |
| 152 | pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x00); /* disable T1 data link |
| 153 | * transmit */ |
| 154 | } |
| 155 | |
| 156 | /* the following is a default value */ |
| 157 | /* Enable 8 out of 10 validation */ |
| 158 | pci_write_32 ((u_int32_t *) &comet->t1_rboc_ena, 0x00); /* t1RBOC |
| 159 | * enable(BOC:BitOriented |
| 160 | * Code) */ |
| 161 | if (isT1mode) |
| 162 | { |
| 163 | |
| 164 | /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */ |
| 165 | pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x04); /* 6 bit down, 5 bit up |
| 166 | * (assert) */ |
| 167 | pci_write_32 ((u_int32_t *) &comet->ibcd_act, 0x08); /* line loopback |
| 168 | * activate pattern */ |
| 169 | pci_write_32 ((u_int32_t *) &comet->ibcd_deact, 0x24); /* deactivate code |
| 170 | * pattern (i.e.001) */ |
| 171 | } |
| 172 | /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */ |
| 173 | /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */ |
| 174 | /* 60: t1 ALMI cfg */ |
| 175 | /* Configure Line Coding */ |
| 176 | |
| 177 | switch (port_mode) |
| 178 | { |
| 179 | case CFG_FRAME_SF: /* 1 - T1 B8ZS */ |
| 180 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 181 | pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0); |
| 182 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 183 | pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */ |
| 184 | pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0); |
| 185 | break; |
| 186 | case CFG_FRAME_ESF: /* 2 - T1 B8ZS */ |
| 187 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 188 | pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20); /* Bit 5: T1 DataLink |
| 189 | * Enable */ |
| 190 | pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ |
| 191 | pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF 5:ESFFA */ |
| 192 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ |
| 193 | pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF 5:B8ZS */ |
| 194 | pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ |
| 195 | break; |
| 196 | case CFG_FRAME_E1PLAIN: /* 3 - HDB3 */ |
| 197 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 198 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 199 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0); |
| 200 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40); |
| 201 | break; |
| 202 | case CFG_FRAME_E1CAS: /* 4 - HDB3 */ |
| 203 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 204 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 205 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x60); |
| 206 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0); |
| 207 | break; |
| 208 | case CFG_FRAME_E1CRC: /* 5 - HDB3 */ |
| 209 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 210 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 211 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x10); |
| 212 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); |
| 213 | break; |
| 214 | case CFG_FRAME_E1CRC_CAS: /* 6 - HDB3 */ |
| 215 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0); |
| 216 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 217 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x70); |
| 218 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82); |
| 219 | break; |
| 220 | case CFG_FRAME_SF_AMI: /* 7 - T1 AMI */ |
| 221 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 222 | * Decoding */ |
| 223 | pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0); |
| 224 | pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0); |
| 225 | pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0); |
| 226 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 227 | break; |
| 228 | case CFG_FRAME_ESF_AMI: /* 8 - T1 AMI */ |
| 229 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 230 | * Decoding */ |
| 231 | pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20); /* 5: T1 DataLink Enable */ |
| 232 | pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */ |
| 233 | pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF 5:ESFFA */ |
| 234 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */ |
| 235 | pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */ |
| 236 | pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */ |
| 237 | break; |
| 238 | case CFG_FRAME_E1PLAIN_AMI: /* 9 - AMI */ |
| 239 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 240 | * Decoding */ |
| 241 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 242 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x80); |
| 243 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40); |
| 244 | break; |
| 245 | case CFG_FRAME_E1CAS_AMI: /* 10 - AMI */ |
| 246 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 247 | * Decoding */ |
| 248 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 249 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xe0); |
| 250 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0); |
| 251 | break; |
| 252 | case CFG_FRAME_E1CRC_AMI: /* 11 - AMI */ |
| 253 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 254 | * Decoding */ |
| 255 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 256 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x90); |
| 257 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2); |
| 258 | break; |
| 259 | case CFG_FRAME_E1CRC_CAS_AMI: /* 12 - AMI */ |
| 260 | pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line |
| 261 | * Decoding */ |
| 262 | pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0); |
| 263 | pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xf0); |
| 264 | pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82); |
| 265 | break; |
| 266 | } /* end switch */ |
| 267 | |
| 268 | /*** |
| 269 | * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) |
| 270 | * CMODE=1: Clock slave mode with BRCLK as an input, |
| 271 | * DE=0: Use falling edge of BRCLK for data, |
| 272 | * FE=0: Use falling edge of BRCLK for frame, |
| 273 | * CMS=0: Use backplane freq, |
| 274 | * RATE[1:0]=0,0: T1 |
| 275 | ***/ |
| 276 | |
| 277 | |
| 278 | /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */ |
| 279 | /* note "rate bits can only be set once after reset" */ |
| 280 | if (clockmaster) |
| 281 | { /* CMODE == clockMode, 0=clock master (so |
| 282 | * all 3 others should be slave) */ |
| 283 | if (isT1mode) /* rate = 1.544 Mb/s */ |
| 284 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x00); /* Comet 0 Master |
| 285 | * Mode(CMODE=0) */ |
| 286 | else /* rate = 2.048 Mb/s */ |
| 287 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x01); /* Comet 0 Master |
| 288 | * Mode(CMODE=0) */ |
| 289 | |
| 290 | /* 31: BRIF frame pulse cfg 06: tx timing options */ |
| 291 | pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x00); /* Master Mode |
| 292 | * i.e.FPMODE=0 (@0x20) */ |
| 293 | if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) |
| 294 | { |
Greg Kroah-Hartman | b8b7399 | 2010-12-10 10:46:30 -0800 | [diff] [blame] | 295 | if (cxt1e1_log_level >= LOG_SBEBUG12) |
Joe Perches | 694a980 | 2010-05-03 12:33:16 -0700 | [diff] [blame] | 296 | pr_info(">> %s: clockmaster internal clock\n", __func__); |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 297 | pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */ |
| 298 | } else /* external clock source */ |
| 299 | { |
Greg Kroah-Hartman | b8b7399 | 2010-12-10 10:46:30 -0800 | [diff] [blame] | 300 | if (cxt1e1_log_level >= LOG_SBEBUG12) |
Joe Perches | 694a980 | 2010-05-03 12:33:16 -0700 | [diff] [blame] | 301 | pr_info(">> %s: clockmaster external clock\n", __func__); |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 302 | pci_write_32 ((u_int32_t *) &comet->tx_time, 0x09); /* loop timing |
| 303 | * (external) */ |
| 304 | } |
| 305 | |
| 306 | } else /* slave */ |
| 307 | { |
| 308 | if (isT1mode) |
| 309 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x20); /* Slave Mode(CMODE=1, |
| 310 | * see above) */ |
| 311 | else |
| 312 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x21); /* Slave Mode (CMODE=1) */ |
| 313 | pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x20); /* Slave Mode i.e. |
| 314 | * FPMODE=1 (@0x20) */ |
Greg Kroah-Hartman | b8b7399 | 2010-12-10 10:46:30 -0800 | [diff] [blame] | 315 | if (cxt1e1_log_level >= LOG_SBEBUG12) |
Joe Perches | 694a980 | 2010-05-03 12:33:16 -0700 | [diff] [blame] | 316 | pr_info(">> %s: clockslave internal clock\n", __func__); |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 317 | pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d); /* oscillator timing */ |
| 318 | } |
| 319 | |
| 320 | /* 32: BRIF parity F-bit cfg */ |
| 321 | /* Totem-pole operation */ |
| 322 | pci_write_32 ((u_int32_t *) &comet->brif_pfcfg, 0x01); /* Receive Backplane |
| 323 | * Parity/F-bit */ |
| 324 | |
| 325 | /* dc: RLPS equalizer V ref */ |
| 326 | /* Configuration */ |
| 327 | if (isT1mode) |
| 328 | pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x2c); /* RLPS Equalizer |
| 329 | * Voltage */ |
| 330 | else |
| 331 | pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x34); /* RLPS Equalizer |
| 332 | * Voltage */ |
| 333 | |
| 334 | /* Reserved bit set and SQUELCH enabled */ |
| 335 | /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */ |
| 336 | pci_write_32 ((u_int32_t *) &comet->rlps_cfgsts, 0x11); /* RLPS Configuration |
| 337 | * Status */ |
| 338 | if (isT1mode) |
| 339 | pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x55); /* ? */ |
| 340 | else |
| 341 | pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x22); /* ? */ |
| 342 | |
| 343 | |
| 344 | /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */ |
| 345 | /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */ |
| 346 | /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */ |
| 347 | /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */ |
| 348 | /*** Transmit side is always an Input, Slave Clock*/ |
| 349 | /* 40: BTIF cfg 41: BTIF frame pulse cfg */ |
| 350 | if (isT1mode) |
| 351 | pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x38); /* BTIF Configuration |
| 352 | * Reg. */ |
| 353 | else |
| 354 | pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x39); /* BTIF Configuration |
| 355 | * Reg. */ |
| 356 | |
| 357 | pci_write_32 ((u_int32_t *) &comet->btif_fpcfg, 0x01); /* BTIF Frame Pulse |
| 358 | * Config. */ |
| 359 | |
| 360 | /* 0a: master diag 06: tx timing options */ |
| 361 | /* if set Comet to loop back */ |
| 362 | |
| 363 | /* Comets set to normal */ |
| 364 | pci_write_32 ((u_int32_t *) &comet->mdiag, 0x00); |
| 365 | |
| 366 | /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */ |
| 367 | /* Store is enabled. */ |
| 368 | |
| 369 | WrtXmtWaveformTbl (ci, comet, TWV_table[tix]); |
| 370 | if (isT1mode) |
| 371 | WrtRcvEqualizerTbl ((ci_t *) ci, comet, &T1_Equalizer[0]); |
| 372 | else |
| 373 | WrtRcvEqualizerTbl ((ci_t *) ci, comet, &E1_Equalizer[0]); |
| 374 | SetPwrLevel (comet); |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | ** Name: WrtXmtWaveform |
| 379 | ** Description: Formulate the Data for the Pulse Waveform Storage |
| 380 | ** Write register, (F2), from the sample and unit inputs. |
| 381 | ** Write the data to the Pulse Waveform Storage Data register. |
| 382 | ** Returns: Nothing |
| 383 | */ |
| 384 | STATIC void |
| 385 | WrtXmtWaveform (ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data) |
| 386 | { |
| 387 | u_int8_t WaveformAddr; |
| 388 | |
| 389 | WaveformAddr = (sample << 3) + (unit & 7); |
| 390 | pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr); |
| 391 | pci_flush_write (ci); /* for write order preservation when |
| 392 | * Optimizing driver */ |
| 393 | pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data); |
| 394 | } |
| 395 | |
| 396 | /* |
| 397 | ** Name: WrtXmtWaveformTbl |
| 398 | ** Description: Fill in the Transmit Waveform Values |
| 399 | ** for driving the transmitter DAC. |
| 400 | ** Returns: Nothing |
| 401 | */ |
| 402 | STATIC void |
| 403 | WrtXmtWaveformTbl (ci_t * ci, comet_t * comet, |
| 404 | u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]) |
| 405 | { |
| 406 | u_int32_t sample, unit; |
| 407 | |
| 408 | for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) |
| 409 | { |
| 410 | for (unit = 0; unit < COMET_NUM_UNITS; unit++) |
| 411 | WrtXmtWaveform (ci, comet, sample, unit, table[sample][unit]); |
| 412 | } |
| 413 | |
| 414 | /* Enable transmitter and set output amplitude */ |
| 415 | pci_write_32 ((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]); |
| 416 | } |
| 417 | |
| 418 | |
| 419 | /* |
| 420 | ** Name: WrtXmtWaveform |
| 421 | ** Description: Fill in the Receive Equalizer RAM from the desired |
| 422 | ** table. |
| 423 | ** Returns: Nothing |
| 424 | ** |
| 425 | ** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization |
| 426 | ** is coded with early setup of indirect address. |
| 427 | */ |
| 428 | |
| 429 | STATIC void |
| 430 | WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table) |
| 431 | { |
| 432 | u_int32_t ramaddr; |
| 433 | volatile u_int32_t value; |
| 434 | |
| 435 | for (ramaddr = 0; ramaddr < 256; ramaddr++) |
| 436 | { |
| 437 | /*** the following lines are per Errata 7, 2.5 ***/ |
| 438 | { |
| 439 | pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0x80); /* Set up for a read |
| 440 | * operation */ |
| 441 | pci_flush_write (ci); /* for write order preservation when |
| 442 | * Optimizing driver */ |
| 443 | pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, |
| 444 | * initiate a read */ |
| 445 | pci_flush_write (ci); /* for write order preservation when |
| 446 | * Optimizing driver */ |
| 447 | /* |
| 448 | * wait 3 line rate clock cycles to ensure address bits are |
| 449 | * captured by T1/E1 clock |
| 450 | */ |
| 451 | OS_uwait (4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but |
| 452 | * use 4us) */ |
| 453 | } |
| 454 | |
| 455 | value = *table++; |
| 456 | pci_write_32 ((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24)); |
| 457 | pci_write_32 ((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16)); |
| 458 | pci_write_32 ((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8)); |
| 459 | pci_write_32 ((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value); |
| 460 | pci_flush_write (ci); /* for write order preservation when |
| 461 | * Optimizing driver */ |
| 462 | |
| 463 | /* Storing RAM address, causes RAM to be updated */ |
| 464 | |
| 465 | pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0); /* Set up for a write |
| 466 | * operation */ |
| 467 | pci_flush_write (ci); /* for write order preservation when |
| 468 | * Optimizing driver */ |
| 469 | pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, |
| 470 | * initiate a read */ |
| 471 | pci_flush_write (ci); /* for write order preservation when |
| 472 | * Optimizing driver */ |
| 473 | /* |
| 474 | * wait 3 line rate clock cycles to ensure address bits are captured |
| 475 | * by T1/E1 clock |
| 476 | */ |
| 477 | OS_uwait (4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but |
| 478 | * use 4us) */ |
| 479 | } |
| 480 | |
| 481 | pci_write_32 ((u_int32_t *) &comet->rlps_eq_cfg, 0xCB); /* Enable Equalizer & |
| 482 | * set it to use 256 |
| 483 | * periods */ |
| 484 | } |
| 485 | |
| 486 | |
| 487 | /* |
| 488 | ** Name: SetPwrLevel |
| 489 | ** Description: Implement power level setting algorithm described below |
| 490 | ** Returns: Nothing |
| 491 | */ |
| 492 | |
| 493 | STATIC void |
| 494 | SetPwrLevel (comet_t * comet) |
| 495 | { |
| 496 | volatile u_int32_t temp; |
| 497 | |
| 498 | /* |
| 499 | ** Algorithm to Balance the Power Distribution of Ttip Tring |
| 500 | ** |
| 501 | ** Zero register F6 |
| 502 | ** Write 0x01 to register F4 |
| 503 | ** Write another 0x01 to register F4 |
| 504 | ** Read register F4 |
| 505 | ** Remove the 0x01 bit by Anding register F4 with 0xFE |
| 506 | ** Write the resultant value to register F4 |
| 507 | ** Repeat these steps for register F5 |
| 508 | ** Write 0x01 to register F6 |
| 509 | */ |
| 510 | pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x00); /* XLPG Fuse Data Select */ |
| 511 | |
| 512 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test |
| 513 | * Positive control */ |
| 514 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); |
| 515 | |
| 516 | temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe; |
| 517 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, temp); |
| 518 | |
| 519 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test |
| 520 | * Negative control */ |
| 521 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); |
| 522 | |
| 523 | temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe; |
| 524 | pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, temp); |
| 525 | pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x01); /* XLPG */ |
| 526 | } |
| 527 | |
| 528 | |
| 529 | /* |
| 530 | ** Name: SetCometOps |
| 531 | ** Description: Set up the selected Comet's clock edge drive for both |
| 532 | ** the transmit out the analog side and receive to the |
| 533 | ** backplane side. |
| 534 | ** Returns: Nothing |
| 535 | */ |
| 536 | #if 0 |
| 537 | STATIC void |
| 538 | SetCometOps (comet_t * comet) |
| 539 | { |
| 540 | volatile u_int8_t rd_value; |
| 541 | |
| 542 | if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) |
| 543 | { |
| 544 | rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg); /* read the BRIF |
| 545 | * Configuration */ |
| 546 | rd_value &= ~0x20; |
| 547 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); |
| 548 | |
| 549 | rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame |
| 550 | * Pulse Configuration */ |
| 551 | rd_value &= ~0x20; |
| 552 | pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); |
| 553 | } else |
| 554 | { |
| 555 | rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg); /* read the BRIF |
| 556 | * Configuration */ |
| 557 | rd_value |= 0x20; |
| 558 | pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); |
| 559 | |
| 560 | rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame |
| 561 | * Pulse Configuration */ |
| 562 | rd_value |= 0x20; |
| 563 | pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); |
| 564 | } |
| 565 | } |
| 566 | #endif |
| 567 | |
| 568 | /*** End-of-File ***/ |