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gerrit-public.fairphone.software / kernel / msm-4.9 / e415c689a8842670e161581f060575c14957f073 / . / drivers / media / dvb / frontends / stv090x.c
blob: a65f1b7849a11ecd478742b36d72f7c04cfad07c [file] [log] [blame]
Manu Abrahame415c682009-04-06 15:45:20 -0300[diff] [blame^]1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/mutex.h>
27
28#include <linux/dvb/frontend.h>
29#include "dvb_frontend.h"
30
31#include "stv6110x.h" /* for demodulator internal modes */
32
33#include "stv090x_reg.h"
34#include "stv090x.h"
35#include "stv090x_priv.h"
36
37static unsigned int verbose;
38module_param(verbose, int, 0644);
39
40struct mutex demod_lock;
41
42/* DVBS1 and DSS C/N Lookup table */
43static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
96};
97
98/* DVBS2 C/N Lookup table */
99static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
155};
156
157/* RF level C/N lookup table */
158static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
173};
174
175
176static struct stv090x_reg stv0900_initval[] = {
177
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_AGCRF1CFG, 0x11 },
180 { STV090x_AGCRF2CFG, 0x13 },
181 { STV090x_TSTTNR2, 0x21 },
182 { STV090x_TSTTNR4, 0x21 },
183 { STV090x_P2_DISTXCTL, 0x22 },
184 { STV090x_P2_F22TX, 0xc0 },
185 { STV090x_P2_F22RX, 0xc0 },
186 { STV090x_P2_DISRXCTL, 0x00 },
187 { STV090x_P2_DMDCFGMD, 0xF9 },
188 { STV090x_P2_DEMOD, 0x08 },
189 { STV090x_P2_DMDCFG3, 0xc4 },
190 { STV090x_P2_CARFREQ, 0xed },
191 { STV090x_P2_LDT, 0xd0 },
192 { STV090x_P2_LDT2, 0xb8 },
193 { STV090x_P2_TMGCFG, 0xd2 },
194 { STV090x_P2_TMGTHRISE, 0x20 },
195 { STV090x_P1_TMGCFG, 0xd2 },
196
197 { STV090x_P2_TMGTHFALL, 0x00 },
198 { STV090x_P2_FECSPY, 0x88 },
199 { STV090x_P2_FSPYDATA, 0x3a },
200 { STV090x_P2_FBERCPT4, 0x00 },
201 { STV090x_P2_FSPYBER, 0x10 },
202 { STV090x_P2_ERRCTRL1, 0x35 },
203 { STV090x_P2_ERRCTRL2, 0xc1 },
204 { STV090x_P2_CFRICFG, 0xf8 },
205 { STV090x_P2_NOSCFG, 0x1c },
206 { STV090x_P2_CORRELMANT, 0x70 },
207 { STV090x_P2_CORRELABS, 0x88 },
208 { STV090x_P2_AGC2REF, 0x38 },
209 { STV090x_P2_CARCFG, 0xe4 },
210 { STV090x_P2_ACLC, 0x1A },
211 { STV090x_P2_BCLC, 0x09 },
212 { STV090x_P2_CARHDR, 0x08 },
213 { STV090x_P2_KREFTMG, 0xc1 },
214 { STV090x_P2_SFRUPRATIO, 0xf0 },
215 { STV090x_P2_SFRLOWRATIO, 0x70 },
216 { STV090x_P2_SFRSTEP, 0x58 },
217 { STV090x_P2_TMGCFG2, 0x01 },
218 { STV090x_P2_CAR2CFG, 0x26 },
219 { STV090x_P2_BCLC2S2Q, 0x86 },
220 { STV090x_P2_BCLC2S28, 0x86 },
221 { STV090x_P2_SMAPCOEF7, 0x77 },
222 { STV090x_P2_SMAPCOEF6, 0x85 },
223 { STV090x_P2_SMAPCOEF5, 0x77 },
224 { STV090x_P2_TSCFGL, 0x20 },
225 { STV090x_P2_DMDCFG2, 0x3b },
226 { STV090x_P2_MODCODLST0, 0xff },
227 { STV090x_P2_MODCODLST1, 0xff },
228 { STV090x_P2_MODCODLST2, 0xff },
229 { STV090x_P2_MODCODLST3, 0xff },
230 { STV090x_P2_MODCODLST4, 0xff },
231 { STV090x_P2_MODCODLST5, 0xff },
232 { STV090x_P2_MODCODLST6, 0xff },
233 { STV090x_P2_MODCODLST7, 0xcc },
234 { STV090x_P2_MODCODLST8, 0xcc },
235 { STV090x_P2_MODCODLST9, 0xcc },
236 { STV090x_P2_MODCODLSTA, 0xcc },
237 { STV090x_P2_MODCODLSTB, 0xcc },
238 { STV090x_P2_MODCODLSTC, 0xcc },
239 { STV090x_P2_MODCODLSTD, 0xcc },
240 { STV090x_P2_MODCODLSTE, 0xcc },
241 { STV090x_P2_MODCODLSTF, 0xcf },
242 { STV090x_P1_DISTXCTL, 0x22 },
243 { STV090x_P1_F22TX, 0xc0 },
244 { STV090x_P1_F22RX, 0xc0 },
245 { STV090x_P1_DISRXCTL, 0x00 },
246 { STV090x_P1_DMDCFGMD, 0xf9 },
247 { STV090x_P1_DEMOD, 0x08 },
248 { STV090x_P1_DMDCFG3, 0xc4 },
249 { STV090x_P1_CARFREQ, 0xed },
250 { STV090x_P1_LDT, 0xd0 },
251 { STV090x_P1_LDT2, 0xb8 },
252 { STV090x_P1_TMGCFG, 0xd2 },
253 { STV090x_P1_TMGTHRISE, 0x20 },
254 { STV090x_P1_TMGTHFALL, 0x00 },
255 { STV090x_P1_SFRUPRATIO, 0xf0 },
256 { STV090x_P1_SFRLOWRATIO, 0x70 },
257 { STV090x_P1_TSCFGL, 0x20 },
258 { STV090x_P1_FECSPY, 0x88 },
259 { STV090x_P1_FSPYDATA, 0x3a },
260 { STV090x_P1_FBERCPT4, 0x00 },
261 { STV090x_P1_FSPYBER, 0x10 },
262 { STV090x_P1_ERRCTRL1, 0x35 },
263 { STV090x_P1_ERRCTRL2, 0xc1 },
264 { STV090x_P1_CFRICFG, 0xf8 },
265 { STV090x_P1_NOSCFG, 0x1c },
266 { STV090x_P1_CORRELMANT, 0x70 },
267 { STV090x_P1_CORRELABS, 0x88 },
268 { STV090x_P1_AGC2REF, 0x38 },
269 { STV090x_P1_CARCFG, 0xe4 },
270 { STV090x_P1_ACLC, 0x1A },
271 { STV090x_P1_BCLC, 0x09 },
272 { STV090x_P1_CARHDR, 0x08 },
273 { STV090x_P1_KREFTMG, 0xc1 },
274 { STV090x_P1_SFRSTEP, 0x58 },
275 { STV090x_P1_TMGCFG2, 0x01 },
276 { STV090x_P1_CAR2CFG, 0x26 },
277 { STV090x_P1_BCLC2S2Q, 0x86 },
278 { STV090x_P1_BCLC2S28, 0x86 },
279 { STV090x_P1_SMAPCOEF7, 0x77 },
280 { STV090x_P1_SMAPCOEF6, 0x85 },
281 { STV090x_P1_SMAPCOEF5, 0x77 },
282 { STV090x_P1_DMDCFG2, 0x3b },
283 { STV090x_P1_MODCODLST0, 0xff },
284 { STV090x_P1_MODCODLST1, 0xff },
285 { STV090x_P1_MODCODLST2, 0xff },
286 { STV090x_P1_MODCODLST3, 0xff },
287 { STV090x_P1_MODCODLST4, 0xff },
288 { STV090x_P1_MODCODLST5, 0xff },
289 { STV090x_P1_MODCODLST6, 0xff },
290 { STV090x_P1_MODCODLST7, 0xcc },
291 { STV090x_P1_MODCODLST8, 0xcc },
292 { STV090x_P1_MODCODLST9, 0xcc },
293 { STV090x_P1_MODCODLSTA, 0xcc },
294 { STV090x_P1_MODCODLSTB, 0xcc },
295 { STV090x_P1_MODCODLSTC, 0xcc },
296 { STV090x_P1_MODCODLSTD, 0xcc },
297 { STV090x_P1_MODCODLSTE, 0xcc },
298 { STV090x_P1_MODCODLSTF, 0xcf },
299 { STV090x_GENCFG, 0x1d },
300 { STV090x_NBITER_NF4, 0x37 },
301 { STV090x_NBITER_NF5, 0x29 },
302 { STV090x_NBITER_NF6, 0x37 },
303 { STV090x_NBITER_NF7, 0x33 },
304 { STV090x_NBITER_NF8, 0x31 },
305 { STV090x_NBITER_NF9, 0x2f },
306 { STV090x_NBITER_NF10, 0x39 },
307 { STV090x_NBITER_NF11, 0x3a },
308 { STV090x_NBITER_NF12, 0x29 },
309 { STV090x_NBITER_NF13, 0x37 },
310 { STV090x_NBITER_NF14, 0x33 },
311 { STV090x_NBITER_NF15, 0x2f },
312 { STV090x_NBITER_NF16, 0x39 },
313 { STV090x_NBITER_NF17, 0x3a },
314 { STV090x_NBITERNOERR, 0x04 },
315 { STV090x_GAINLLR_NF4, 0x0C },
316 { STV090x_GAINLLR_NF5, 0x0F },
317 { STV090x_GAINLLR_NF6, 0x11 },
318 { STV090x_GAINLLR_NF7, 0x14 },
319 { STV090x_GAINLLR_NF8, 0x17 },
320 { STV090x_GAINLLR_NF9, 0x19 },
321 { STV090x_GAINLLR_NF10, 0x20 },
322 { STV090x_GAINLLR_NF11, 0x21 },
323 { STV090x_GAINLLR_NF12, 0x0D },
324 { STV090x_GAINLLR_NF13, 0x0F },
325 { STV090x_GAINLLR_NF14, 0x13 },
326 { STV090x_GAINLLR_NF15, 0x1A },
327 { STV090x_GAINLLR_NF16, 0x1F },
328 { STV090x_GAINLLR_NF17, 0x21 },
329 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
330 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
331 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
332 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
333};
334
335static struct stv090x_reg stv0903_initval[] = {
336 { STV090x_OUTCFG, 0x00 },
337 { STV090x_AGCRF1CFG, 0x11 },
338 { STV090x_STOPCLK1, 0x48 },
339 { STV090x_STOPCLK2, 0x14 },
340 { STV090x_TSTTNR1, 0x27 },
341 { STV090x_TSTTNR2, 0x21 },
342 { STV090x_P1_DISTXCTL, 0x22 },
343 { STV090x_P1_F22TX, 0xc0 },
344 { STV090x_P1_F22RX, 0xc0 },
345 { STV090x_P1_DISRXCTL, 0x00 },
346 { STV090x_P1_DMDCFGMD, 0xF9 },
347 { STV090x_P1_DEMOD, 0x08 },
348 { STV090x_P1_DMDCFG3, 0xc4 },
349 { STV090x_P1_CARFREQ, 0xed },
350 { STV090x_P1_TNRCFG2, 0x82 },
351 { STV090x_P1_LDT, 0xd0 },
352 { STV090x_P1_LDT2, 0xb8 },
353 { STV090x_P1_TMGCFG, 0xd2 },
354 { STV090x_P1_TMGTHRISE, 0x20 },
355 { STV090x_P1_TMGTHFALL, 0x00 },
356 { STV090x_P1_SFRUPRATIO, 0xf0 },
357 { STV090x_P1_SFRLOWRATIO, 0x70 },
358 { STV090x_P1_TSCFGL, 0x20 },
359 { STV090x_P1_FECSPY, 0x88 },
360 { STV090x_P1_FSPYDATA, 0x3a },
361 { STV090x_P1_FBERCPT4, 0x00 },
362 { STV090x_P1_FSPYBER, 0x10 },
363 { STV090x_P1_ERRCTRL1, 0x35 },
364 { STV090x_P1_ERRCTRL2, 0xc1 },
365 { STV090x_P1_CFRICFG, 0xf8 },
366 { STV090x_P1_NOSCFG, 0x1c },
367 { STV090x_P1_CORRELMANT, 0x70 },
368 { STV090x_P1_CORRELABS, 0x88 },
369 { STV090x_P1_AGC2REF, 0x38 } ,
370 { STV090x_P1_CARCFG, 0xe4 },
371 { STV090x_P1_ACLC, 0x1A },
372 { STV090x_P1_BCLC, 0x09 } ,
373 { STV090x_P1_CARHDR, 0x08 },
374 { STV090x_P1_KREFTMG, 0xc1 },
375 { STV090x_P1_SFRSTEP, 0x58 },
376 { STV090x_P1_TMGCFG2, 0x01 },
377 { STV090x_P1_CAR2CFG, 0x26 },
378 { STV090x_P1_BCLC2S2Q, 0x86 },
379 { STV090x_P1_BCLC2S28, 0x86 },
380 { STV090x_P1_SMAPCOEF7, 0x77 },
381 { STV090x_P1_SMAPCOEF6, 0x85 },
382 { STV090x_P1_SMAPCOEF5, 0x77 },
383 { STV090x_P1_DMDCFG2, 0x3b },
384 { STV090x_P1_MODCODLST0, 0xff },
385 { STV090x_P1_MODCODLST1, 0xff },
386 { STV090x_P1_MODCODLST2, 0xff },
387 { STV090x_P1_MODCODLST3, 0xff },
388 { STV090x_P1_MODCODLST4, 0xff },
389 { STV090x_P1_MODCODLST5, 0xff },
390 { STV090x_P1_MODCODLST6, 0xff },
391 { STV090x_P1_MODCODLST7, 0xcc },
392 { STV090x_P1_MODCODLST8, 0xcc },
393 { STV090x_P1_MODCODLST9, 0xcc },
394 { STV090x_P1_MODCODLSTA, 0xcc },
395 { STV090x_P1_MODCODLSTB, 0xcc },
396 { STV090x_P1_MODCODLSTC, 0xcc },
397 { STV090x_P1_MODCODLSTD, 0xcc },
398 { STV090x_P1_MODCODLSTE, 0xcc },
399 { STV090x_P1_MODCODLSTF, 0xcf },
400 { STV090x_GENCFG, 0x1c },
401 { STV090x_NBITER_NF4, 0x37 },
402 { STV090x_NBITER_NF5, 0x29 },
403 { STV090x_NBITER_NF6, 0x37 },
404 { STV090x_NBITER_NF7, 0x33 },
405 { STV090x_NBITER_NF8, 0x31 },
406 { STV090x_NBITER_NF9, 0x2f },
407 { STV090x_NBITER_NF10, 0x39 },
408 { STV090x_NBITER_NF11, 0x3a },
409 { STV090x_NBITER_NF12, 0x29 },
410 { STV090x_NBITER_NF13, 0x37 },
411 { STV090x_NBITER_NF14, 0x33 },
412 { STV090x_NBITER_NF15, 0x2f },
413 { STV090x_NBITER_NF16, 0x39 },
414 { STV090x_NBITER_NF17, 0x3a },
415 { STV090x_NBITERNOERR, 0x04 },
416 { STV090x_GAINLLR_NF4, 0x0C },
417 { STV090x_GAINLLR_NF5, 0x0F },
418 { STV090x_GAINLLR_NF6, 0x11 },
419 { STV090x_GAINLLR_NF7, 0x14 },
420 { STV090x_GAINLLR_NF8, 0x17 },
421 { STV090x_GAINLLR_NF9, 0x19 },
422 { STV090x_GAINLLR_NF10, 0x20 },
423 { STV090x_GAINLLR_NF11, 0x21 },
424 { STV090x_GAINLLR_NF12, 0x0D },
425 { STV090x_GAINLLR_NF13, 0x0F },
426 { STV090x_GAINLLR_NF14, 0x13 },
427 { STV090x_GAINLLR_NF15, 0x1A },
428 { STV090x_GAINLLR_NF16, 0x1F },
429 { STV090x_GAINLLR_NF17, 0x21 },
430 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
431 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
432};
433
434static struct stv090x_reg stv0900_cut20_val[] = {
435
436 { STV090x_P2_DMDCFG3, 0xe8 },
437 { STV090x_P2_CARFREQ, 0x38 },
438 { STV090x_P2_CARHDR, 0x20 },
439 { STV090x_P2_KREFTMG, 0x5a },
440 { STV090x_P2_SMAPCOEF7, 0x06 },
441 { STV090x_P2_SMAPCOEF6, 0x00 },
442 { STV090x_P2_SMAPCOEF5, 0x04 },
443 { STV090x_P2_NOSCFG, 0x0c },
444 { STV090x_P1_DMDCFG3, 0xe8 },
445 { STV090x_P1_CARFREQ, 0x38 },
446 { STV090x_P1_CARHDR, 0x20 },
447 { STV090x_P1_KREFTMG, 0x5a },
448 { STV090x_P1_SMAPCOEF7, 0x06 },
449 { STV090x_P1_SMAPCOEF6, 0x00 },
450 { STV090x_P1_SMAPCOEF5, 0x04 },
451 { STV090x_P1_NOSCFG, 0x0c },
452 { STV090x_GAINLLR_NF4, 0x21 },
453 { STV090x_GAINLLR_NF5, 0x21 },
454 { STV090x_GAINLLR_NF6, 0x20 },
455 { STV090x_GAINLLR_NF7, 0x1F },
456 { STV090x_GAINLLR_NF8, 0x1E },
457 { STV090x_GAINLLR_NF9, 0x1E },
458 { STV090x_GAINLLR_NF10, 0x1D },
459 { STV090x_GAINLLR_NF11, 0x1B },
460 { STV090x_GAINLLR_NF12, 0x20 },
461 { STV090x_GAINLLR_NF13, 0x20 },
462 { STV090x_GAINLLR_NF14, 0x20 },
463 { STV090x_GAINLLR_NF15, 0x20 },
464 { STV090x_GAINLLR_NF16, 0x20 },
465 { STV090x_GAINLLR_NF17, 0x21 },
466};
467
468static struct stv090x_reg stv0903_cut20_val[] = {
469 { STV090x_P1_DMDCFG3, 0xe8 },
470 { STV090x_P1_CARFREQ, 0x38 },
471 { STV090x_P1_CARHDR, 0x20 },
472 { STV090x_P1_KREFTMG, 0x5a },
473 { STV090x_P1_SMAPCOEF7, 0x06 },
474 { STV090x_P1_SMAPCOEF6, 0x00 },
475 { STV090x_P1_SMAPCOEF5, 0x04 },
476 { STV090x_P1_NOSCFG, 0x0c },
477 { STV090x_GAINLLR_NF4, 0x21 },
478 { STV090x_GAINLLR_NF5, 0x21 },
479 { STV090x_GAINLLR_NF6, 0x20 },
480 { STV090x_GAINLLR_NF7, 0x1F },
481 { STV090x_GAINLLR_NF8, 0x1E },
482 { STV090x_GAINLLR_NF9, 0x1E },
483 { STV090x_GAINLLR_NF10, 0x1D },
484 { STV090x_GAINLLR_NF11, 0x1B },
485 { STV090x_GAINLLR_NF12, 0x20 },
486 { STV090x_GAINLLR_NF13, 0x20 },
487 { STV090x_GAINLLR_NF14, 0x20 },
488 { STV090x_GAINLLR_NF15, 0x20 },
489 { STV090x_GAINLLR_NF16, 0x20 },
490 { STV090x_GAINLLR_NF17, 0x21 }
491};
492
493/* Cut 1.x Long Frame Tracking CR loop */
494static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
495 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
496 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
497 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
498 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
499 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
500 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
501 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
502 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
503 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
504 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
505 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
506 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
507 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
508 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
509 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
510};
511
512/* Cut 2.0 Long Frame Tracking CR loop */
513static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
514 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
515 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
516 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
517 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
518 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
519 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
520 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
521 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
522 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
523 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
524 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
525 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
526 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
527 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
528 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
529};
530
531
532/* Cut 2.0 Long Frame Tracking CR Loop */
533static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
534 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
535 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
536 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
537 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
538 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
539 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
540 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
541 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
542 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
543 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
544 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
545 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
546};
547
548
549static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
550 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
551 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
552 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
553 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
554};
555
556
557/* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
558static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
559 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
560 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
561 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
562 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
563 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
564};
565
566
567static inline s32 comp2(s32 __x, s32 __width)
568{
569 if (__width == 32)
570 return __x;
571 else
572 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
573}
574
575static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
576{
577 const struct stv090x_config *config = state->config;
578 int ret;
579
580 u8 b0[] = { reg >> 8, reg & 0xff };
581 u8 buf;
582
583 struct i2c_msg msg[] = {
584 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
585 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
586 };
587
588 ret = i2c_transfer(state->i2c, msg, 2);
589 if (ret != 2) {
590 if (ret != -ERESTARTSYS)
591 dprintk(FE_ERROR, 1,
592 "Read error, Reg=[0x%02x], Status=%d",
593 reg, ret);
594
595 return ret < 0 ? ret : -EREMOTEIO;
596 }
597 if (unlikely(*state->verbose >= FE_DEBUGREG))
598 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
599 reg, buf);
600
601 return (unsigned int) buf;
602}
603
604static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
605{
606 const struct stv090x_config *config = state->config;
607 int ret;
608 u8 buf[2 + count];
609 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
610
611 buf[0] = reg >> 8;
612 buf[1] = reg & 0xff;
613 memcpy(&buf[2], data, count);
614
615 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
616 int i;
617
618 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
619 for (i = 0; i < count; i++)
620 printk(" %02x", data[i]);
621 printk("\n");
622 }
623
624 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
625 if (ret != 1) {
626 if (ret != -ERESTARTSYS)
627 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
628 reg, data[0], count, ret);
629 return ret < 0 ? ret : -EREMOTEIO;
630 }
631
632 return 0;
633}
634
635static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
636{
637 return stv090x_write_regs(state, reg, &data, 1);
638}
639
640static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
641{
642 struct stv090x_state *state = fe->demodulator_priv;
643 u32 reg;
644
645 reg = STV090x_READ_DEMOD(state, I2CRPT);
646
647 if (enable) {
648 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
649 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
650 goto err;
651
652 } else {
653 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
654 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
655 goto err;
656 }
657 return 0;
658err:
659 dprintk(FE_ERROR, 1, "I/O error");
660 return -1;
661}
662
663static void stv090x_get_lock_tmg(struct stv090x_state *state)
664{
665 switch (state->algo) {
666 case STV090x_BLIND_SEARCH:
667 dprintk(FE_DEBUG, 1, "Blind Search");
668 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
669 state->DemodTimeout = 1500;
670 state->FecTimeout = 400;
671 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
672 state->DemodTimeout = 1000;
673 state->FecTimeout = 300;
674 } else { /*SR >20Msps*/
675 state->DemodTimeout = 700;
676 state->FecTimeout = 100;
677 }
678 break;
679
680 case STV090x_COLD_SEARCH:
681 case STV090x_WARM_SEARCH:
682 default:
683 dprintk(FE_DEBUG, 1, "Normal Search");
684 if (state->srate <= 1000000) { /*SR <=1Msps*/
685 state->DemodTimeout = 4500;
686 state->FecTimeout = 1700;
687 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
688 state->DemodTimeout = 2500;
689 state->FecTimeout = 1100;
690 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
691 state->DemodTimeout = 1000;
692 state->FecTimeout = 550;
693 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
694 state->DemodTimeout = 700;
695 state->FecTimeout = 250;
696 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
697 state->DemodTimeout = 400;
698 state->FecTimeout = 130;
699 } else { /*SR >20Msps*/
700 state->DemodTimeout = 300;
701 state->FecTimeout = 100;
702 }
703 break;
704 }
705
706 if (state->algo == STV090x_WARM_SEARCH)
707 state->DemodTimeout /= 2;
708}
709
710static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
711{
712 u32 sym;
713
714 if (srate > 6000000) {
715 sym = (srate / 1000) * 65536;
716 sym /= (state->mclk / 1000);
717 } else {
718 sym = (srate / 100) * 65536;
719 sym /= (state->mclk / 100);
720 }
721
722 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) /* MSB */
723 goto err;
724 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
725 goto err;
726 return 0;
727err:
728 dprintk(FE_ERROR, 1, "I/O error");
729 return -1;
730}
731
732static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
733{
734 u32 sym;
735
736 srate = 105 * (srate / 100);
737 if (srate > 6000000) {
738 sym = (srate / 1000) * 65536;
739 sym /= (clk / 1000);
740 } else {
741 sym = (srate / 100) * 65536;
742 sym /= (clk / 100);
743 }
744 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
745 goto err;
746 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
747 goto err;
748 return 0;
749err:
750 dprintk(FE_ERROR, 1, "I/O error");
751 return -1;
752}
753
754static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
755{
756 u32 sym;
757
758 srate = 95 * (srate / 100);
759 if (srate > 6000000) {
760 sym = (srate / 1000) * 65536;
761 sym /= (clk / 1000);
762 } else {
763 sym = (srate / 100) * 65536;
764 sym /= (clk / 100);
765 }
766 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
767 goto err;
768 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
769 goto err;
770 return 0;
771err:
772 dprintk(FE_ERROR, 1, "I/O error");
773 return -1;
774}
775
776static u32 stv090x_car_width(u32 srate, u32 rolloff)
777{
778 return srate + (srate * rolloff) / 100;
779}
780
781static int stv090x_set_vit_thacq(struct stv090x_state *state)
782{
783 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
784 goto err;
785 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
786 goto err;
787 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
788 goto err;
789 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
790 goto err;
791 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
792 goto err;
793 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
794 goto err;
795 return 0;
796err:
797 dprintk(FE_ERROR, 1, "I/O error");
798 return -1;
799}
800
801static int stv090x_set_vit_thtracq(struct stv090x_state *state)
802{
803 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
804 goto err;
805 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
806 goto err;
807 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
808 goto err;
809 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
810 goto err;
811 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
812 goto err;
813 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
814 goto err;
815 return 0;
816err:
817 dprintk(FE_ERROR, 1, "I/O error");
818 return -1;
819}
820
821static int stv090x_set_viterbi(struct stv090x_state *state)
822{
823 switch (state->search_mode) {
824 case STV090x_SEARCH_AUTO:
825 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
826 goto err;
827 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
828 goto err;
829 break;
830 case STV090x_SEARCH_DVBS1:
831 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
832 goto err;
833 switch (state->fec) {
834 case STV090x_PR12:
835 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
836 goto err;
837 break;
838
839 case STV090x_PR23:
840 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
841 goto err;
842 break;
843
844 case STV090x_PR34:
845 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
846 goto err;
847 break;
848
849 case STV090x_PR56:
850 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
851 goto err;
852 break;
853
854 case STV090x_PR78:
855 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
856 goto err;
857 break;
858
859 default:
860 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
861 goto err;
862 break;
863 }
864 break;
865 case STV090x_SEARCH_DSS:
866 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
867 goto err;
868 switch (state->fec) {
869 case STV090x_PR12:
870 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
871 goto err;
872 break;
873
874 case STV090x_PR23:
875 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
876 goto err;
877 break;
878
879 case STV090x_PR67:
880 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
881 goto err;
882 break;
883
884 default:
885 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
886 goto err;
887 break;
888 }
889 break;
890 default:
891 break;
892 }
893 return 0;
894err:
895 dprintk(FE_ERROR, 1, "I/O error");
896 return -1;
897}
898
899static int stv090x_stop_modcod(struct stv090x_state *state)
900{
901 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
902 goto err;
903 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
904 goto err;
905 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
906 goto err;
907 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
908 goto err;
909 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
910 goto err;
911 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
912 goto err;
913 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
914 goto err;
915 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
916 goto err;
917 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
918 goto err;
919 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
920 goto err;
921 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
922 goto err;
923 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
924 goto err;
925 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
926 goto err;
927 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
928 goto err;
929 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
930 goto err;
931 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
932 goto err;
933 return 0;
934err:
935 dprintk(FE_ERROR, 1, "I/O error");
936 return -1;
937}
938
939static int stv090x_activate_modcod(struct stv090x_state *state)
940{
941 u32 matype, modcod, f_mod, index;
942
943 if (state->dev_ver <= 0x11) {
944 msleep(5);
945 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
946 matype = modcod & 0x03;
947 modcod = (modcod & 0x7f) >> 2;
948 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
949
950 switch (matype) {
951 default:
952 case 0:
953 f_mod = 14;
954 break;
955 case 1:
956 f_mod = 13;
957 break;
958 case 2:
959 f_mod = 11;
960 break;
961 case 3:
962 f_mod = 7;
963 break;
964 }
965 if (matype <= 1) {
966 if (modcod % 2) {
967 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
968 goto err;
969 } else {
970 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
971 goto err;
972 }
973 }
974 } else if (state->dev_ver >= 0x12) {
975 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
976 goto err;
977 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
978 goto err;
979 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
980 goto err;
981 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
982 goto err;
983 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
984 goto err;
985 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
986 goto err;
987 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
988 goto err;
989 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
990 goto err;
991 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
992 goto err;
993 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
994 goto err;
995 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
996 goto err;
997 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
998 goto err;
999 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1000 goto err;
1001 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1002 goto err;
1003 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1004 goto err;
1005 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1006 goto err;
1007 }
1008 return 0;
1009err:
1010 dprintk(FE_ERROR, 1, "I/O error");
1011 return -1;
1012}
1013
1014static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1015{
1016 u32 reg;
1017
1018 switch (state->demod) {
1019 case STV090x_DEMODULATOR_0:
1020 mutex_lock(&demod_lock);
1021 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1022 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1023 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1024 goto err;
1025 mutex_unlock(&demod_lock);
1026 break;
1027
1028 case STV090x_DEMODULATOR_1:
1029 mutex_lock(&demod_lock);
1030 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1031 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1032 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1033 goto err;
1034 mutex_unlock(&demod_lock);
1035 break;
1036
1037 default:
1038 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1039 break;
1040 }
1041 return 0;
1042err:
1043 mutex_unlock(&demod_lock);
1044 dprintk(FE_ERROR, 1, "I/O error");
1045 return -1;
1046}
1047
1048static int stv090x_delivery_search(struct stv090x_state *state)
1049{
1050 u32 reg;
1051
1052 switch (state->search_mode) {
1053 case STV090x_SEARCH_DVBS1:
1054 case STV090x_SEARCH_DSS:
1055 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1056 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1057 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1058 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1059 goto err;
1060
1061 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1062 if (stv090x_vitclk_ctl(state, 0) < 0)
1063 goto err;
1064
1065 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1066 goto err;
1067 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1068 goto err;
1069 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1070 goto err;
1071
1072 stv090x_set_vit_thacq(state);
1073 stv090x_set_viterbi(state);
1074 break;
1075
1076 case STV090x_SEARCH_DVBS2:
1077 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1078 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1079 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1080 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1081 goto err;
1082 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1083 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1084 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1085 goto err;
1086
1087 if (stv090x_vitclk_ctl(state, 1) < 0)
1088 goto err;
1089
1090 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1091 goto err;
1092 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1093 goto err;
1094 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1095 goto err;
1096
1097 if (state->demod_mode != STV090x_SINGLE) {
1098 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1099 stv090x_stop_modcod(state);
1100 else
1101 stv090x_activate_modcod(state);
1102 }
1103 break;
1104
1105 case STV090x_SEARCH_AUTO:
1106 default:
1107 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1108 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1109 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1110 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1111 goto err;
1112 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1113 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1114 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1115 goto err;
1116
1117 if (stv090x_vitclk_ctl(state, 1) < 0)
1118 goto err;
1119
1120 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1121 goto err;
1122 if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
1123 goto err;
1124 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1125 goto err;
1126
1127 if (state->demod_mode != STV090x_SINGLE) {
1128 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1129 stv090x_stop_modcod(state);
1130 else
1131 stv090x_activate_modcod(state);
1132 }
1133 stv090x_set_vit_thacq(state);
1134 stv090x_set_viterbi(state);
1135 break;
1136 }
1137 return 0;
1138err:
1139 dprintk(FE_ERROR, 1, "I/O error");
1140 return -1;
1141}
1142
1143static int stv090x_start_search(struct stv090x_state *state)
1144{
1145 u32 reg;
1146
1147 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1148 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1149 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1150 goto err;
1151
1152 if (state->dev_ver == 0x10) {
1153 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1154 goto err;
1155 }
1156 if (state->dev_ver < 0x20) {
1157 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1158 goto err;
1159 }
1160 if (state->srate <= 5000000) {
1161 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1162 goto err;
1163 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1164 goto err;
1165 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1166 goto err;
1167 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1168 goto err;
1169 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1170 goto err;
1171
1172 /*enlarge the timing bandwith for Low SR*/
1173 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1174 goto err;
1175 } else {
1176 /* If the symbol rate is >5 Msps
1177 Set The carrier search up and low to auto mode */
1178 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1179 goto err;
1180 /*reduce the timing bandwith for high SR*/
1181 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1182 goto err;
1183 }
1184 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1185 goto err;
1186 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1187 goto err;
1188
1189 if (state->dev_ver >= 0x20) {
1190 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1191 goto err;
1192 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1193 goto err;
1194
1195 if ((state->search_mode == STV090x_DVBS1) ||
1196 (state->search_mode == STV090x_DSS) ||
1197 (state->search_mode == STV090x_SEARCH_AUTO)) {
1198
1199 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1200 goto err;
1201 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1202 goto err;
1203 }
1204 }
1205
1206 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1207 goto err;
1208 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1209 goto err;
1210 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1211 goto err;
1212
1213 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1214 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1215 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1216 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1217 goto err;
1218 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1219 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1220 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1221 goto err;
1222
1223 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1224 if (state->srate < 10000000) {
1225 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1226 goto err;
1227 } else {
1228 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1229 goto err;
1230 }
1231 } else {
1232 if (state->srate < 10000000) {
1233 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1234 goto err;
1235 } else {
1236 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1237 goto err;
1238 }
1239 }
1240
1241 switch (state->algo) {
1242 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1243 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1244 goto err;
1245 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1246 goto err;
1247 break;
1248
1249 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1250 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1251 goto err;
1252 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1253 goto err;
1254 break;
1255
1256 default:
1257 break;
1258 }
1259 return 0;
1260err:
1261 dprintk(FE_ERROR, 1, "I/O error");
1262 return -1;
1263}
1264
1265static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1266{
1267 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1268 s32 i, j, steps, dir;
1269
1270 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1271 goto err;
1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1273 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1274 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1276 goto err;
1277
1278 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1279 goto err;
1280 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1281 goto err;
1282 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1283 goto err;
1284 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1285 goto err;
1286 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1287 goto err;
1288 stv090x_set_srate(state, 1000000);
1289
1290 steps = -1 + state->search_range / 1000000;
1291 steps /= 2;
1292 steps = (2 * steps) + 1;
1293 if (steps < 0)
1294 steps = 1;
1295
1296 dir = 1;
1297 freq_step = (1000000 * 256) / (state->mclk / 256);
1298 freq_init = 0;
1299
1300 for (i = 0; i < steps; i++) {
1301 if (dir > 0)
1302 freq_init = freq_init + (freq_step * i);
1303 else
1304 freq_init = freq_init - (freq_step * i);
1305
1306 dir = -1;
1307
1308 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1309 goto err;
1310 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1311 goto err;
1312 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1313 goto err;
1314 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1315 goto err;
1316 msleep(10);
1317 for (j = 0; j < 10; j++) {
1318 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1319 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1320 }
1321 agc2 /= 10;
1322 agc2_min = 0xffff;
1323 if (agc2 < 0xffff)
1324 agc2_min = agc2;
1325 }
1326
1327 return agc2_min;
1328err:
1329 dprintk(FE_ERROR, 1, "I/O error");
1330 return -1;
1331}
1332
1333static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1334{
1335 u8 r3, r2, r1, r0;
1336 s32 srate, int_1, int_2, tmp_1, tmp_2;
1337 u32 pow2;
1338
1339 r3 = STV090x_READ_DEMOD(state, SFR3);
1340 r2 = STV090x_READ_DEMOD(state, SFR2);
1341 r1 = STV090x_READ_DEMOD(state, SFR1);
1342 r0 = STV090x_READ_DEMOD(state, SFR0);
1343
1344 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1345
1346 pow2 = 1 << 16;
1347 int_1 = clk / pow2;
1348 int_2 = srate / pow2;
1349
1350 tmp_1 = clk % pow2;
1351 tmp_2 = srate % pow2;
1352
1353 srate = (int_1 * int_2) +
1354 ((int_1 * tmp_2) / pow2) +
1355 ((int_2 * tmp_1) / pow2);
1356
1357 return srate;
1358}
1359
1360static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1361{
1362 struct dvb_frontend *fe = &state->frontend;
1363
1364 int tmg_lock = 0, i;
1365 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1366 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1367
1368 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1369 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1371 goto err;
1372 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1373 goto err;
1374 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1375 goto err;
1376 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1377 goto err;
1378 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1379 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1380 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1381 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1382 goto err;
1383
1384 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1385 goto err;
1386 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1387 goto err;
1388 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1389 goto err;
1390 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1391 goto err;
1392 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1393 goto err;
1394 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1395 goto err;
1396
1397 if (state->dev_ver >= 0x20) {
1398 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1399 goto err;
1400 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1401 goto err;
1402 } else {
1403 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1404 goto err;
1405 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1406 goto err;
1407 }
1408
1409 if (state->srate <= 2000000)
1410 car_step = 1000;
1411 else if (state->srate <= 5000000)
1412 car_step = 2000;
1413 else if (state->srate <= 12000000)
1414 car_step = 3000;
1415 else
1416 car_step = 5000;
1417
1418 steps = -1 + ((state->search_range / 1000) / car_step);
1419 steps /= 2;
1420 steps = (2 * steps) + 1;
1421 if (steps < 0)
1422 steps = 1;
1423 else if (steps > 10) {
1424 steps = 11;
1425 car_step = (state->search_range / 1000) / 10;
1426 }
1427 cur_step = 0;
1428 dir = 1;
1429 freq = state->frequency;
1430
1431 while ((!tmg_lock) && (cur_step < steps)) {
1432 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1433 goto err;
1434 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1435 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1436 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1437 goto err;
1438 msleep(50);
1439 for (i = 0; i < 10; i++) {
1440 reg = STV090x_READ_DEMOD(state, DSTATUS);
1441 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1442 tmg_cpt++;
1443 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1444 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1445 }
1446 agc2 /= 10;
1447 srate_coarse = stv090x_get_srate(state, state->mclk);
1448 cur_step++;
1449 dir *= -1;
1450 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1451 tmg_lock = 1;
1452 else if (cur_step < steps) {
1453 if (dir > 0)
1454 freq += cur_step * car_step;
1455 else
1456 freq -= cur_step * car_step;
1457
1458 /* Setup tuner */
1459 stv090x_i2c_gate_ctrl(fe, 1);
1460
1461 if (state->config->tuner_set_frequency)
1462 state->config->tuner_set_frequency(fe, state->frequency);
1463
1464 if (state->config->tuner_set_bandwidth)
1465 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1466
1467 stv090x_i2c_gate_ctrl(fe, 0);
1468 msleep(50);
1469 stv090x_i2c_gate_ctrl(fe, 1);
1470
1471 if (state->config->tuner_get_status)
1472 state->config->tuner_get_status(fe, &reg);
1473
1474 if (reg)
1475 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1476 else
1477 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1478
1479 stv090x_i2c_gate_ctrl(fe, 0);
1480
1481 }
1482 }
1483 if (!tmg_lock)
1484 srate_coarse = 0;
1485 else
1486 srate_coarse = stv090x_get_srate(state, state->mclk);
1487
1488 return srate_coarse;
1489err:
1490 dprintk(FE_ERROR, 1, "I/O error");
1491 return -1;
1492}
1493
1494static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1495{
1496 u32 srate_coarse, freq_coarse, sym, reg;
1497
1498 srate_coarse = stv090x_get_srate(state, state->mclk);
1499 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1500 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1501 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1502
1503 if (sym < state->srate)
1504 srate_coarse = 0;
1505 else {
1506 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1507 goto err;
1508 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1509 goto err;
1510 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1511 goto err;
1512 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1513 goto err;
1514 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1515 goto err;
1516 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1517 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1518 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1519 goto err;
1520
1521 if (state->dev_ver >= 0x20) {
1522 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1523 goto err;
1524 } else {
1525 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1526 goto err;
1527 }
1528
1529 if (srate_coarse > 3000000) {
1530 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1531 sym = (sym / 1000) * 65536;
1532 sym /= (state->mclk / 1000);
1533 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1534 goto err;
1535 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1536 goto err;
1537 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1538 sym = (sym / 1000) * 65536;
1539 sym /= (state->mclk / 1000);
1540 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1541 goto err;
1542 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1543 goto err;
1544 sym = (srate_coarse / 1000) * 65536;
1545 sym /= (state->mclk / 1000);
1546 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1547 goto err;
1548 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1549 goto err;
1550 } else {
1551 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1552 sym = (sym / 100) * 65536;
1553 sym /= (state->mclk / 100);
1554 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1555 goto err;
1556 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1557 goto err;
1558 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1559 sym = (sym / 100) * 65536;
1560 sym /= (state->mclk / 100);
1561 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1562 goto err;
1563 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1564 goto err;
1565 sym = (srate_coarse / 100) * 65536;
1566 sym /= (state->mclk / 100);
1567 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1568 goto err;
1569 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1570 goto err;
1571 }
1572 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1573 goto err;
1574 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1575 goto err;
1576 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1577 goto err;
1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1579 goto err;
1580 }
1581
1582 return srate_coarse;
1583
1584err:
1585 dprintk(FE_ERROR, 1, "I/O error");
1586 return -1;
1587}
1588
1589static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1590{
1591 s32 timer = 0, lock = 0;
1592 u32 reg;
1593 u8 stat;
1594
1595 while ((timer < timeout) && (!lock)) {
1596 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1597 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1598
1599 switch (stat) {
1600 case 0: /* searching */
1601 case 1: /* first PLH detected */
1602 default:
1603 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1604 lock = 0;
1605 break;
1606 case 2: /* DVB-S2 mode */
1607 case 3: /* DVB-S1/legacy mode */
1608 reg = STV090x_READ_DEMOD(state, DSTATUS);
1609 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1610 break;
1611 }
1612
1613 if (!lock)
1614 msleep(10);
1615 else
1616 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1617
1618 timer += 10;
1619 }
1620 return lock;
1621}
1622
1623static int stv090x_blind_search(struct stv090x_state *state)
1624{
1625 u32 agc2, reg, srate_coarse;
1626 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1627 u8 k_ref, k_max, k_min;
1628 int coarse_fail, lock;
1629
1630 if (state->dev_ver < 0x20) {
1631 k_max = 233;
1632 k_min = 143;
1633 } else {
1634 k_max = 120;
1635 k_min = 30;
1636 }
1637
1638 agc2 = stv090x_get_agc2_min_level(state);
1639
1640 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1641 lock = 0;
1642 } else {
1643 if (state->dev_ver == 0x10) {
1644 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1645 goto err;
1646 }
1647 if (state->dev_ver < 0x20) {
1648 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1649 goto err;
1650 }
1651
1652 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1653 goto err;
1654 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1655 goto err;
1656 if (state->dev_ver >= 0x20) {
1657 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1658 goto err;
1659 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1660 goto err;
1661 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1662 goto err;
1663 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1664 goto err;
1665 }
1666
1667 k_ref = k_max;
1668 do {
1669 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1670 goto err;
1671 if (stv090x_srate_srch_coarse(state) != 0) {
1672 srate_coarse = stv090x_srate_srch_fine(state);
1673 if (srate_coarse != 0) {
1674 stv090x_get_lock_tmg(state);
1675 lock = stv090x_get_dmdlock(state, timeout_dmd);
1676 } else {
1677 lock = 0;
1678 }
1679 } else {
1680 cpt_fail = 0;
1681 agc2_ovflw = 0;
1682 for (i = 0; i < 10; i++) {
1683 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1684 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1685 if (agc2 >= 0xff00)
1686 agc2_ovflw++;
1687 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1688 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1689 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1690
1691 cpt_fail++;
1692 }
1693 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1694 coarse_fail = 1;
1695
1696 lock = 0;
1697 }
1698 k_ref -= 30;
1699 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1700 }
1701
1702 return lock;
1703
1704err:
1705 dprintk(FE_ERROR, 1, "I/O error");
1706 return -1;
1707}
1708
1709static int stv090x_chk_tmg(struct stv090x_state *state)
1710{
1711 u32 reg;
1712 s32 tmg_cpt, i;
1713 u8 freq, tmg_thh, tmg_thl;
1714 int tmg_lock;
1715
1716 freq = STV090x_READ_DEMOD(state, CARFREQ);
1717 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1718 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1719 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1720 goto err;
1721 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1722 goto err;
1723
1724 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1725 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1726 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1727 goto err;
1728 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1729 goto err;
1730
1731 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1732 goto err;
1733 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1734 goto err;
1735
1736 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1737 goto err;
1738 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1739 goto err;
1740 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1741 goto err;
1742
1743 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1744 goto err;
1745 msleep(10);
1746
1747 for (i = 0; i < 10; i++) {
1748 reg = STV090x_READ_DEMOD(state, DSTATUS);
1749 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1750 tmg_cpt++;
1751 msleep(1);
1752 }
1753 if (tmg_cpt >= 3)
1754 tmg_lock = 1;
1755
1756 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1757 goto err;
1758 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1759 goto err;
1760 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1761 goto err;
1762
1763 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1764 goto err;
1765 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1766 goto err;
1767 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1768 goto err;
1769
1770 return tmg_lock;
1771
1772err:
1773 dprintk(FE_ERROR, 1, "I/O error");
1774 return -1;
1775}
1776
1777static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1778{
1779 struct dvb_frontend *fe = &state->frontend;
1780
1781 u32 reg;
1782 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1783 int lock = 0;
1784
1785 if (state->srate >= 10000000)
1786 timeout_lock = timeout_dmd / 3;
1787 else
1788 timeout_lock = timeout_dmd / 2;
1789
1790 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1791 if (!lock) {
1792 if (state->srate >= 10000000) {
1793 if (stv090x_chk_tmg(state)) {
1794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1795 goto err;
1796 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1797 goto err;
1798 lock = stv090x_get_dmdlock(state, timeout_dmd);
1799 } else {
1800 lock = 0;
1801 }
1802 } else {
1803 if (state->srate <= 4000000)
1804 car_step = 1000;
1805 else if (state->srate <= 7000000)
1806 car_step = 2000;
1807 else if (state->srate <= 10000000)
1808 car_step = 3000;
1809 else
1810 car_step = 5000;
1811
1812 steps = (state->search_range / 1000) / car_step;
1813 steps /= 2;
1814 steps = 2 * (steps + 1);
1815 if (steps < 0)
1816 steps = 2;
1817 else if (steps > 12)
1818 steps = 12;
1819
1820 cur_step = 1;
1821 dir = 1;
1822
1823 if (!lock) {
1824 freq = state->frequency;
1825 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1826 while ((cur_step <= steps) && (!lock)) {
1827 if (dir > 0)
1828 freq += cur_step * car_step;
1829 else
1830 freq -= cur_step * car_step;
1831
1832 /* Setup tuner */
1833 stv090x_i2c_gate_ctrl(fe, 1);
1834
1835 if (state->config->tuner_set_frequency)
1836 state->config->tuner_set_frequency(fe, state->frequency);
1837
1838 if (state->config->tuner_set_bandwidth)
1839 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1840
1841 stv090x_i2c_gate_ctrl(fe, 0);
1842
1843 msleep(50);
1844
1845 stv090x_i2c_gate_ctrl(fe, 1);
1846
1847 if (state->config->tuner_get_status)
1848 state->config->tuner_get_status(fe, &reg);
1849
1850 if (reg)
1851 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1852 else
1853 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1854
1855 stv090x_i2c_gate_ctrl(fe, 0);
1856
1857 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1858 if (state->delsys == STV090x_DVBS2) {
1859 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1860 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1861 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1862 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1863 goto err;
1864 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1865 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1866 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1867 goto err;
1868 }
1869 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1870 goto err;
1871 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1872 goto err;
1873 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1874 goto err;
1875 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1876 goto err;
1877 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1878
1879 dir *= -1;
1880 cur_step++;
1881 }
1882 }
1883 }
1884 }
1885
1886 return lock;
1887
1888err:
1889 dprintk(FE_ERROR, 1, "I/O error");
1890 return -1;
1891}
1892
1893static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1894{
1895 s32 timeout, inc, steps_max, srate, car_max;
1896
1897 srate = state->srate;
1898 car_max = state->search_range / 1000;
1899 car_max = 65536 * (car_max / 2);
1900 car_max /= (state->mclk / 1000);
1901
1902 if (car_max > 0x4000)
1903 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1904
1905 inc = srate;
1906 inc /= state->mclk / 1000;
1907 inc *= 256;
1908 inc *= 256;
1909 inc /= 1000;
1910
1911 switch (state->algo) {
1912 case STV090x_SEARCH_DVBS1:
1913 case STV090x_SEARCH_DSS:
1914 inc *= 3; /* freq step = 3% of srate */
1915 timeout = 20;
1916 break;
1917
1918 case STV090x_SEARCH_DVBS2:
1919 inc *= 4;
1920 timeout = 25;
1921 break;
1922
1923 case STV090x_SEARCH_AUTO:
1924 default:
1925 inc *= 3;
1926 timeout = 25;
1927 break;
1928 }
1929 inc /= 100;
1930 if ((inc > car_max) || (inc < 0))
1931 inc = car_max / 2; /* increment <= 1/8 Mclk */
1932
1933 timeout *= 27500; /* 27.5 Msps reference */
1934 if (srate > 0)
1935 timeout /= (srate / 1000);
1936
1937 if ((timeout > 100) || (timeout < 0))
1938 timeout = 100;
1939
1940 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1941 if ((steps_max > 100) || (steps_max < 0)) {
1942 steps_max = 100; /* max steps <= 100 */
1943 inc = car_max / steps_max;
1944 }
1945 *freq_inc = inc;
1946 *timeout_sw = timeout;
1947 *steps = steps_max;
1948
1949 return 0;
1950}
1951
1952static int stv090x_chk_signal(struct stv090x_state *state)
1953{
1954 s32 offst_car, agc2, car_max;
1955 int no_signal;
1956
1957 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
1958 offst_car |= STV090x_READ_DEMOD(state, CFR1);
1959
1960 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1961 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1962 car_max = state->search_range / 1000;
1963
1964 car_max += (car_max / 10); /* 10% margin */
1965 car_max = (65536 * car_max / 2);
1966 car_max /= state->mclk / 1000;
1967
1968 if (car_max > 0x4000)
1969 car_max = 0x4000;
1970
1971 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
1972 no_signal = 1;
1973 dprintk(FE_DEBUG, 1, "No Signal");
1974 } else {
1975 no_signal = 0;
1976 dprintk(FE_DEBUG, 1, "Found Signal");
1977 }
1978
1979 return no_signal;
1980}
1981
1982static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
1983{
1984 int no_signal, lock = 0;
1985 s32 cpt_step, offst_freq, car_max;
1986 u32 reg;
1987
1988 car_max = state->search_range / 1000;
1989 car_max += (car_max / 10);
1990 car_max = (65536 * car_max / 2);
1991 car_max /= (state->mclk / 1000);
1992 if (car_max > 0x4000)
1993 car_max = 0x4000;
1994
1995 if (zigzag)
1996 offst_freq = 0;
1997 else
1998 offst_freq = -car_max + inc;
1999
2000 cpt_step = 0;
2001 do {
2002 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2003 goto err;
2004 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2005 goto err;
2006 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2007 goto err;
2008 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2009 goto err;
2010
2011 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2012 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2013 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2014 goto err;
2015
2016 if (state->dev_ver == 0x12) {
2017 reg = STV090x_READ_DEMOD(state, TSCFGH);
2018 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2019 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2020 goto err;
2021 }
2022
2023 if (zigzag) {
2024 if (offst_freq >= 0)
2025 offst_freq = -offst_freq - 2 * inc;
2026 else
2027 offst_freq = -offst_freq;
2028 } else {
2029 offst_freq += 2 * inc;
2030 }
2031
2032 lock = stv090x_get_dmdlock(state, timeout);
2033 no_signal = stv090x_chk_signal(state);
2034
2035 } while ((!lock) &&
2036 (!no_signal) &&
2037 ((offst_freq - inc) < car_max) &&
2038 ((offst_freq + inc) > -car_max) &&
2039 (cpt_step < steps_max));
2040
2041 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2042 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2043 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2044 goto err;
2045
2046 return lock;
2047err:
2048 dprintk(FE_ERROR, 1, "I/O error");
2049 return -1;
2050}
2051
2052static int stv090x_sw_algo(struct stv090x_state *state)
2053{
2054 int no_signal, zigzag, lock = 0;
2055 u32 reg;
2056
2057 s32 dvbs2_fly_wheel;
2058 s32 inc, timeout_step, trials, steps_max;
2059
2060 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2061
2062 switch (state->algo) {
2063 case STV090x_SEARCH_DVBS1:
2064 case STV090x_SEARCH_DSS:
2065 /* accelerate the frequency detector */
2066 if (state->dev_ver >= 0x20) {
2067 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2068 goto err;
2069 } else {
2070 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2071 goto err;
2072 }
2073 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2074 goto err;
2075 zigzag = 0;
2076 break;
2077
2078 case STV090x_SEARCH_DVBS2:
2079 if (state->dev_ver >= 0x20) {
2080 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2081 goto err;
2082 } else {
2083 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2084 goto err;
2085 }
2086 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2087 goto err;
2088 zigzag = 1;
2089 break;
2090
2091 case STV090x_SEARCH_AUTO:
2092 default:
2093 /* accelerate the frequency detector */
2094 if (state->dev_ver >= 0x20) {
2095 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2096 goto err;
2097 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2098 goto err;
2099 } else {
2100 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2101 goto err;
2102 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2103 goto err;
2104 }
2105 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2106 goto err;
2107 zigzag = 0;
2108 break;
2109 }
2110
2111 trials = 0;
2112 do {
2113 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2114 no_signal = stv090x_chk_signal(state);
2115 trials++;
2116
2117 /*run the SW search 2 times maximum*/
2118 if (lock || no_signal || (trials == 2)) {
2119 /*Check if the demod is not losing lock in DVBS2*/
2120 if (state->dev_ver >= 0x20) {
2121 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2122 goto err;
2123 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2124 goto err;
2125 } else {
2126 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2127 goto err;
2128 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2129 goto err;
2130 }
2131
2132 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2133 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2134 /*Check if the demod is not losing lock in DVBS2*/
2135 msleep(timeout_step);
2136 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2137 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2138 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2139 msleep(timeout_step);
2140 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2141 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2142 }
2143 if (dvbs2_fly_wheel < 0xd) {
2144 /*FALSE lock, The demod is loosing lock */
2145 lock = 0;
2146 if (trials < 2) {
2147 if (state->dev_ver >= 0x20) {
2148 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2149 goto err;
2150 } else {
2151 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2152 goto err;
2153 }
2154 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2155 goto err;
2156 }
2157 }
2158 }
2159 }
2160 } while ((!lock) && (trials < 2) && (!no_signal));
2161
2162 return lock;
2163err:
2164 dprintk(FE_ERROR, 1, "I/O error");
2165 return -1;
2166}
2167
2168static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2169{
2170 u32 reg;
2171 enum stv090x_delsys delsys;
2172
2173 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2174 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2175 delsys = STV090x_DVBS2;
2176 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2177 reg = STV090x_READ_DEMOD(state, FECM);
2178 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2179 delsys = STV090x_DSS;
2180 else
2181 delsys = STV090x_DVBS1;
2182 } else {
2183 delsys = STV090x_ERROR;
2184 }
2185
2186 return delsys;
2187}
2188
2189/* in Hz */
2190static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2191{
2192 s32 derot, int_1, int_2, tmp_1, tmp_2;
2193 u32 pow2;
2194
2195 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2196 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2197 derot |= STV090x_READ_DEMOD(state, CFR0);
2198
2199 derot = comp2(derot, 24);
2200 pow2 = 1 << 12;
2201 int_1 = state->mclk / pow2;
2202 int_2 = derot / pow2;
2203
2204 tmp_1 = state->mclk % pow2;
2205 tmp_2 = derot % pow2;
2206
2207 derot = (int_1 * int_2) +
2208 ((int_1 * tmp_2) / pow2) +
2209 ((int_1 * tmp_1) / pow2);
2210
2211 return derot;
2212}
2213
2214static int stv090x_get_viterbi(struct stv090x_state *state)
2215{
2216 u32 reg, rate;
2217
2218 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2219 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2220
2221 switch (rate) {
2222 case 13:
2223 state->fec = STV090x_PR12;
2224 break;
2225
2226 case 18:
2227 state->fec = STV090x_PR23;
2228 break;
2229
2230 case 21:
2231 state->fec = STV090x_PR34;
2232 break;
2233
2234 case 24:
2235 state->fec = STV090x_PR56;
2236 break;
2237
2238 case 25:
2239 state->fec = STV090x_PR67;
2240 break;
2241
2242 case 26:
2243 state->fec = STV090x_PR78;
2244 break;
2245
2246 default:
2247 state->fec = STV090x_PRERR;
2248 break;
2249 }
2250
2251 return 0;
2252}
2253
2254static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2255{
2256 struct dvb_frontend *fe = &state->frontend;
2257
2258 u8 tmg;
2259 u32 reg;
2260 s32 i = 0, offst_freq;
2261
2262 msleep(5);
2263
2264 if (state->algo == STV090x_BLIND_SEARCH) {
2265 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2266 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2267 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2268 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2269 msleep(5);
2270 i += 5;
2271 }
2272 }
2273 state->delsys = stv090x_get_std(state);
2274
2275 stv090x_i2c_gate_ctrl(fe, 1);
2276
2277 if (state->config->tuner_get_frequency)
2278 state->config->tuner_get_frequency(fe, &state->frequency);
2279
2280 stv090x_i2c_gate_ctrl(fe, 0);
2281
2282 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2283 state->frequency += offst_freq;
2284 stv090x_get_viterbi(state);
2285 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2286 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2287 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2288 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2289 reg = STV090x_READ_DEMOD(state, TMGOBS);
2290 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2291 reg = STV090x_READ_DEMOD(state, FECM);
2292 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2293
2294 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2295
2296 stv090x_i2c_gate_ctrl(fe, 1);
2297
2298 if (state->config->tuner_get_frequency)
2299 state->config->tuner_get_frequency(fe, &state->frequency);
2300
2301 stv090x_i2c_gate_ctrl(fe, 0);
2302
2303 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2304 return STV090x_RANGEOK;
2305 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2306 return STV090x_RANGEOK;
2307 else
2308 return STV090x_OUTOFRANGE; /* Out of Range */
2309 } else {
2310 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2311 return STV090x_RANGEOK;
2312 else
2313 return STV090x_OUTOFRANGE;
2314 }
2315
2316 return STV090x_OUTOFRANGE;
2317}
2318
2319static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2320{
2321 s32 offst_tmg;
2322 s32 pow2;
2323
2324 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2325 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2326 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2327
2328 pow2 = 1 << 24;
2329
2330 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2331 if (!offst_tmg)
2332 offst_tmg = 1;
2333
2334 offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
2335 offst_tmg /= 320;
2336
2337 return offst_tmg;
2338}
2339
2340static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2341{
2342 u8 aclc = 0x29;
2343 s32 i;
2344 struct stv090x_long_frame_crloop *car_loop;
2345
2346 if (state->dev_ver <= 0x12)
2347 car_loop = stv090x_s2_crl;
2348 else if (state->dev_ver == 0x20)
2349 car_loop = stv090x_s2_crl_cut20;
2350 else
2351 car_loop = stv090x_s2_crl;
2352
2353
2354 if (modcod < STV090x_QPSK_12) {
2355 i = 0;
2356 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2357 i++;
2358
2359 if (i >= 3)
2360 i = 2;
2361
2362 } else {
2363 i = 0;
2364 while ((i < 14) && (modcod != car_loop[i].modcod))
2365 i++;
2366
2367 if (i >= 14) {
2368 i = 0;
2369 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2370 i++;
2371
2372 if (i >= 11)
2373 i = 10;
2374 }
2375 }
2376
2377 if (modcod <= STV090x_QPSK_25) {
2378 if (pilots) {
2379 if (state->srate <= 3000000)
2380 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2381 else if (state->srate <= 7000000)
2382 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2383 else if (state->srate <= 15000000)
2384 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2385 else if (state->srate <= 25000000)
2386 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2387 else
2388 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2389 } else {
2390 if (state->srate <= 3000000)
2391 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2392 else if (state->srate <= 7000000)
2393 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2394 else if (state->srate <= 15000000)
2395 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2396 else if (state->srate <= 25000000)
2397 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2398 else
2399 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2400 }
2401
2402 } else if (modcod <= STV090x_8PSK_910) {
2403 if (pilots) {
2404 if (state->srate <= 3000000)
2405 aclc = car_loop[i].crl_pilots_on_2;
2406 else if (state->srate <= 7000000)
2407 aclc = car_loop[i].crl_pilots_on_5;
2408 else if (state->srate <= 15000000)
2409 aclc = car_loop[i].crl_pilots_on_10;
2410 else if (state->srate <= 25000000)
2411 aclc = car_loop[i].crl_pilots_on_20;
2412 else
2413 aclc = car_loop[i].crl_pilots_on_30;
2414 } else {
2415 if (state->srate <= 3000000)
2416 aclc = car_loop[i].crl_pilots_off_2;
2417 else if (state->srate <= 7000000)
2418 aclc = car_loop[i].crl_pilots_off_5;
2419 else if (state->srate <= 15000000)
2420 aclc = car_loop[i].crl_pilots_off_10;
2421 else if (state->srate <= 25000000)
2422 aclc = car_loop[i].crl_pilots_off_20;
2423 else
2424 aclc = car_loop[i].crl_pilots_off_30;
2425 }
2426 } else { /* 16APSK and 32APSK */
2427 if (state->srate <= 3000000)
2428 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2429 else if (state->srate <= 7000000)
2430 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2431 else if (state->srate <= 15000000)
2432 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2433 else if (state->srate <= 25000000)
2434 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2435 else
2436 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2437 }
2438
2439 return aclc;
2440}
2441
2442static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2443{
2444 s32 index = 0;
2445 u8 aclc = 0x0b;
2446
2447 switch (state->modulation) {
2448 case STV090x_QPSK:
2449 default:
2450 index = 0;
2451 break;
2452 case STV090x_8PSK:
2453 index = 1;
2454 break;
2455 case STV090x_16APSK:
2456 index = 2;
2457 break;
2458 case STV090x_32APSK:
2459 index = 3;
2460 break;
2461 }
2462
2463 switch (state->dev_ver) {
2464 case 0x20:
2465 if (state->srate <= 3000000)
2466 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2467 else if (state->srate <= 7000000)
2468 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2469 else if (state->srate <= 15000000)
2470 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2471 else if (state->srate <= 25000000)
2472 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2473 else
2474 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2475 break;
2476
2477 case 0x12:
2478 default:
2479 if (state->srate <= 3000000)
2480 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2481 else if (state->srate <= 7000000)
2482 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2483 else if (state->srate <= 15000000)
2484 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2485 else if (state->srate <= 25000000)
2486 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2487 else
2488 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2489 break;
2490 }
2491
2492 return aclc;
2493}
2494
2495static int stv090x_optimize_track(struct stv090x_state *state)
2496{
2497 struct dvb_frontend *fe = &state->frontend;
2498
2499 enum stv090x_rolloff rolloff;
2500 enum stv090x_modcod modcod;
2501
2502 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2503 u32 reg;
2504
2505 srate = stv090x_get_srate(state, state->mclk);
2506 srate += stv090x_get_tmgoffst(state, srate);
2507
2508 switch (state->delsys) {
2509 case STV090x_DVBS1:
2510 case STV090x_DSS:
2511 if (state->algo == STV090x_SEARCH_AUTO) {
2512 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2513 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2514 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2515 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2516 goto err;
2517 }
2518 reg = STV090x_READ_DEMOD(state, DEMOD);
2519 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2520 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2521 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2522 goto err;
2523 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2524 goto err;
2525 break;
2526
2527 case STV090x_DVBS2:
2528 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2529 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2530 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2531 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2532 goto err;
2533 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2534 goto err;
2535 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2536 goto err;
2537 if (state->frame_len == STV090x_LONG_FRAME) {
2538 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2539 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2540 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2541 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2542 if (modcod <= STV090x_QPSK_910) {
2543 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2544 } else if (modcod <= STV090x_8PSK_910) {
2545 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2546 goto err;
2547 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2548 goto err;
2549 }
2550 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2551 if (modcod <= STV090x_16APSK_910) {
2552 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2553 goto err;
2554 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2555 goto err;
2556 } else {
2557 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2558 goto err;
2559 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2560 goto err;
2561 }
2562 }
2563 } else {
2564 /*Carrier loop setting for short frame*/
2565 aclc = stv090x_optimize_carloop_short(state);
2566 if (state->modulation == STV090x_QPSK) {
2567 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2568 goto err;
2569 } else if (state->modulation == STV090x_8PSK) {
2570 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2571 goto err;
2572 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2573 goto err;
2574 } else if (state->modulation == STV090x_16APSK) {
2575 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2576 goto err;
2577 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2578 goto err;
2579 } else if (state->modulation == STV090x_32APSK) {
2580 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2581 goto err;
2582 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2583 goto err;
2584 }
2585 }
2586 if (state->dev_ver <= 0x11) {
2587 if (state->demod_mode != STV090x_SINGLE)
2588 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2589 }
2590 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2591 break;
2592
2593 case STV090x_UNKNOWN:
2594 default:
2595 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2596 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2597 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2598 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2599 goto err;
2600 break;
2601 }
2602
2603 f_1 = STV090x_READ_DEMOD(state, CFR2);
2604 f_0 = STV090x_READ_DEMOD(state, CFR1);
2605 reg = STV090x_READ_DEMOD(state, TMGOBS);
2606 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2607
2608 if (state->algo == STV090x_BLIND_SEARCH) {
2609 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2610 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2611 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2612 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2613 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2614 goto err;
2615 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2616 goto err;
2617 stv090x_set_srate(state, srate);
2618 stv090x_set_max_srate(state, state->mclk, srate);
2619 stv090x_set_min_srate(state, state->mclk, srate);
2620 blind_tune = 1;
2621 }
2622
2623 if (state->dev_ver >= 0x20) {
2624 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2625 (state->search_mode == STV090x_SEARCH_DSS) ||
2626 (state->search_mode == STV090x_SEARCH_AUTO)) {
2627
2628 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2629 goto err;
2630 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2631 goto err;
2632 }
2633 }
2634
2635 if (state->dev_ver < 0x20) {
2636 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2637 goto err;
2638 }
2639 if (state->dev_ver == 0x10) {
2640 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2641 goto err;
2642 }
2643
2644 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2645 goto err;
2646
2647 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2648
2649 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2650 goto err;
2651 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2652 goto err;
2653 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2654
2655 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2656
2657 if (state->algo != STV090x_WARM_SEARCH) {
2658
2659 stv090x_i2c_gate_ctrl(fe, 1);
2660
2661 if (state->config->tuner_set_bandwidth)
2662 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2663
2664 stv090x_i2c_gate_ctrl(fe, 0);
2665
2666 }
2667 }
2668 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2669 msleep(50); /* blind search: wait 50ms for SR stabilization */
2670 else
2671 msleep(5);
2672
2673 stv090x_get_lock_tmg(state);
2674
2675 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2676 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2677 goto err;
2678 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2679 goto err;
2680 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2681 goto err;
2682 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2683 goto err;
2684
2685 i = 0;
2686
2687 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2688
2689 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2690 goto err;
2691 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2692 goto err;
2693 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2694 goto err;
2695 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2696 goto err;
2697 i++;
2698 }
2699 }
2700
2701 }
2702
2703 if (state->dev_ver >= 0x20) {
2704 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2705 goto err;
2706 }
2707 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2708 stv090x_set_vit_thtracq(state);
2709
2710 return 0;
2711err:
2712 dprintk(FE_ERROR, 1, "I/O error");
2713 return -1;
2714}
2715
2716static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2717{
2718 s32 timer = 0, lock = 0, stat;
2719 u32 reg;
2720
2721 while ((timer < timeout) && (!lock)) {
2722 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2723 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2724
2725 switch (stat) {
2726 case 0: /* searching */
2727 case 1: /* first PLH detected */
2728 default:
2729 lock = 0;
2730 break;
2731
2732 case 2: /* DVB-S2 mode */
2733 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2734 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2735 break;
2736
2737 case 3: /* DVB-S1/legacy mode */
2738 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2739 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2740 break;
2741 }
2742 if (!lock) {
2743 msleep(10);
2744 timer += 10;
2745 }
2746 }
2747 return lock;
2748}
2749
2750static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2751{
2752 u32 reg;
2753 s32 timer = 0;
2754 int lock;
2755
2756 lock = stv090x_get_dmdlock(state, timeout_dmd);
2757 if (lock)
2758 lock = stv090x_get_feclock(state, timeout_fec);
2759
2760 if (lock) {
2761 lock = 0;
2762
2763 while ((timer < timeout_fec) && (!lock)) {
2764 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2765 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2766 msleep(1);
2767 timer++;
2768 }
2769 }
2770
2771 return lock;
2772}
2773
2774static int stv090x_set_s2rolloff(struct stv090x_state *state)
2775{
2776 s32 rolloff;
2777 u32 reg;
2778
2779 if (state->dev_ver == 0x10) {
2780 reg = STV090x_READ_DEMOD(state, DEMOD);
2781 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2782 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2783 goto err;
2784 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2785 reg = STV090x_READ_DEMOD(state, DEMOD);
2786 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2787 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2788 goto err;
2789 } else {
2790 reg = STV090x_READ_DEMOD(state, DEMOD);
2791 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2792 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2793 goto err;
2794 }
2795 return 0;
2796err:
2797 dprintk(FE_ERROR, 1, "I/O error");
2798 return -1;
2799}
2800
2801static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2802{
2803 s32 srate, f_1, f_2;
2804 enum stv090x_signal_state signal_state = STV090x_NODATA;
2805 u32 reg;
2806 int lock;
2807
2808 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2809 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2810 srate = stv090x_get_srate(state, state->mclk);
2811 srate += stv090x_get_tmgoffst(state, state->srate);
2812
2813 if (state->algo == STV090x_BLIND_SEARCH)
2814 stv090x_set_srate(state, state->srate);
2815
2816 stv090x_get_lock_tmg(state);
2817
2818 f_1 = STV090x_READ_DEMOD(state, CFR2);
2819 f_2 = STV090x_READ_DEMOD(state, CFR1);
2820
2821 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2822 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2823 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2824 goto err;
2825
2826 reg = STV090x_READ_DEMOD(state, DEMOD);
2827 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2828 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2829 goto err;
2830 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2831 goto err;
2832 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2833 goto err;
2834 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2835 goto err;
2836 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2837 goto err;
2838
2839 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2840 lock = 1;
2841 stv090x_get_sig_params(state);
2842 stv090x_optimize_track(state);
2843 } else {
2844 reg = STV090x_READ_DEMOD(state, DEMOD);
2845 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2846 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2847 goto err;
2848 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2849 goto err;
2850 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2851 goto err;
2852 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2853 goto err;
2854 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2855 goto err;
2856 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2857 lock = 1;
2858 signal_state = stv090x_get_sig_params(state);
2859 stv090x_optimize_track(state);
2860 }
2861 }
2862 } else {
2863 lock = 0;
2864 }
2865
2866 return signal_state;
2867
2868err:
2869 dprintk(FE_ERROR, 1, "I/O error");
2870 return -1;
2871}
2872
2873static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2874{
2875 struct dvb_frontend *fe = &state->frontend;
2876 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2877 u32 reg;
2878 s32 timeout_dmd = 500, timeout_fec = 50;
2879 int lock = 0, low_sr, no_signal = 0;
2880
2881 reg = STV090x_READ_DEMOD(state, TSCFGH);
2882 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2883 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2884 goto err;
2885
2886 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2887 goto err;
2888
2889 if (state->dev_ver >= 0x20) {
2890 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2891 goto err;
2892 } else {
2893 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2894 goto err;
2895 }
2896
2897 stv090x_get_lock_tmg(state);
2898
2899 if (state->algo == STV090x_BLIND_SEARCH) {
2900 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2901 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2902 goto err;
2903 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2904 } else {
2905 /* known srate */
2906 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2907 goto err;
2908 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2909 goto err;
2910
2911 if (state->srate >= 10000000) {
2912 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2913 goto err;
2914 } else {
2915 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2916 goto err;
2917 }
2918
2919 if (state->dev_ver >= 0x20) {
2920 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2921 goto err;
2922 if (state->algo == STV090x_COLD_SEARCH)
2923 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
2924 else if (state->algo == STV090x_WARM_SEARCH)
2925 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2926 } else {
2927 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2928 goto err;
2929 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2930 }
2931 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2932 goto err;
2933 stv090x_set_srate(state, state->srate);
2934 stv090x_set_max_srate(state, state->mclk, state->srate);
2935 stv090x_set_min_srate(state, state->mclk, state->srate);
2936
2937 if (state->srate >= 10000000)
2938 low_sr = 1;
2939 }
2940
2941 /* Setup tuner */
2942 stv090x_i2c_gate_ctrl(fe, 1);
2943
2944 if (state->config->tuner_set_bbgain)
2945 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2946
2947 if (state->config->tuner_set_frequency)
2948 state->config->tuner_set_frequency(fe, state->frequency);
2949
2950 if (state->config->tuner_set_bandwidth)
2951 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2952
2953 stv090x_i2c_gate_ctrl(fe, 0);
2954
2955 msleep(50);
2956
2957 stv090x_i2c_gate_ctrl(fe, 1);
2958
2959 if (state->config->tuner_get_status)
2960 state->config->tuner_get_status(fe, &reg);
2961
2962 if (reg)
2963 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2964 else
2965 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2966
2967 stv090x_i2c_gate_ctrl(fe, 0);
2968
2969 reg = STV090x_READ_DEMOD(state, DEMOD);
2970 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
2971 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
2972 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2973 goto err;
2974 stv090x_delivery_search(state);
2975 if (state->algo == STV090x_BLIND_SEARCH)
2976 stv090x_start_search(state);
2977
2978 if (state->dev_ver == 0x12) {
2979 reg = STV090x_READ_DEMOD(state, TSCFGH);
2980 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2981 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2982 goto err;
2983 msleep(3);
2984 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
2985 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2986 goto err;
2987 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2988 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2989 goto err;
2990 }
2991
2992 if (state->algo == STV090x_BLIND_SEARCH)
2993 lock = stv090x_blind_search(state);
2994 else if (state->algo == STV090x_COLD_SEARCH)
2995 lock = stv090x_get_coldlock(state, timeout_dmd);
2996 else if (state->algo == STV090x_WARM_SEARCH)
2997 lock = stv090x_get_dmdlock(state, timeout_dmd);
2998
2999 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3000 if (!low_sr) {
3001 if (stv090x_chk_tmg(state))
3002 lock = stv090x_sw_algo(state);
3003 }
3004 }
3005
3006 if (lock)
3007 signal_state = stv090x_get_sig_params(state);
3008
3009 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3010 stv090x_optimize_track(state);
3011 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3012 if (stv090x_get_std(state) == STV090x_DVBS1) {
3013 msleep(20);
3014 reg = STV090x_READ_DEMOD(state, TSCFGH);
3015 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3016 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3017 goto err;
3018 } else {
3019 reg = STV090x_READ_DEMOD(state, TSCFGH);
3020 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3021 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3022 goto err;
3023 msleep(3);
3024 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3025 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3026 goto err;
3027 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3028 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3029 goto err;
3030 }
3031 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3032 reg = STV090x_READ_DEMOD(state, TSCFGH);
3033 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3034 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3035 goto err;
3036 msleep(3);
3037 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3038 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3039 goto err;
3040
3041 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3042 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3043 goto err;
3044 }
3045
3046 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3047 lock = 1;
3048 if (state->delsys == STV090x_DVBS2) {
3049 stv090x_set_s2rolloff(state);
3050 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3051 goto err;
3052 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3053 goto err;
3054 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3055 goto err;
3056 } else {
3057 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3058 goto err;
3059 }
3060 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3061 goto err;
3062 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3063 goto err;
3064 } else {
3065 lock = 0;
3066 signal_state = STV090x_NODATA;
3067 no_signal = stv090x_chk_signal(state);
3068 }
3069 }
3070 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3071 if (state->dev_ver <= 0x11) {
3072 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3073 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3074 signal_state = stv090x_acq_fixs1(state);
3075 }
3076 }
3077 return signal_state;
3078
3079err:
3080 dprintk(FE_ERROR, 1, "I/O error");
3081 return -1;
3082}
3083
3084static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3085{
3086 struct stv090x_state *state = fe->demodulator_priv;
3087 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3088
3089 state->delsys = props->delivery_system;
3090 state->frequency = p->frequency;
3091 state->srate = p->u.qpsk.symbol_rate;
3092
3093 if (!stv090x_algo(state)) {
3094 dprintk(FE_DEBUG, 1, "Search success!");
3095 return DVBFE_ALGO_SEARCH_SUCCESS;
3096 } else {
3097 dprintk(FE_DEBUG, 1, "Search failed!");
3098 return DVBFE_ALGO_SEARCH_FAILED;
3099 }
3100
3101 return DVBFE_ALGO_SEARCH_ERROR;
3102}
3103
3104/* FIXME! */
3105static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3106{
3107 struct stv090x_state *state = fe->demodulator_priv;
3108 u32 reg;
3109 u8 search_state;
3110 int locked = 0;
3111
3112 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3113 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3114
3115 switch (search_state) {
3116 case 0: /* searching */
3117 case 1: /* first PLH detected */
3118 default:
3119 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3120 locked = 0;
3121 break;
3122
3123 case 2: /* DVB-S2 mode */
3124 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3125 reg = STV090x_READ_DEMOD(state, DSTATUS);
3126 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3127 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3128 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3129 locked = 1;
3130 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3131 }
3132 }
3133 break;
3134
3135 case 3: /* DVB-S1/legacy mode */
3136 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3137 reg = STV090x_READ_DEMOD(state, DSTATUS);
3138 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3139 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3140 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3141 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3142 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3143 locked = 1;
3144 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3145 }
3146 }
3147 }
3148 break;
3149 }
3150
3151 return locked;
3152}
3153
3154static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3155{
3156 struct stv090x_state *state = fe->demodulator_priv;
3157
3158 s32 count_4, count_3, count_2, count_1, count_0, count;
3159 u32 reg, h, m, l;
3160 enum fe_status status;
3161
3162 if (!stv090x_read_status(fe, &status)) {
3163 *per = 1 << 23; /* Max PER */
3164 } else {
3165 /* Counter 2 */
3166 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3167 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3168
3169 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3170 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3171
3172 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3173 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3174
3175 *per = ((h << 16) | (m << 8) | l);
3176
3177 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3178 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3179 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3180 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3181 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3182
3183 if ((!count_4) && (!count_3)) {
3184 count = (count_2 & 0xff) << 16;
3185 count |= (count_1 & 0xff) << 8;
3186 count |= count_0 & 0xff;
3187 } else {
3188 count = 1 << 24;
3189 }
3190 if (count == 0)
3191 *per = 1;
3192 }
3193 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3194 goto err;
3195 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3196 goto err;
3197
3198 return 0;
3199err:
3200 dprintk(FE_ERROR, 1, "I/O error");
3201 return -1;
3202}
3203
3204static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3205{
3206 int res = 0;
3207 int min = 0, med;
3208
3209 if (val < tab[min].read)
3210 res = tab[min].real;
3211 else if (val >= tab[max].read)
3212 res = tab[max].real;
3213 else {
3214 while ((max - min) > 1) {
3215 med = (max + min) / 2;
3216 if (val >= tab[min].read && val < tab[med].read)
3217 max = med;
3218 else
3219 min = med;
3220 }
3221 res = ((val - tab[min].read) *
3222 (tab[max].real - tab[min].real) /
3223 (tab[max].read - tab[min].read)) +
3224 tab[min].real;
3225 }
3226
3227 return res;
3228}
3229
3230static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3231{
3232 struct stv090x_state *state = fe->demodulator_priv;
3233 u32 reg;
3234 s32 agc;
3235
3236 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3237 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3238
3239 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3240 if (agc > stv090x_rf_tab[0].read)
3241 *strength = 5;
3242 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3243 *strength = -100;
3244
3245 return 0;
3246}
3247
3248static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3249{
3250 struct stv090x_state *state = fe->demodulator_priv;
3251 u32 reg_0, reg_1, reg, i;
3252 s32 val_0, val_1, val = 0;
3253 u8 lock_f;
3254
3255 switch (state->delsys) {
3256 case STV090x_DVBS2:
3257 reg = STV090x_READ_DEMOD(state, DSTATUS);
3258 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3259 if (lock_f) {
3260 msleep(5);
3261 for (i = 0; i < 16; i++) {
3262 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3263 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3264 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3265 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3266 val += MAKEWORD16(val_1, val_0);
3267 msleep(1);
3268 }
3269 val /= 16;
3270 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3271 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3272 *cnr = 1000;
3273 }
3274 break;
3275
3276 case STV090x_DVBS1:
3277 case STV090x_DSS:
3278 reg = STV090x_READ_DEMOD(state, DSTATUS);
3279 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3280 if (lock_f) {
3281 msleep(5);
3282 for (i = 0; i < 16; i++) {
3283 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3284 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3285 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3286 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3287 val += MAKEWORD16(val_1, val_0);
3288 msleep(1);
3289 }
3290 val /= 16;
3291 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3292 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3293 *cnr = 1000;
3294 }
3295 break;
3296 default:
3297 break;
3298 }
3299
3300 return 0;
3301}
3302
3303static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3304{
3305 struct stv090x_state *state = fe->demodulator_priv;
3306 u32 reg;
3307
3308 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3309 switch (tone) {
3310 case SEC_TONE_ON:
3311 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3312 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3313 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3314 goto err;
3315 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3316 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3317 goto err;
3318 break;
3319
3320 case SEC_TONE_OFF:
3321 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3322 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3323 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3324 goto err;
3325 break;
3326 default:
3327 return -EINVAL;
3328 }
3329
3330 return 0;
3331err:
3332 dprintk(FE_ERROR, 1, "I/O error");
3333 return -1;
3334}
3335
3336
3337static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3338{
3339 return DVBFE_ALGO_CUSTOM;
3340}
3341
3342static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3343{
3344 struct stv090x_state *state = fe->demodulator_priv;
3345 u32 reg, idle = 0, fifo_full = 1;
3346 int i;
3347
3348 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3349 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3350 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3351 goto err;
3352
3353 for (i = 0; i < cmd->msg_len; i++) {
3354
3355 while (fifo_full) {
3356 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3357 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3358 }
3359
3360 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3361 goto err;
3362 i++;
3363 }
3364 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3365 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3366 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3367 goto err;
3368
3369 i = 0;
3370
3371 while ((!idle) && (i < 10)) {
3372 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3373 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3374 msleep(10);
3375 i++;
3376 }
3377
3378 return 0;
3379err:
3380 dprintk(FE_ERROR, 1, "I/O error");
3381 return -1;
3382}
3383
3384static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3385{
3386 struct stv090x_state *state = fe->demodulator_priv;
3387 u32 reg = 0, i = 0, rx_end = 0;
3388
3389 while ((rx_end != 1) && (i < 10)) {
3390 msleep(10);
3391 i++;
3392 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3393 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3394 }
3395
3396 if (rx_end) {
3397 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3398 for (i = 0; i < reply->msg_len; i++)
3399 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3400 }
3401
3402 return 0;
3403}
3404
3405static int stv090x_sleep(struct dvb_frontend *fe)
3406{
3407 struct stv090x_state *state = fe->demodulator_priv;
3408 u32 reg;
3409
3410 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3411 state->device == STV0900 ? "STV0900" : "STV0903");
3412
3413 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3414 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3415 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3416 goto err;
3417
3418 return 0;
3419err:
3420 dprintk(FE_ERROR, 1, "I/O error");
3421 return -1;
3422}
3423
3424static int stv090x_wakeup(struct dvb_frontend *fe)
3425{
3426 struct stv090x_state *state = fe->demodulator_priv;
3427 u32 reg;
3428
3429 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3430 state->device == STV0900 ? "STV0900" : "STV0903");
3431
3432 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3433 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3434 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3435 goto err;
3436
3437 return 0;
3438err:
3439 dprintk(FE_ERROR, 1, "I/O error");
3440 return -1;
3441}
3442
3443static void stv090x_release(struct dvb_frontend *fe)
3444{
3445 struct stv090x_state *state = fe->demodulator_priv;
3446
3447 kfree(state);
3448}
3449
3450static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3451{
3452 u32 reg;
3453
3454 switch (ldpc_mode) {
3455 case STV090x_DUAL:
3456 default:
3457 reg = stv090x_read_reg(state, STV090x_GENCFG);
3458 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3459 /* follow LDPC default state */
3460 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3461 goto err;
3462 state->demod_mode = STV090x_DUAL;
3463 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3464 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3465 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3466 goto err;
3467 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3468 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3469 goto err;
3470 }
3471 break;
3472
3473 case STV090x_SINGLE:
3474 if (state->demod == STV090x_DEMODULATOR_1) {
3475 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3476 goto err;
3477 } else {
3478 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3479 goto err;
3480 }
3481
3482 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3483 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3484 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3485 goto err;
3486 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3487 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3488 goto err;
3489
3490 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3491 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3492 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3493 goto err;
3494 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3495 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3496 goto err;
3497 break;
3498 }
3499
3500 return 0;
3501err:
3502 dprintk(FE_ERROR, 1, "I/O error");
3503 return -1;
3504}
3505
3506/* return (Hz), clk in Hz*/
3507static u32 stv090x_get_mclk(struct stv090x_state *state)
3508{
3509 const struct stv090x_config *config = state->config;
3510 u32 div, reg;
3511 u8 ratio;
3512
3513 div = stv090x_read_reg(state, STV090x_NCOARSE);
3514 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3515 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3516
3517 return (div + 1) * config->xtal / ratio; /* kHz */
3518}
3519
3520static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3521{
3522 const struct stv090x_config *config = state->config;
3523 u32 reg, div, clk_sel;
3524
3525 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3526 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3527
3528 div = ((clk_sel * mclk) / config->xtal) - 1;
3529
3530 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3531 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3532 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3533 goto err;
3534
3535 state->mclk = stv090x_get_mclk(state);
3536
3537 return 0;
3538err:
3539 dprintk(FE_ERROR, 1, "I/O error");
3540 return -1;
3541}
3542
3543static int stv090x_set_tspath(struct stv090x_state *state)
3544{
3545 u32 reg;
3546
3547 if (state->dev_ver >= 0x20) {
3548 switch (state->config->ts1_mode) {
3549 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3550 case STV090x_TSMODE_DVBCI:
3551 switch (state->config->ts2_mode) {
3552 case STV090x_TSMODE_SERIAL_PUNCTURED:
3553 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3554 default:
3555 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3556 break;
3557
3558 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3559 case STV090x_TSMODE_DVBCI:
3560 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3561 goto err;
3562 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3563 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3564 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3565 goto err;
3566 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3567 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3568 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3569 goto err;
3570 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3571 goto err;
3572 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3573 goto err;
3574 break;
3575 }
3576 break;
3577
3578 case STV090x_TSMODE_SERIAL_PUNCTURED:
3579 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3580 default:
3581 switch (state->config->ts2_mode) {
3582 case STV090x_TSMODE_SERIAL_PUNCTURED:
3583 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3584 default:
3585 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3586 goto err;
3587 break;
3588
3589 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3590 case STV090x_TSMODE_DVBCI:
3591 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3592 goto err;
3593 break;
3594 }
3595 break;
3596 }
3597 } else {
3598 switch (state->config->ts1_mode) {
3599 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3600 case STV090x_TSMODE_DVBCI:
3601 switch (state->config->ts2_mode) {
3602 case STV090x_TSMODE_SERIAL_PUNCTURED:
3603 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3604 default:
3605 break;
3606
3607 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3608 case STV090x_TSMODE_DVBCI:
3609 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3610 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3611 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3612 goto err;
3613 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3614 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3615 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3616 goto err;
3617 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3618 goto err;
3619 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3620 goto err;
3621 break;
3622 }
3623 break;
3624
3625 case STV090x_TSMODE_SERIAL_PUNCTURED:
3626 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3627 default:
3628 switch (state->config->ts2_mode) {
3629 case STV090x_TSMODE_SERIAL_PUNCTURED:
3630 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3631 default:
3632 break;
3633
3634 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3635 case STV090x_TSMODE_DVBCI:
3636 break;
3637 }
3638 break;
3639 }
3640 }
3641
3642 switch (state->config->ts1_mode) {
3643 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3644 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3645 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3646 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3647 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3648 goto err;
3649 break;
3650
3651 case STV090x_TSMODE_DVBCI:
3652 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3653 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3654 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3655 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3656 goto err;
3657 break;
3658
3659 case STV090x_TSMODE_SERIAL_PUNCTURED:
3660 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3661 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3662 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3663 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3664 goto err;
3665 break;
3666
3667 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3668 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3669 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3670 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3671 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3672 goto err;
3673 break;
3674
3675 default:
3676 break;
3677 }
3678
3679 switch (state->config->ts2_mode) {
3680 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3681 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3682 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3683 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3684 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3685 goto err;
3686 break;
3687
3688 case STV090x_TSMODE_DVBCI:
3689 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3690 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3691 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3692 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3693 goto err;
3694 break;
3695
3696 case STV090x_TSMODE_SERIAL_PUNCTURED:
3697 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3698 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3699 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3700 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3701 goto err;
3702 break;
3703
3704 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3705 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3706 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3707 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3708 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3709 goto err;
3710 break;
3711
3712 default:
3713 break;
3714 }
3715 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3716 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3717 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3718 goto err;
3719 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3720 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3721 goto err;
3722
3723 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3724 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3725 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3726 goto err;
3727 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3728 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3729 goto err;
3730
3731 return 0;
3732err:
3733 dprintk(FE_ERROR, 1, "I/O error");
3734 return -1;
3735}
3736
3737static int stv090x_init(struct dvb_frontend *fe)
3738{
3739 struct stv090x_state *state = fe->demodulator_priv;
3740 const struct stv090x_config *config = state->config;
3741 u32 reg;
3742
3743 stv090x_ldpc_mode(state, state->demod_mode);
3744
3745 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3746 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3747 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3748 goto err;
3749 reg = STV090x_READ_DEMOD(state, DEMOD);
3750 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3751 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3752 goto err;
3753
3754 stv090x_i2c_gate_ctrl(fe, 1);
3755
3756 if (config->tuner_init)
3757 config->tuner_init(fe);
3758
3759 stv090x_i2c_gate_ctrl(fe, 0);
3760
3761 stv090x_set_tspath(state);
3762
3763 return 0;
3764err:
3765 dprintk(FE_ERROR, 1, "I/O error");
3766 return -1;
3767}
3768
3769static int stv090x_setup(struct dvb_frontend *fe)
3770{
3771 struct stv090x_state *state = fe->demodulator_priv;
3772 const struct stv090x_config *config = state->config;
3773 const struct stv090x_reg *stv090x_initval = NULL;
3774 const struct stv090x_reg *stv090x_cut20_val = NULL;
3775 unsigned long t1_size = 0, t2_size = 0;
3776
3777 int i;
3778
3779 if (state->device == STV0900) {
3780 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3781 stv090x_initval = stv0900_initval;
3782 t1_size = ARRAY_SIZE(stv0900_initval);
3783 stv090x_cut20_val = stv0900_cut20_val;
3784 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3785 } else if (state->device == STV0903) {
3786 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3787 stv090x_initval = stv0903_initval;
3788 t1_size = ARRAY_SIZE(stv0903_initval);
3789 stv090x_cut20_val = stv0903_cut20_val;
3790 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3791 }
3792
3793 /* STV090x init */
3794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3795 goto err;
3796
3797 msleep(5);
3798
3799 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3800 goto err;
3801
3802 if (STV090x_WRITE_DEMOD(state, I2CRPT, 0x00) < 0) /* repeater OFF */
3803 goto err;
3804
3805 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3806 goto err;
3807 msleep(5);
3808 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3809 goto err;
3810 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3811 goto err;
3812 msleep(5);
3813
3814 /* write initval */
3815 for (i = 0; i < t1_size; i++) {
3816 dprintk(FE_DEBUG, 1, "Setting up initial values");
3817 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3818 goto err;
3819 }
3820
3821 if (state->dev_ver >= 0x20) {
3822 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3823 goto err;
3824
3825 /* write cut20_val*/
3826 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3827 for (i = 0; i < t2_size; i++) {
3828 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3829 goto err;
3830 }
3831 }
3832
3833 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3834 goto err;
3835 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3836 goto err;
3837
3838 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3839 msleep(5);
3840 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3841 goto err;
3842 stv090x_get_mclk(state);
3843
3844 return 0;
3845err:
3846 dprintk(FE_ERROR, 1, "I/O error");
3847 return -1;
3848}
3849
3850static struct dvb_frontend_ops stv090x_ops = {
3851
3852 .info = {
3853 .name = "STV090x Multistandard",
3854 },
3855
3856 .release = stv090x_release,
3857 .init = stv090x_init,
3858
3859 .sleep = stv090x_sleep,
3860 .get_frontend_algo = stv090x_frontend_algo,
3861
3862 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
3863
3864 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
3865 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
3866 .set_tone = stv090x_set_tone,
3867
3868 .search = stv090x_search,
3869 .read_status = stv090x_read_status,
3870 .read_ber = stv090x_read_per,
3871 .read_signal_strength = stv090x_read_signal_strength,
3872 .read_snr = stv090x_read_cnr
3873};
3874
3875
3876struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
3877 struct i2c_adapter *i2c,
3878 enum stv090x_demodulator demod)
3879{
3880 struct stv090x_state *state = NULL;
3881
3882 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
3883 if (state == NULL)
3884 goto error;
3885
3886 state->verbose = &verbose;
3887 state->config = config;
3888 state->i2c = i2c;
3889 state->frontend.ops = stv090x_ops;
3890 state->frontend.demodulator_priv = state;
3891 state->demod_mode = config->demod_mode; /* Single or Dual mode */
3892 state->device = config->device;
3893 state->rolloff = 35; /* default */
3894
3895 if (state->demod == STV090x_DEMODULATOR_0)
3896 mutex_init(&demod_lock);
3897
3898 if (stv090x_sleep(&state->frontend) < 0) {
3899 dprintk(FE_ERROR, 1, "Error putting device to sleep");
3900 goto error;
3901 }
3902
3903 if (stv090x_setup(&state->frontend) < 0) {
3904 dprintk(FE_ERROR, 1, "Error setting up device");
3905 goto error;
3906 }
3907 if (stv090x_wakeup(&state->frontend) < 0) {
3908 dprintk(FE_ERROR, 1, "Error waking device");
3909 goto error;
3910 }
3911 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
3912
3913 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
3914 state->device == STV0900 ? "STV0900" : "STV0903",
3915 demod,
3916 state->dev_ver);
3917
3918 return &state->frontend;
3919
3920error:
3921 kfree(state);
3922 return NULL;
3923}
3924EXPORT_SYMBOL(stv090x_attach);
3925MODULE_PARM_DESC(verbose, "Set Verbosity level");
3926MODULE_AUTHOR("Manu Abraham");
3927MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
3928MODULE_LICENSE("GPL");