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gerrit-public.fairphone.software / kernel / msm-4.9 / e443b333629f82ca0da91a05ca638050943bbedd / . / drivers / usb / chipidea / ci.h
blob: f5b3b8538a3b7292d2d3591aff976df03fad8cc9 [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +0300[diff] [blame^]1/*
2 * ci.h - common structures, functions, and macros of the ChipIdea driver
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14#define __DRIVERS_USB_CHIPIDEA_CI_H
15
16#include <linux/list.h>
17#include <linux/usb/gadget.h>
18
19/******************************************************************************
20 * DEFINE
21 *****************************************************************************/
22#define DMA_ADDR_INVALID (~(dma_addr_t)0)
23#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
24#define ENDPT_MAX 32
25
26/******************************************************************************
27 * STRUCTURES
28 *****************************************************************************/
29/* Extension of usb_ep */
30struct ci13xxx_ep {
31 struct usb_ep ep;
32 u8 dir;
33 u8 num;
34 u8 type;
35 char name[16];
36 struct {
37 struct list_head queue;
38 struct ci13xxx_qh *ptr;
39 dma_addr_t dma;
40 } qh;
41 int wedge;
42
43 /* global resources */
44 struct ci13xxx *udc;
45 spinlock_t *lock;
46 struct device *device;
47 struct dma_pool *td_pool;
48};
49
50struct hw_bank {
51 unsigned lpm; /* is LPM? */
52 void __iomem *abs; /* bus map offset */
53 void __iomem *cap; /* bus map offset + CAP offset */
54 void __iomem *op; /* bus map offset + OP offset */
55 size_t size; /* bank size */
56 void __iomem **regmap;
57};
58
59/* CI13XXX UDC descriptor & global resources */
60struct ci13xxx {
61 spinlock_t lock; /* ctrl register bank access */
62 void __iomem *regs; /* registers address space */
63
64 struct dma_pool *qh_pool; /* DMA pool for queue heads */
65 struct dma_pool *td_pool; /* DMA pool for transfer descs */
66 struct usb_request *status; /* ep0 status request */
67
68 struct device *dev;
69 struct usb_gadget gadget; /* USB slave device */
70 struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
71 u32 ep0_dir; /* ep0 direction */
72 struct ci13xxx_ep *ep0out, *ep0in;
73 unsigned hw_ep_max; /* number of hw endpoints */
74
75 bool setaddr;
76 u8 address;
77 u8 remote_wakeup; /* Is remote wakeup feature
78 enabled by the host? */
79 u8 suspended; /* suspended by the host */
80 u8 test_mode; /* the selected test mode */
81
82 struct hw_bank hw_bank;
83 int irq;
84 struct usb_gadget_driver *driver; /* 3rd party gadget driver */
85 struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
86 int vbus_active; /* is VBUS active */
87 struct usb_phy *transceiver; /* Transceiver struct */
88};
89
90/******************************************************************************
91 * REGISTERS
92 *****************************************************************************/
93/* register size */
94#define REG_BITS (32)
95
96/* register indices */
97enum ci13xxx_regs {
98 CAP_CAPLENGTH,
99 CAP_HCCPARAMS,
100 CAP_DCCPARAMS,
101 CAP_TESTMODE,
102 CAP_LAST = CAP_TESTMODE,
103 OP_USBCMD,
104 OP_USBSTS,
105 OP_USBINTR,
106 OP_DEVICEADDR,
107 OP_ENDPTLISTADDR,
108 OP_PORTSC,
109 OP_DEVLC,
110 OP_USBMODE,
111 OP_ENDPTSETUPSTAT,
112 OP_ENDPTPRIME,
113 OP_ENDPTFLUSH,
114 OP_ENDPTSTAT,
115 OP_ENDPTCOMPLETE,
116 OP_ENDPTCTRL,
117 /* endptctrl1..15 follow */
118 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
119};
120
121
122/**
123 * ffs_nr: find first (least significant) bit set
124 * @x: the word to search
125 *
126 * This function returns bit number (instead of position)
127 */
128static inline int ffs_nr(u32 x)
129{
130 int n = ffs(x);
131
132 return n ? n-1 : 32;
133}
134
135/**
136 * hw_read: reads from a hw register
137 * @reg: register index
138 * @mask: bitfield mask
139 *
140 * This function returns register contents
141 */
142static inline u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
143{
144 return ioread32(udc->hw_bank.regmap[reg]) & mask;
145}
146
147/**
148 * hw_write: writes to a hw register
149 * @reg: register index
150 * @mask: bitfield mask
151 * @data: new value
152 */
153static inline void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
154 u32 mask, u32 data)
155{
156 if (~mask)
157 data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
158 | (data & mask);
159
160 iowrite32(data, udc->hw_bank.regmap[reg]);
161}
162
163/**
164 * hw_test_and_clear: tests & clears a hw register
165 * @reg: register index
166 * @mask: bitfield mask
167 *
168 * This function returns register contents
169 */
170static inline u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
171 u32 mask)
172{
173 u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
174
175 iowrite32(val, udc->hw_bank.regmap[reg]);
176 return val;
177}
178
179/**
180 * hw_test_and_write: tests & writes a hw register
181 * @reg: register index
182 * @mask: bitfield mask
183 * @data: new value
184 *
185 * This function returns register contents
186 */
187static inline u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
188 u32 mask, u32 data)
189{
190 u32 val = hw_read(udc, reg, ~0);
191
192 hw_write(udc, reg, mask, data);
193 return (val & mask) >> ffs_nr(mask);
194}
195
196int hw_device_init(struct ci13xxx *udc, void __iomem *base,
197 uintptr_t cap_offset);
198int hw_device_reset(struct ci13xxx *ci);
199
200int hw_port_test_set(struct ci13xxx *ci, u8 mode);
201
202u8 hw_port_test_get(struct ci13xxx *ci);
203
204#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */