Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 1 | * CoreSight Components: |
| 2 | |
| 3 | CoreSight components are compliant with the ARM CoreSight architecture |
| 4 | specification and can be connected in various topologies to suit a particular |
| 5 | SoCs tracing needs. These trace components can generally be classified as |
| 6 | sinks, links and sources. Trace data produced by one or more sources flows |
| 7 | through the intermediate links connecting the source to the currently selected |
| 8 | sink. Each CoreSight component device should use these properties to describe |
| 9 | its hardware characteristcs. |
| 10 | |
| 11 | * Required properties for all components *except* non-configurable replicators: |
| 12 | |
| 13 | * compatible: These have to be supplemented with "arm,primecell" as |
| 14 | drivers are using the AMBA bus interface. Possible values include: |
mathieu.poirier@linaro.org | 4b681ef | 2016-06-22 09:01:03 -0600 | [diff] [blame] | 15 | - Embedded Trace Buffer (version 1.0): |
| 16 | "arm,coresight-etb10", "arm,primecell"; |
| 17 | |
| 18 | - Trace Port Interface Unit: |
| 19 | "arm,coresight-tpiu", "arm,primecell"; |
| 20 | |
| 21 | - Trace Memory Controller, used for Embedded Trace Buffer(ETB), |
| 22 | Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) |
| 23 | configuration. The configuration mode (ETB, ETF, ETR) is |
| 24 | discovered at boot time when the device is probed. |
| 25 | "arm,coresight-tmc", "arm,primecell"; |
| 26 | |
| 27 | - Trace Funnel: |
| 28 | "arm,coresight-funnel", "arm,primecell"; |
| 29 | |
| 30 | - Embedded Trace Macrocell (version 3.x) and |
| 31 | Program Flow Trace Macrocell: |
| 32 | "arm,coresight-etm3x", "arm,primecell"; |
| 33 | |
| 34 | - Embedded Trace Macrocell (version 4.x): |
| 35 | "arm,coresight-etm4x", "arm,primecell"; |
| 36 | |
| 37 | - Qualcomm Configurable Replicator (version 1.x): |
| 38 | "qcom,coresight-replicator1x", "arm,primecell"; |
| 39 | |
| 40 | - System Trace Macrocell: |
| 41 | "arm,coresight-stm", "arm,primecell"; [1] |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 42 | |
| 43 | * reg: physical base address and length of the register |
| 44 | set(s) of the component. |
| 45 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 46 | * clocks: the clocks associated to this component. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 47 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 48 | * clock-names: the name of the clocks referenced by the code. |
| 49 | Since we are using the AMBA framework, the name of the clock |
| 50 | providing the interconnect should be "apb_pclk", and some |
| 51 | coresight blocks also have an additional clock "atclk", which |
| 52 | clocks the core of that coresight component. The latter clock |
| 53 | is optional. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 54 | |
| 55 | * port or ports: The representation of the component's port |
| 56 | layout using the generic DT graph presentation found in |
| 57 | "bindings/graph.txt". |
| 58 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 59 | * coresight-name: unique descriptive name of the component. |
| 60 | |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 61 | * Additional required properties for System Trace Macrocells (STM): |
| 62 | * reg: along with the physical base address and length of the register |
| 63 | set as described above, another entry is required to describe the |
| 64 | mapping of the extended stimulus port area. |
| 65 | |
| 66 | * reg-names: the only acceptable values are "stm-base" and |
| 67 | "stm-stimulus-base", each corresponding to the areas defined in "reg". |
| 68 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 69 | * Required properties for devices that don't show up on the AMBA bus, such as |
| 70 | non-configurable replicators: |
| 71 | |
| 72 | * compatible: Currently supported value is (note the absence of the |
| 73 | AMBA markee): |
| 74 | - "arm,coresight-replicator" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 75 | - "qcom,coresight-csr" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 76 | - "qcom,coresight-remote-etm" |
| 77 | - "qcom,coresight-hwevent" |
| 78 | - "qcom,coresight-dummy" |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 79 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 80 | * port or ports: same as above. |
| 81 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 82 | * coresight-name: unique descriptive name of the component. |
| 83 | |
Satyajit Desai | 80e47d4 | 2017-03-06 18:23:52 -0800 | [diff] [blame] | 84 | * Additional required property for coresight-dummy devices: |
| 85 | * qcom,dummy-source: Configure the device as source. |
| 86 | |
Satyajit Desai | f4c5ee9 | 2017-01-04 15:31:06 -0800 | [diff] [blame] | 87 | * qcom,dummy-sink: Configure the device as sink. |
| 88 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 89 | * Optional properties for all components: |
| 90 | * reg-names: names corresponding to each reg property value. |
| 91 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 92 | * Optional properties for ETM/PTMs: |
| 93 | |
| 94 | * arm,cp14: must be present if the system accesses ETM/PTM management |
| 95 | registers via co-processor 14. |
| 96 | |
| 97 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the |
| 98 | source is considered to belong to CPU0. |
| 99 | |
| 100 | * Optional property for TMC: |
| 101 | |
| 102 | * arm,buffer-size: size of contiguous buffer space for TMC ETR |
| 103 | (embedded trace router) |
| 104 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 105 | * arm,default-sink: represents the default compile time CoreSight sink |
| 106 | |
| 107 | * coresight-ctis: represents flush and reset CTIs for TMC buffer |
| 108 | |
| 109 | * qcom,force-reg-dump: enables TMC reg dump support |
| 110 | |
| 111 | * arm,sg-enable : indicates whether scatter gather feature is enabled |
| 112 | by default for TMC ETR configuration. |
| 113 | |
| 114 | * Required property for TPDAs: |
| 115 | |
| 116 | * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. |
| 117 | |
| 118 | * Optional properties for TPDAs: |
| 119 | |
| 120 | * qcom,bc-elem-size: specifies the BC element size supported by each |
| 121 | monitor connected to the aggregator on each port. Should be specified |
| 122 | in pairs (port, bc element size). |
| 123 | |
| 124 | * qcom,tc-elem-size: specifies the TC element size supported by each |
| 125 | monitor connected to the aggregator on each port. Should be specified |
| 126 | in pairs (port, tc element size). |
| 127 | |
| 128 | * qcom,dsb-elem-size: specifies the DSB element size supported by each |
| 129 | monitor connected to the aggregator on each port. Should be specified |
| 130 | in pairs (port, dsb element size). |
| 131 | |
| 132 | * qcom,cmb-elem-size: specifies the CMB element size supported by each |
| 133 | monitor connected to the aggregator on each port. Should be specified |
| 134 | in pairs (port, cmb element size). |
| 135 | |
| 136 | * Optional properties for TPDM: |
| 137 | |
| 138 | * qcom,clk-enable: specifies whether additional clock bit needs to be |
| 139 | set for M4M TPDM. |
| 140 | |
| 141 | * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed |
| 142 | after enabling the subunit. |
| 143 | |
Satyajit Desai | e450813 | 2017-04-05 17:15:22 -0700 | [diff] [blame^] | 144 | * Optional properties for CTI: |
| 145 | |
| 146 | * qcom,cti-gpio-trigin: cti trigger input driven by gpio. |
| 147 | |
| 148 | * qcom,cti-gpio-trigout: cti trigger output sent to gpio. |
| 149 | |
| 150 | * pinctrl-names: names corresponding to the numbered pinctrl. The |
| 151 | allowed names are subset of the following: cti-trigin-pinctrl, |
| 152 | cti-trigout-pctrl. |
| 153 | |
| 154 | * pinctrl-<n>: list of pinctrl phandles for the different pinctrl |
| 155 | states. Refer to |
| 156 | "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" |
| 157 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 158 | * Required property for Remote ETMs: |
| 159 | |
| 160 | * qcom,inst-id: must be present. QMI instance id for remote ETMs. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 161 | |
| 162 | Example: |
| 163 | |
| 164 | 1. Sinks |
| 165 | etb@20010000 { |
| 166 | compatible = "arm,coresight-etb10", "arm,primecell"; |
| 167 | reg = <0 0x20010000 0 0x1000>; |
| 168 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 169 | clocks = <&oscclk6a>; |
| 170 | clock-names = "apb_pclk"; |
| 171 | port { |
| 172 | etb_in_port: endpoint@0 { |
| 173 | slave-mode; |
| 174 | remote-endpoint = <&replicator_out_port0>; |
| 175 | }; |
| 176 | }; |
| 177 | }; |
| 178 | |
| 179 | tpiu@20030000 { |
| 180 | compatible = "arm,coresight-tpiu", "arm,primecell"; |
| 181 | reg = <0 0x20030000 0 0x1000>; |
| 182 | |
| 183 | clocks = <&oscclk6a>; |
| 184 | clock-names = "apb_pclk"; |
| 185 | port { |
| 186 | tpiu_in_port: endpoint@0 { |
| 187 | slave-mode; |
| 188 | remote-endpoint = <&replicator_out_port1>; |
| 189 | }; |
| 190 | }; |
| 191 | }; |
| 192 | |
| 193 | 2. Links |
| 194 | replicator { |
| 195 | /* non-configurable replicators don't show up on the |
| 196 | * AMBA bus. As such no need to add "arm,primecell". |
| 197 | */ |
| 198 | compatible = "arm,coresight-replicator"; |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 199 | |
| 200 | ports { |
| 201 | #address-cells = <1>; |
| 202 | #size-cells = <0>; |
| 203 | |
| 204 | /* replicator output ports */ |
| 205 | port@0 { |
| 206 | reg = <0>; |
| 207 | replicator_out_port0: endpoint { |
| 208 | remote-endpoint = <&etb_in_port>; |
| 209 | }; |
| 210 | }; |
| 211 | |
| 212 | port@1 { |
| 213 | reg = <1>; |
| 214 | replicator_out_port1: endpoint { |
| 215 | remote-endpoint = <&tpiu_in_port>; |
| 216 | }; |
| 217 | }; |
| 218 | |
| 219 | /* replicator input port */ |
| 220 | port@2 { |
| 221 | reg = <0>; |
| 222 | replicator_in_port0: endpoint { |
| 223 | slave-mode; |
| 224 | remote-endpoint = <&funnel_out_port0>; |
| 225 | }; |
| 226 | }; |
| 227 | }; |
| 228 | }; |
| 229 | |
| 230 | funnel@20040000 { |
| 231 | compatible = "arm,coresight-funnel", "arm,primecell"; |
| 232 | reg = <0 0x20040000 0 0x1000>; |
| 233 | |
| 234 | clocks = <&oscclk6a>; |
| 235 | clock-names = "apb_pclk"; |
| 236 | ports { |
| 237 | #address-cells = <1>; |
| 238 | #size-cells = <0>; |
| 239 | |
| 240 | /* funnel output port */ |
| 241 | port@0 { |
| 242 | reg = <0>; |
| 243 | funnel_out_port0: endpoint { |
| 244 | remote-endpoint = |
| 245 | <&replicator_in_port0>; |
| 246 | }; |
| 247 | }; |
| 248 | |
| 249 | /* funnel input ports */ |
| 250 | port@1 { |
| 251 | reg = <0>; |
| 252 | funnel_in_port0: endpoint { |
| 253 | slave-mode; |
| 254 | remote-endpoint = <&ptm0_out_port>; |
| 255 | }; |
| 256 | }; |
| 257 | |
| 258 | port@2 { |
| 259 | reg = <1>; |
| 260 | funnel_in_port1: endpoint { |
| 261 | slave-mode; |
| 262 | remote-endpoint = <&ptm1_out_port>; |
| 263 | }; |
| 264 | }; |
| 265 | |
| 266 | port@3 { |
| 267 | reg = <2>; |
| 268 | funnel_in_port2: endpoint { |
| 269 | slave-mode; |
| 270 | remote-endpoint = <&etm0_out_port>; |
| 271 | }; |
| 272 | }; |
| 273 | |
| 274 | }; |
| 275 | }; |
| 276 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 277 | tpda_mss: tpda@7043000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 278 | compatible = "qcom,coresight-tpda", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 279 | reg = <0x7043000 0x1000>; |
| 280 | reg-names = "tpda-base"; |
| 281 | |
| 282 | coresight-name = "coresight-tpda-mss"; |
| 283 | |
| 284 | qcom,tpda-atid = <67>; |
| 285 | qcom,dsb-elem-size = <0 32>; |
| 286 | qcom,cmb-elem-size = <0 32>; |
| 287 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 288 | clocks = <&clock_aop clk_qdss_clk>; |
| 289 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 290 | |
| 291 | ports { |
| 292 | #address-cells = <1>; |
| 293 | #size-cells = <0>; |
| 294 | port@0 { |
| 295 | reg = <0>; |
| 296 | tpda_mss_out_funnel_in1: endpoint { |
| 297 | remote-endpoint = |
| 298 | <&funnel_in1_in_tpda_mss>; |
| 299 | }; |
| 300 | }; |
| 301 | port@1 { |
| 302 | reg = <0>; |
| 303 | tpda_mss_in_tpdm_mss: endpoint { |
| 304 | slave-mode; |
| 305 | remote-endpoint = |
| 306 | <&tpdm_mss_out_tpda_mss>; |
| 307 | }; |
| 308 | }; |
| 309 | }; |
| 310 | }; |
| 311 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 312 | 3. Sources |
| 313 | ptm@2201c000 { |
| 314 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 315 | reg = <0 0x2201c000 0 0x1000>; |
| 316 | |
| 317 | cpu = <&cpu0>; |
| 318 | clocks = <&oscclk6a>; |
| 319 | clock-names = "apb_pclk"; |
| 320 | port { |
| 321 | ptm0_out_port: endpoint { |
| 322 | remote-endpoint = <&funnel_in_port0>; |
| 323 | }; |
| 324 | }; |
| 325 | }; |
| 326 | |
| 327 | ptm@2201d000 { |
| 328 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 329 | reg = <0 0x2201d000 0 0x1000>; |
| 330 | |
| 331 | cpu = <&cpu1>; |
| 332 | clocks = <&oscclk6a>; |
| 333 | clock-names = "apb_pclk"; |
| 334 | port { |
| 335 | ptm1_out_port: endpoint { |
| 336 | remote-endpoint = <&funnel_in_port1>; |
| 337 | }; |
| 338 | }; |
| 339 | }; |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 340 | |
| 341 | 4. STM |
| 342 | stm@20100000 { |
| 343 | compatible = "arm,coresight-stm", "arm,primecell"; |
| 344 | reg = <0 0x20100000 0 0x1000>, |
| 345 | <0 0x28000000 0 0x180000>; |
| 346 | reg-names = "stm-base", "stm-stimulus-base"; |
| 347 | |
| 348 | clocks = <&soc_smc50mhz>; |
| 349 | clock-names = "apb_pclk"; |
| 350 | port { |
| 351 | stm_out_port: endpoint { |
| 352 | remote-endpoint = <&main_funnel_in_port2>; |
| 353 | }; |
| 354 | }; |
| 355 | }; |
| 356 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 357 | tpdm_mss: tpdm@7042000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 358 | compatible = "qcom,coresight-tpdm", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 359 | reg = <0x7042000 0x1000>; |
| 360 | reg-names = "tpdm-base"; |
| 361 | |
| 362 | coresight-name = "coresight-tpdm-mss"; |
| 363 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 364 | clocks = <&clock_aop qdss_clk>; |
| 365 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 366 | |
| 367 | port{ |
| 368 | tpdm_mss_out_tpda_mss: endpoint { |
| 369 | remote-endpoint = <&tpda_mss_in_tpdm_mss>; |
| 370 | }; |
| 371 | }; |
| 372 | }; |
| 373 | |
| 374 | 4. CTIs |
| 375 | cti0: cti@6010000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 376 | compatible = "arm,coresight-cti", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 377 | reg = <0x6010000 0x1000>; |
| 378 | reg-names = "cti-base"; |
| 379 | |
| 380 | coresight-name = "coresight-cti0"; |
| 381 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 382 | clocks = <&clock_aop qdss_clk>; |
| 383 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 384 | }; |
| 385 | |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 386 | [1]. There is currently two version of STM: STM32 and STM500. Both |
| 387 | have the same HW interface and as such don't need an explicit binding name. |