Harry Yang | 3d515b8 | 2018-04-06 16:01:04 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __SMB2_CHARGER_REG_H |
| 14 | #define __SMB2_CHARGER_REG_H |
| 15 | |
| 16 | #include <linux/bitops.h> |
| 17 | |
| 18 | #define CHGR_BASE 0x1000 |
| 19 | #define OTG_BASE 0x1100 |
| 20 | #define BATIF_BASE 0x1200 |
| 21 | #define USBIN_BASE 0x1300 |
| 22 | #define DCIN_BASE 0x1400 |
| 23 | #define MISC_BASE 0x1600 |
Anirudh Ghayal | 4da3df9 | 2017-01-25 18:55:57 +0530 | [diff] [blame] | 24 | #define CHGR_FREQ_BASE 0x1900 |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 25 | |
| 26 | #define PERPH_TYPE_OFFSET 0x04 |
| 27 | #define TYPE_MASK GENMASK(7, 0) |
| 28 | #define PERPH_SUBTYPE_OFFSET 0x05 |
| 29 | #define SUBTYPE_MASK GENMASK(7, 0) |
| 30 | #define INT_RT_STS_OFFSET 0x10 |
| 31 | |
| 32 | /* CHGR Peripheral Registers */ |
| 33 | #define BATTERY_CHARGER_STATUS_1_REG (CHGR_BASE + 0x06) |
| 34 | #define BVR_INITIAL_RAMP_BIT BIT(7) |
| 35 | #define CC_SOFT_TERMINATE_BIT BIT(6) |
Harry Yang | bedee33 | 2016-08-31 16:14:29 -0700 | [diff] [blame] | 36 | #define STEP_CHARGING_STATUS_SHIFT 3 |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 37 | #define STEP_CHARGING_STATUS_MASK GENMASK(5, 3) |
| 38 | #define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0) |
| 39 | enum { |
| 40 | TRICKLE_CHARGE = 0, |
| 41 | PRE_CHARGE, |
| 42 | FAST_CHARGE, |
| 43 | FULLON_CHARGE, |
| 44 | TAPER_CHARGE, |
Nicholas Troast | 8cb7755 | 2016-09-23 11:50:18 -0700 | [diff] [blame] | 45 | TERMINATE_CHARGE, |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 46 | INHIBIT_CHARGE, |
Nicholas Troast | 8cb7755 | 2016-09-23 11:50:18 -0700 | [diff] [blame] | 47 | DISABLE_CHARGE, |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | #define BATTERY_CHARGER_STATUS_2_REG (CHGR_BASE + 0x07) |
| 51 | #define INPUT_CURRENT_LIMITED_BIT BIT(7) |
| 52 | #define CHARGER_ERROR_STATUS_SFT_EXPIRE_BIT BIT(6) |
| 53 | #define CHARGER_ERROR_STATUS_BAT_OV_BIT BIT(5) |
| 54 | #define CHARGER_ERROR_STATUS_BAT_TERM_MISSING_BIT BIT(4) |
| 55 | #define BAT_TEMP_STATUS_MASK GENMASK(3, 0) |
Abhijeet Dharmapurikar | c0b0f59 | 2016-10-14 10:55:42 -0700 | [diff] [blame] | 56 | #define BAT_TEMP_STATUS_SOFT_LIMIT_MASK GENMASK(3, 2) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 57 | #define BAT_TEMP_STATUS_HOT_SOFT_LIMIT_BIT BIT(3) |
| 58 | #define BAT_TEMP_STATUS_COLD_SOFT_LIMIT_BIT BIT(2) |
| 59 | #define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(1) |
| 60 | #define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(0) |
| 61 | |
| 62 | #define CHG_OPTION_REG (CHGR_BASE + 0x08) |
| 63 | #define PIN_BIT BIT(7) |
| 64 | |
| 65 | #define BATTERY_CHARGER_STATUS_3_REG (CHGR_BASE + 0x09) |
| 66 | #define FV_POST_JEITA_MASK GENMASK(7, 0) |
| 67 | |
| 68 | #define BATTERY_CHARGER_STATUS_4_REG (CHGR_BASE + 0x0A) |
| 69 | #define CHARGE_CURRENT_POST_JEITA_MASK GENMASK(7, 0) |
| 70 | |
| 71 | #define BATTERY_CHARGER_STATUS_5_REG (CHGR_BASE + 0x0B) |
| 72 | #define VALID_INPUT_POWER_SOURCE_BIT BIT(7) |
| 73 | #define DISABLE_CHARGING_BIT BIT(6) |
| 74 | #define FORCE_ZERO_CHARGE_CURRENT_BIT BIT(5) |
| 75 | #define CHARGING_ENABLE_BIT BIT(4) |
| 76 | #define TAPER_BIT BIT(3) |
| 77 | #define ENABLE_CHG_SENSORS_BIT BIT(2) |
| 78 | #define ENABLE_TAPER_SENSOR_BIT BIT(1) |
| 79 | #define TAPER_REGION_BIT BIT(0) |
| 80 | |
| 81 | #define BATTERY_CHARGER_STATUS_6_REG (CHGR_BASE + 0x0C) |
| 82 | #define GF_BATT_OV_BIT BIT(7) |
| 83 | #define DROP_IN_BATTERY_VOLTAGE_REFERENCE_BIT BIT(6) |
| 84 | #define VBATT_LTET_RECHARGE_BIT BIT(5) |
| 85 | #define VBATT_GTET_INHIBIT_BIT BIT(4) |
| 86 | #define VBATT_GTET_FLOAT_VOLTAGE_BIT BIT(3) |
| 87 | #define BATT_GT_PRE_TO_FAST_BIT BIT(2) |
| 88 | #define BATT_GT_FULL_ON_BIT BIT(1) |
| 89 | #define VBATT_LT_2V_BIT BIT(0) |
| 90 | |
| 91 | #define BATTERY_CHARGER_STATUS_7_REG (CHGR_BASE + 0x0D) |
| 92 | #define ENABLE_TRICKLE_BIT BIT(7) |
| 93 | #define ENABLE_PRE_CHARGING_BIT BIT(6) |
| 94 | #define ENABLE_FAST_CHARGING_BIT BIT(5) |
| 95 | #define ENABLE_FULLON_MODE_BIT BIT(4) |
| 96 | #define TOO_COLD_ADC_BIT BIT(3) |
| 97 | #define TOO_HOT_ADC_BIT BIT(2) |
| 98 | #define HOT_SL_ADC_BIT BIT(1) |
| 99 | #define COLD_SL_ADC_BIT BIT(0) |
| 100 | |
| 101 | #define BATTERY_CHARGER_STATUS_8_REG (CHGR_BASE + 0x0E) |
| 102 | #define PRE_FAST_BIT BIT(7) |
| 103 | #define PRE_FULLON_BIT BIT(6) |
| 104 | #define PRE_RCHG_BIT BIT(5) |
| 105 | #define PRE_INHIBIT_BIT BIT(4) |
| 106 | #define PRE_OVRV_BIT BIT(3) |
| 107 | #define PRE_TERM_BIT BIT(2) |
| 108 | #define BAT_ID_BMISS_CMP_BIT BIT(1) |
| 109 | #define THERM_CMP_BIT BIT(0) |
| 110 | |
| 111 | /* CHGR Interrupt Bits */ |
| 112 | #define CHGR_7_RT_STS_BIT BIT(7) |
| 113 | #define CHGR_6_RT_STS_BIT BIT(6) |
| 114 | #define FG_FVCAL_QUALIFIED_RT_STS_BIT BIT(5) |
| 115 | #define STEP_CHARGING_SOC_UPDATE_REQUEST_RT_STS_BIT BIT(4) |
| 116 | #define STEP_CHARGING_SOC_UPDATE_FAIL_RT_STS_BIT BIT(3) |
| 117 | #define STEP_CHARGING_STATE_CHANGE_RT_STS_BIT BIT(2) |
| 118 | #define CHARGING_STATE_CHANGE_RT_STS_BIT BIT(1) |
| 119 | #define CHGR_ERROR_RT_STS_BIT BIT(0) |
| 120 | |
| 121 | #define STEP_CHG_SOC_VBATT_V_REG (CHGR_BASE + 0x40) |
| 122 | #define STEP_CHG_SOC_VBATT_V_MASK GENMASK(7, 0) |
| 123 | |
| 124 | #define STEP_CHG_SOC_VBATT_V_UPDATE_REG (CHGR_BASE + 0x41) |
| 125 | #define STEP_CHG_SOC_VBATT_V_UPDATE_BIT BIT(0) |
| 126 | |
| 127 | #define CHARGING_ENABLE_CMD_REG (CHGR_BASE + 0x42) |
| 128 | #define CHARGING_ENABLE_CMD_BIT BIT(0) |
| 129 | |
| 130 | #define ALLOW_FAST_CHARGING_CMD_REG (CHGR_BASE + 0x43) |
| 131 | #define ALLOW_FAST_CHARGING_CMD_BIT BIT(0) |
| 132 | |
| 133 | #define QNOVO_PT_ENABLE_CMD_REG (CHGR_BASE + 0x44) |
| 134 | #define QNOVO_PT_ENABLE_CMD_BIT BIT(0) |
| 135 | |
| 136 | #define CHGR_CFG1_REG (CHGR_BASE + 0x50) |
| 137 | #define INCREASE_RCHG_TIMEOUT_CFG_BIT BIT(1) |
| 138 | #define LOAD_BAT_BIT BIT(0) |
| 139 | |
| 140 | #define CHGR_CFG2_REG (CHGR_BASE + 0x51) |
| 141 | #define CHG_EN_SRC_BIT BIT(7) |
| 142 | #define CHG_EN_POLARITY_BIT BIT(6) |
| 143 | #define PRETOFAST_TRANSITION_CFG_BIT BIT(5) |
| 144 | #define BAT_OV_ECC_BIT BIT(4) |
| 145 | #define I_TERM_BIT BIT(3) |
| 146 | #define AUTO_RECHG_BIT BIT(2) |
| 147 | #define EN_ANALOG_DROP_IN_VBATT_BIT BIT(1) |
| 148 | #define CHARGER_INHIBIT_BIT BIT(0) |
| 149 | |
| 150 | #define CHARGER_ENABLE_CFG_REG (CHGR_BASE + 0x52) |
| 151 | #define CHG_ENB_TIMEOUT_SETTING_BIT BIT(1) |
| 152 | #define FORCE_ZERO_CFG_BIT BIT(0) |
| 153 | |
| 154 | #define CFG_REG (CHGR_BASE + 0x53) |
| 155 | #define CHG_OPTION_PIN_TRIM_BIT BIT(7) |
| 156 | #define BATN_SNS_CFG_BIT BIT(4) |
| 157 | #define CFG_TAPER_DIS_AFVC_BIT BIT(3) |
| 158 | #define BATFET_SHUTDOWN_CFG_BIT BIT(2) |
| 159 | #define VDISCHG_EN_CFG_BIT BIT(1) |
| 160 | #define VCHG_EN_CFG_BIT BIT(0) |
| 161 | |
| 162 | #define CHARGER_SPARE_REG (CHGR_BASE + 0x54) |
| 163 | #define CHARGER_SPARE_MASK GENMASK(5, 0) |
| 164 | |
| 165 | #define PRE_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x60) |
| 166 | #define PRE_CHARGE_CURRENT_SETTING_MASK GENMASK(5, 0) |
| 167 | |
| 168 | #define FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x61) |
| 169 | #define FAST_CHARGE_CURRENT_SETTING_MASK GENMASK(7, 0) |
| 170 | |
| 171 | #define CHARGE_CURRENT_TERMINATION_CFG_REG (CHGR_BASE + 0x62) |
| 172 | #define ANALOG_CHARGE_CURRENT_TERMINATION_SETTING_MASK GENMASK(2, 0) |
| 173 | |
| 174 | #define TCCC_CHARGE_CURRENT_TERMINATION_CFG_REG (CHGR_BASE + 0x63) |
| 175 | #define TCCC_CHARGE_CURRENT_TERMINATION_SETTING_MASK GENMASK(3, 0) |
| 176 | |
| 177 | #define CHARGE_CURRENT_SOFTSTART_SETTING_CFG_REG (CHGR_BASE + 0x64) |
| 178 | #define CHARGE_CURRENT_SOFTSTART_SETTING_MASK GENMASK(1, 0) |
| 179 | |
| 180 | #define FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x70) |
| 181 | #define FLOAT_VOLTAGE_SETTING_MASK GENMASK(7, 0) |
| 182 | |
| 183 | #define AUTO_FLOAT_VOLTAGE_COMPENSATION_CFG_REG (CHGR_BASE + 0x71) |
| 184 | #define AUTO_FLOAT_VOLTAGE_COMPENSATION_MASK GENMASK(2, 0) |
| 185 | |
| 186 | #define CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x72) |
| 187 | #define CHARGE_INHIBIT_THRESHOLD_MASK GENMASK(1, 0) |
Subbaraman Narayanamurthy | 5c4f6de | 2016-11-02 15:25:32 -0700 | [diff] [blame] | 188 | #define CHARGE_INHIBIT_THRESHOLD_50MV 0 |
| 189 | #define CHARGE_INHIBIT_THRESHOLD_100MV 1 |
| 190 | #define CHARGE_INHIBIT_THRESHOLD_200MV 2 |
| 191 | #define CHARGE_INHIBIT_THRESHOLD_300MV 3 |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 192 | |
| 193 | #define RECHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x73) |
| 194 | #define RECHARGE_THRESHOLD_MASK GENMASK(1, 0) |
| 195 | |
| 196 | #define PRE_TO_FAST_CHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x74) |
| 197 | #define PRE_TO_FAST_CHARGE_THRESHOLD_MASK GENMASK(1, 0) |
| 198 | |
| 199 | #define FV_HYSTERESIS_CFG_REG (CHGR_BASE + 0x75) |
| 200 | #define FV_DROP_HYSTERESIS_CFG_MASK GENMASK(7, 4) |
| 201 | #define THRESH_HYSTERESIS_CFG_MASK GENMASK(3, 0) |
| 202 | |
| 203 | #define FVC_CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x80) |
| 204 | #define FVC_CHARGE_INHIBIT_THRESHOLD_MASK GENMASK(5, 0) |
| 205 | |
| 206 | #define FVC_RECHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x81) |
| 207 | #define FVC_RECHARGE_THRESHOLD_MASK GENMASK(7, 0) |
| 208 | |
| 209 | #define FVC_PRE_TO_FAST_CHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x82) |
| 210 | #define FVC_PRE_TO_FAST_CHARGE_THRESHOLD_MASK GENMASK(7, 0) |
| 211 | |
| 212 | #define FVC_FULL_ON_THRESHOLD_CFG_REG (CHGR_BASE + 0x83) |
| 213 | #define FVC_FULL_ON_THRESHOLD_MASK GENMASK(7, 0) |
| 214 | |
| 215 | #define FVC_CC_MODE_GLITCH_FILTER_SEL_CFG_REG (CHGR_BASE + 0x84) |
| 216 | #define FVC_CC_MODE_GLITCH_FILTER_SEL_MASK GENMASK(1, 0) |
| 217 | |
| 218 | #define FVC_TERMINATION_GLITCH_FILTER_SEL_CFG_REG (CHGR_BASE + 0x85) |
| 219 | #define FVC_TERMINATION_GLITCH_FILTER_SEL_MASK GENMASK(1, 0) |
| 220 | |
| 221 | #define JEITA_EN_CFG_REG (CHGR_BASE + 0x90) |
| 222 | #define JEITA_EN_HARDLIMIT_BIT BIT(4) |
| 223 | #define JEITA_EN_HOT_SL_FCV_BIT BIT(3) |
| 224 | #define JEITA_EN_COLD_SL_FCV_BIT BIT(2) |
| 225 | #define JEITA_EN_HOT_SL_CCC_BIT BIT(1) |
| 226 | #define JEITA_EN_COLD_SL_CCC_BIT BIT(0) |
| 227 | |
| 228 | #define JEITA_FVCOMP_CFG_REG (CHGR_BASE + 0x91) |
| 229 | #define JEITA_FVCOMP_MASK GENMASK(7, 0) |
| 230 | |
| 231 | #define JEITA_CCCOMP_CFG_REG (CHGR_BASE + 0x92) |
| 232 | #define JEITA_CCCOMP_MASK GENMASK(7, 0) |
| 233 | |
| 234 | #define FV_CAL_CFG_REG (CHGR_BASE + 0x76) |
| 235 | #define FV_CALIBRATION_CFG_MASK GENMASK(2, 0) |
| 236 | |
| 237 | #define FV_ADJUST_REG (CHGR_BASE + 0x77) |
| 238 | #define FLOAT_VOLTAGE_ADJUSTMENT_MASK GENMASK(4, 0) |
| 239 | |
| 240 | #define FG_VADC_DISQ_THRESH_REG (CHGR_BASE + 0x78) |
| 241 | #define VADC_DISQUAL_THRESH_MASK GENMASK(7, 0) |
| 242 | |
| 243 | #define FG_IADC_DISQ_THRESH_REG (CHGR_BASE + 0x79) |
| 244 | #define IADC_DISQUAL_THRESH_MASK GENMASK(7, 0) |
| 245 | |
| 246 | #define FG_UPDATE_CFG_1_REG (CHGR_BASE + 0x7A) |
| 247 | #define BT_TMPR_TCOLD_BIT BIT(7) |
| 248 | #define BT_TMPR_COLD_BIT BIT(6) |
| 249 | #define BT_TMPR_HOT_BIT BIT(5) |
| 250 | #define BT_TMPR_THOT_BIT BIT(4) |
| 251 | #define CHG_DIE_TMPR_HOT_BIT BIT(3) |
| 252 | #define CHG_DIE_TMPR_THOT_BIT BIT(2) |
| 253 | #define SKIN_TMPR_HOT_BIT BIT(1) |
| 254 | #define SKIN_TMPR_THOT_BIT BIT(0) |
| 255 | |
| 256 | #define FG_UPDATE_CFG_1_SEL_REG (CHGR_BASE + 0x7B) |
| 257 | #define BT_TMPR_TCOLD_SEL_BIT BIT(7) |
| 258 | #define BT_TMPR_COLD_SEL_BIT BIT(6) |
| 259 | #define BT_TMPR_HOT_SEL_BIT BIT(5) |
| 260 | #define BT_TMPR_THOT_SEL_BIT BIT(4) |
| 261 | #define CHG_DIE_TMPR_HOT_SEL_BIT BIT(3) |
| 262 | #define CHG_DIE_TMPR_THOT_SEL_BIT BIT(2) |
| 263 | #define SKIN_TMPR_HOT_SEL_BIT BIT(1) |
| 264 | #define SKIN_TMPR_THOT_SEL_BIT BIT(0) |
| 265 | |
| 266 | #define FG_UPDATE_CFG_2_REG (CHGR_BASE + 0x7C) |
| 267 | #define SOC_LT_OTG_THRESH_BIT BIT(3) |
| 268 | #define SOC_LT_CHG_RECHARGE_THRESH_BIT BIT(2) |
| 269 | #define VBT_LT_CHG_RECHARGE_THRESH_BIT BIT(1) |
| 270 | #define IBT_LT_CHG_TERM_THRESH_BIT BIT(0) |
| 271 | |
| 272 | #define FG_UPDATE_CFG_2_SEL_REG (CHGR_BASE + 0x7D) |
| 273 | #define SOC_LT_OTG_THRESH_SEL_BIT BIT(3) |
| 274 | #define SOC_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(2) |
| 275 | #define VBT_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(1) |
| 276 | #define IBT_LT_CHG_TERM_THRESH_SEL_BIT BIT(0) |
| 277 | |
| 278 | #define FG_CHG_INTERFACE_CFG_REG (CHGR_BASE + 0x7E) |
| 279 | #define ESR_ISINK_CFG_MASK GENMASK(7, 6) |
| 280 | #define ESR_FASTCHG_DECR_CFG_MASK GENMASK(5, 4) |
| 281 | #define FG_CHARGER_INHIBIT_BIT BIT(3) |
| 282 | #define FG_BATFET_BIT BIT(2) |
| 283 | #define IADC_SYNC_CNV_BIT BIT(1) |
| 284 | #define VADC_SYNC_CNV_BIT BIT(0) |
| 285 | |
| 286 | #define FG_CHG_INTERFACE_CFG_SEL_REG (CHGR_BASE + 0x7F) |
| 287 | #define ESR_ISINK_CFG_SEL_BIT BIT(5) |
| 288 | #define ESR_FASTCHG_DECR_CFG_SEL_BIT BIT(4) |
| 289 | #define FG_CHARGER_INHIBIT_SEL_BIT BIT(3) |
| 290 | #define FG_BATFET_SEL_BIT BIT(2) |
| 291 | #define IADC_SYNC_CNV_SEL_BIT BIT(1) |
| 292 | #define VADC_SYNC_CNV_SEL_BIT BIT(0) |
| 293 | |
Harry Yang | fe91384 | 2016-08-10 12:27:28 -0700 | [diff] [blame] | 294 | #define CHGR_STEP_CHG_MODE_CFG_REG (CHGR_BASE + 0xB0) |
| 295 | #define STEP_CHARGING_SOC_FAIL_OPTION_BIT BIT(3) |
| 296 | #define STEP_CHARGING_MODE_SELECT_BIT BIT(2) |
| 297 | #define STEP_CHARGING_SOURCE_SELECT_BIT BIT(1) |
| 298 | #define STEP_CHARGING_ENABLE_BIT BIT(0) |
| 299 | |
| 300 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_CFG_REG (CHGR_BASE + 0xB1) |
| 301 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_CFG_MASK GENMASK(0, 1) |
| 302 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_5S 0 |
| 303 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_10S 1 |
| 304 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_20S 2 |
| 305 | #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_40S 3 |
| 306 | |
| 307 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_CFG_REG (CHGR_BASE + 0xB2) |
| 308 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_CFG_MASK GENMASK(0, 1) |
| 309 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_10S 0 |
| 310 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_30S 1 |
| 311 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_60S 2 |
| 312 | #define STEP_CHG_UPDATE_FAIL_TIMEOUT_120S 3 |
| 313 | |
| 314 | #define STEP_CHG_SOC_OR_BATT_V_TH1_REG (CHGR_BASE + 0xB3) |
| 315 | #define STEP_CHG_SOC_OR_BATT_V_TH2_REG (CHGR_BASE + 0xB4) |
| 316 | #define STEP_CHG_SOC_OR_BATT_V_TH3_REG (CHGR_BASE + 0xB5) |
| 317 | #define STEP_CHG_SOC_OR_BATT_V_TH4_REG (CHGR_BASE + 0xB6) |
| 318 | #define STEP_CHG_CURRENT_DELTA1_REG (CHGR_BASE + 0xB7) |
| 319 | #define STEP_CHG_CURRENT_DELTA2_REG (CHGR_BASE + 0xB8) |
| 320 | #define STEP_CHG_CURRENT_DELTA3_REG (CHGR_BASE + 0xB9) |
| 321 | #define STEP_CHG_CURRENT_DELTA4_REG (CHGR_BASE + 0xBA) |
| 322 | #define STEP_CHG_CURRENT_DELTA5_REG (CHGR_BASE + 0xBB) |
| 323 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 324 | /* OTG Peripheral Registers */ |
| 325 | #define RID_CC_CONTROL_23_16_REG (OTG_BASE + 0x06) |
| 326 | #define RID_CC_CONTROL_23_BIT BIT(7) |
| 327 | #define VCONN_SOFTSTART_EN_BIT BIT(6) |
| 328 | #define VCONN_SFTST_CFG_MASK GENMASK(5, 4) |
| 329 | #define CONNECT_RIDCC_SENSOR_TO_CC_MASK GENMASK(3, 2) |
| 330 | #define EN_CC_1P1CLAMP_BIT BIT(1) |
| 331 | #define ENABLE_CRUDESEN_CC_1_BIT BIT(0) |
| 332 | |
| 333 | #define RID_CC_CONTROL_15_8_REG (OTG_BASE + 0x07) |
| 334 | #define ENABLE_CRUDESEN_CC_0_BIT BIT(7) |
| 335 | #define EN_FMB_2P5UA_CC_MASK GENMASK(6, 5) |
| 336 | #define EN_ISRC_180UA_BIT BIT(4) |
| 337 | #define ENABLE_CURRENTSOURCE_CC_MASK GENMASK(3, 2) |
| 338 | #define EN_BANDGAP_RID_C_DET_BIT BIT(1) |
| 339 | #define ENABLE_RD_CC_1_BIT BIT(0) |
| 340 | |
| 341 | #define RID_CC_CONTROL_7_0_REG (OTG_BASE + 0x08) |
| 342 | #define ENABLE_RD_CC_0_BIT BIT(7) |
| 343 | #define VCONN_ILIM500MA_BIT BIT(6) |
| 344 | #define EN_MICRO_USB_MODE_BIT BIT(5) |
| 345 | #define UFP_DFP_MODE_BIT BIT(4) |
| 346 | #define VCONN_EN_CC_MASK GENMASK(3, 2) |
| 347 | #define VREF_SEL_RIDCC_SENSOR_MASK GENMASK(1, 0) |
| 348 | |
| 349 | #define OTG_STATUS_REG (OTG_BASE + 0x09) |
| 350 | #define BOOST_SOFTSTART_DONE_BIT BIT(3) |
| 351 | #define OTG_STATE_MASK GENMASK(2, 0) |
Nicholas Troast | 8995a70 | 2016-12-05 10:22:22 -0800 | [diff] [blame] | 352 | #define OTG_STATE_ENABLED 0x2 |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 353 | |
| 354 | /* OTG Interrupt Bits */ |
| 355 | #define TESTMODE_CHANGE_DETECT_RT_STS_BIT BIT(3) |
| 356 | #define OTG_OC_DIS_SW_STS_RT_STS_BIT BIT(2) |
| 357 | #define OTG_OVERCURRENT_RT_STS_BIT BIT(1) |
| 358 | #define OTG_FAIL_RT_STS_BIT BIT(0) |
| 359 | |
| 360 | #define CMD_OTG_REG (OTG_BASE + 0x40) |
| 361 | #define OTG_EN_BIT BIT(0) |
| 362 | |
| 363 | #define BAT_UVLO_THRESHOLD_CFG_REG (OTG_BASE + 0x51) |
| 364 | #define BAT_UVLO_THRESHOLD_MASK GENMASK(1, 0) |
| 365 | |
| 366 | #define OTG_CURRENT_LIMIT_CFG_REG (OTG_BASE + 0x52) |
| 367 | #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0) |
| 368 | |
| 369 | #define OTG_CFG_REG (OTG_BASE + 0x53) |
Nicholas Troast | b11015f | 2017-01-17 17:56:45 -0800 | [diff] [blame] | 370 | #define OTG_RESERVED_MASK GENMASK(7, 6) |
| 371 | #define DIS_OTG_ON_TLIM_BIT BIT(5) |
| 372 | #define QUICKSTART_OTG_FASTROLESWAP_BIT BIT(4) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 373 | #define INCREASE_DFP_TIME_BIT BIT(3) |
| 374 | #define ENABLE_OTG_IN_DEBUG_MODE_BIT BIT(2) |
| 375 | #define OTG_EN_SRC_CFG_BIT BIT(1) |
| 376 | #define CONCURRENT_MODE_CFG_BIT BIT(0) |
| 377 | |
Harry Yang | 360bd53 | 2016-09-26 11:03:22 -0700 | [diff] [blame] | 378 | #define OTG_ENG_OTG_CFG_REG (OTG_BASE + 0xC0) |
| 379 | #define ENG_BUCKBOOST_HALT1_8_MODE_BIT BIT(0) |
| 380 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 381 | /* BATIF Peripheral Registers */ |
| 382 | /* BATIF Interrupt Bits */ |
| 383 | #define BAT_7_RT_STS_BIT BIT(7) |
| 384 | #define BAT_6_RT_STS_BIT BIT(6) |
| 385 | #define BAT_TERMINAL_MISSING_RT_STS_BIT BIT(5) |
| 386 | #define BAT_THERM_OR_ID_MISSING_RT_STS_BIT BIT(4) |
| 387 | #define BAT_LOW_RT_STS_BIT BIT(3) |
| 388 | #define BAT_OV_RT_STS_BIT BIT(2) |
| 389 | #define BAT_OCP_RT_STS_BIT BIT(1) |
| 390 | #define BAT_TEMP_RT_STS_BIT BIT(0) |
| 391 | |
| 392 | #define SHIP_MODE_REG (BATIF_BASE + 0x40) |
| 393 | #define SHIP_MODE_EN_BIT BIT(0) |
| 394 | |
| 395 | #define BATOCP_THRESHOLD_CFG_REG (BATIF_BASE + 0x50) |
| 396 | #define BATOCP_ENABLE_CFG_BIT BIT(3) |
| 397 | #define BATOCP_THRESHOLD_MASK GENMASK(2, 0) |
| 398 | |
| 399 | #define BATOCP_INTRPT_DELAY_TMR_CFG_REG (BATIF_BASE + 0x51) |
| 400 | #define BATOCP_INTRPT_TIMEOUT_MASK GENMASK(5, 3) |
| 401 | #define BATOCP_DELAY_TIMEOUT_MASK GENMASK(2, 0) |
| 402 | |
| 403 | #define BATOCP_RESET_TMR_CFG_REG (BATIF_BASE + 0x52) |
| 404 | #define EN_BATOCP_RESET_TMR_BIT BIT(3) |
| 405 | #define BATOCP_RESET_TIMEOUT_MASK GENMASK(2, 0) |
| 406 | |
| 407 | #define LOW_BATT_DETECT_EN_CFG_REG (BATIF_BASE + 0x60) |
| 408 | #define LOW_BATT_DETECT_EN_BIT BIT(0) |
| 409 | |
| 410 | #define LOW_BATT_THRESHOLD_CFG_REG (BATIF_BASE + 0x61) |
| 411 | #define LOW_BATT_THRESHOLD_MASK GENMASK(3, 0) |
| 412 | |
| 413 | #define BAT_FET_CFG_REG (BATIF_BASE + 0x62) |
| 414 | #define BAT_FET_CFG_BIT BIT(0) |
| 415 | |
| 416 | #define BAT_MISS_SRC_CFG_REG (BATIF_BASE + 0x70) |
| 417 | #define BAT_MISS_ALG_EN_BIT BIT(2) |
| 418 | #define BAT_MISS_RESERVED_BIT BIT(1) |
| 419 | #define BAT_MISS_PIN_SRC_EN_BIT BIT(0) |
| 420 | |
| 421 | #define BAT_MISS_ALG_OPTIONS_CFG_REG (BATIF_BASE + 0x71) |
| 422 | #define BAT_MISS_INPUT_PLUGIN_BIT BIT(2) |
| 423 | #define BAT_MISS_TMR_START_OPTION_BIT BIT(1) |
| 424 | #define BAT_MISS_POLL_EN_BIT BIT(0) |
| 425 | |
| 426 | #define BAT_MISS_PIN_GF_CFG_REG (BATIF_BASE + 0x72) |
| 427 | #define BAT_MISS_PIN_GF_MASK GENMASK(1, 0) |
| 428 | |
| 429 | /* USBIN Peripheral Registers */ |
| 430 | #define USBIN_INPUT_STATUS_REG (USBIN_BASE + 0x06) |
| 431 | #define USBIN_INPUT_STATUS_7_BIT BIT(7) |
| 432 | #define USBIN_INPUT_STATUS_6_BIT BIT(6) |
| 433 | #define USBIN_12V_BIT BIT(5) |
| 434 | #define USBIN_9V_TO_12V_BIT BIT(4) |
| 435 | #define USBIN_9V_BIT BIT(3) |
| 436 | #define USBIN_5V_TO_12V_BIT BIT(2) |
| 437 | #define USBIN_5V_TO_9V_BIT BIT(1) |
| 438 | #define USBIN_5V_BIT BIT(0) |
Harry Yang | cdad2bf | 2016-10-04 17:03:56 -0700 | [diff] [blame] | 439 | #define QC_2P0_STATUS_MASK GENMASK(2, 0) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 440 | |
| 441 | #define APSD_STATUS_REG (USBIN_BASE + 0x07) |
| 442 | #define APSD_STATUS_7_BIT BIT(7) |
Harry Yang | 1369b7a | 2016-09-27 15:59:50 -0700 | [diff] [blame] | 443 | #define HVDCP_CHECK_TIMEOUT_BIT BIT(6) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 444 | #define SLOW_PLUGIN_TIMEOUT_BIT BIT(5) |
| 445 | #define ENUMERATION_DONE_BIT BIT(4) |
| 446 | #define VADP_CHANGE_DONE_AFTER_AUTH_BIT BIT(3) |
| 447 | #define QC_AUTH_DONE_STATUS_BIT BIT(2) |
| 448 | #define QC_CHARGER_BIT BIT(1) |
| 449 | #define APSD_DTC_STATUS_DONE_BIT BIT(0) |
| 450 | |
| 451 | #define APSD_RESULT_STATUS_REG (USBIN_BASE + 0x08) |
| 452 | #define ICL_OVERRIDE_LATCH_BIT BIT(7) |
| 453 | #define APSD_RESULT_STATUS_MASK GENMASK(6, 0) |
| 454 | #define QC_3P0_BIT BIT(6) |
| 455 | #define QC_2P0_BIT BIT(5) |
| 456 | #define FLOAT_CHARGER_BIT BIT(4) |
| 457 | #define DCP_CHARGER_BIT BIT(3) |
| 458 | #define CDP_CHARGER_BIT BIT(2) |
| 459 | #define OCP_CHARGER_BIT BIT(1) |
| 460 | #define SDP_CHARGER_BIT BIT(0) |
| 461 | |
| 462 | #define QC_CHANGE_STATUS_REG (USBIN_BASE + 0x09) |
| 463 | #define QC_CHANGE_STATUS_7_BIT BIT(7) |
| 464 | #define QC_CHANGE_STATUS_6_BIT BIT(6) |
| 465 | #define QC_9V_TO_12V_REASON_BIT BIT(5) |
| 466 | #define QC_5V_TO_9V_REASON_BIT BIT(4) |
| 467 | #define QC_CONTINUOUS_BIT BIT(3) |
| 468 | #define QC_12V_BIT BIT(2) |
| 469 | #define QC_9V_BIT BIT(1) |
| 470 | #define QC_5V_BIT BIT(0) |
| 471 | |
| 472 | #define QC_PULSE_COUNT_STATUS_REG (USBIN_BASE + 0x0A) |
| 473 | #define QC_PULSE_COUNT_STATUS_7_BIT BIT(7) |
| 474 | #define QC_PULSE_COUNT_STATUS_6_BIT BIT(6) |
| 475 | #define QC_PULSE_COUNT_MASK GENMASK(5, 0) |
| 476 | |
| 477 | #define TYPE_C_STATUS_1_REG (USBIN_BASE + 0x0B) |
| 478 | #define UFP_TYPEC_MASK GENMASK(7, 5) |
| 479 | #define UFP_TYPEC_RDSTD_BIT BIT(7) |
| 480 | #define UFP_TYPEC_RD1P5_BIT BIT(6) |
| 481 | #define UFP_TYPEC_RD3P0_BIT BIT(5) |
| 482 | #define UFP_TYPEC_FMB_255K_BIT BIT(4) |
| 483 | #define UFP_TYPEC_FMB_301K_BIT BIT(3) |
| 484 | #define UFP_TYPEC_FMB_523K_BIT BIT(2) |
| 485 | #define UFP_TYPEC_FMB_619K_BIT BIT(1) |
| 486 | #define UFP_TYPEC_OPEN_OPEN_BIT BIT(0) |
| 487 | |
| 488 | #define TYPE_C_STATUS_2_REG (USBIN_BASE + 0x0C) |
Nicholas Troast | 9688605 | 2016-02-25 15:42:17 -0800 | [diff] [blame] | 489 | #define DFP_RA_OPEN_BIT BIT(7) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 490 | #define TIMER_STAGE_BIT BIT(6) |
| 491 | #define EXIT_UFP_MODE_BIT BIT(5) |
| 492 | #define EXIT_DFP_MODE_BIT BIT(4) |
Nicholas Troast | e1932e4 | 2017-04-12 12:38:18 -0700 | [diff] [blame] | 493 | #define DFP_TYPEC_MASK GENMASK(3, 0) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 494 | #define DFP_RD_OPEN_BIT BIT(3) |
| 495 | #define DFP_RD_RA_VCONN_BIT BIT(2) |
| 496 | #define DFP_RD_RD_BIT BIT(1) |
| 497 | #define DFP_RA_RA_BIT BIT(0) |
| 498 | |
| 499 | #define TYPE_C_STATUS_3_REG (USBIN_BASE + 0x0D) |
| 500 | #define ENABLE_BANDGAP_BIT BIT(7) |
Ashay Jaiswal | 4aa2c0c | 2016-12-07 19:39:38 +0530 | [diff] [blame] | 501 | #define U_USB_GND_NOVBUS_BIT BIT(6) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 502 | #define U_USB_FLOAT_NOVBUS_BIT BIT(5) |
Ashay Jaiswal | 4aa2c0c | 2016-12-07 19:39:38 +0530 | [diff] [blame] | 503 | #define U_USB_GND_BIT BIT(4) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 504 | #define U_USB_FMB1_BIT BIT(3) |
| 505 | #define U_USB_FLOAT1_BIT BIT(2) |
| 506 | #define U_USB_FMB2_BIT BIT(1) |
| 507 | #define U_USB_FLOAT2_BIT BIT(0) |
| 508 | |
| 509 | #define TYPE_C_STATUS_4_REG (USBIN_BASE + 0x0E) |
| 510 | #define UFP_DFP_MODE_STATUS_BIT BIT(7) |
| 511 | #define TYPEC_VBUS_STATUS_BIT BIT(6) |
| 512 | #define TYPEC_VBUS_ERROR_STATUS_BIT BIT(5) |
| 513 | #define TYPEC_DEBOUNCE_DONE_STATUS_BIT BIT(4) |
| 514 | #define TYPEC_UFP_AUDIO_ADAPT_STATUS_BIT BIT(3) |
| 515 | #define TYPEC_VCONN_OVERCURR_STATUS_BIT BIT(2) |
| 516 | #define CC_ORIENTATION_BIT BIT(1) |
| 517 | #define CC_ATTACHED_BIT BIT(0) |
| 518 | |
Abhijeet Dharmapurikar | a8075d7 | 2016-10-06 12:59:04 -0700 | [diff] [blame] | 519 | #define TYPE_C_STATUS_5_REG (USBIN_BASE + 0x0F) |
| 520 | #define TRY_SOURCE_FAILED_BIT BIT(6) |
| 521 | #define TRY_SINK_FAILED_BIT BIT(5) |
| 522 | #define TIMER_STAGE_2_BIT BIT(4) |
| 523 | #define TYPEC_LEGACY_CABLE_STATUS_BIT BIT(3) |
| 524 | #define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(2) |
| 525 | #define TYPEC_TRYSOURCE_DETECT_STATUS_BIT BIT(1) |
| 526 | #define TYPEC_TRYSINK_DETECT_STATUS_BIT BIT(0) |
| 527 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 528 | /* USBIN Interrupt Bits */ |
| 529 | #define TYPE_C_CHANGE_RT_STS_BIT BIT(7) |
| 530 | #define USBIN_ICL_CHANGE_RT_STS_BIT BIT(6) |
| 531 | #define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(5) |
| 532 | #define USBIN_PLUGIN_RT_STS_BIT BIT(4) |
| 533 | #define USBIN_OV_RT_STS_BIT BIT(3) |
| 534 | #define USBIN_UV_RT_STS_BIT BIT(2) |
| 535 | #define USBIN_LT_3P6V_RT_STS_BIT BIT(1) |
| 536 | #define USBIN_COLLAPSE_RT_STS_BIT BIT(0) |
| 537 | |
Ashay Jaiswal | 6d308da | 2017-02-18 09:59:23 +0530 | [diff] [blame] | 538 | #define QC_PULSE_COUNT_STATUS_1_REG (USBIN_BASE + 0x30) |
| 539 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 540 | #define USBIN_CMD_IL_REG (USBIN_BASE + 0x40) |
| 541 | #define BAT_2_SYS_FET_DIS_BIT BIT(1) |
| 542 | #define USBIN_SUSPEND_BIT BIT(0) |
| 543 | |
| 544 | #define CMD_APSD_REG (USBIN_BASE + 0x41) |
| 545 | #define ICL_OVERRIDE_BIT BIT(1) |
| 546 | #define APSD_RERUN_BIT BIT(0) |
| 547 | |
| 548 | #define CMD_HVDCP_2_REG (USBIN_BASE + 0x43) |
Ashay Jaiswal | 6d308da | 2017-02-18 09:59:23 +0530 | [diff] [blame] | 549 | #define RESTART_AICL_BIT BIT(7) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 550 | #define TRIGGER_AICL_BIT BIT(6) |
| 551 | #define FORCE_12V_BIT BIT(5) |
| 552 | #define FORCE_9V_BIT BIT(4) |
| 553 | #define FORCE_5V_BIT BIT(3) |
| 554 | #define IDLE_BIT BIT(2) |
| 555 | #define SINGLE_DECREMENT_BIT BIT(1) |
| 556 | #define SINGLE_INCREMENT_BIT BIT(0) |
| 557 | |
| 558 | #define USB_MISC2_REG (USBIN_BASE + 0x57) |
| 559 | #define USB_MISC2_MASK GENMASK(1, 0) |
| 560 | |
| 561 | #define TYPE_C_CFG_REG (USBIN_BASE + 0x58) |
| 562 | #define APSD_START_ON_CC_BIT BIT(7) |
| 563 | #define WAIT_FOR_APSD_BIT BIT(6) |
| 564 | #define FACTORY_MODE_DETECTION_EN_BIT BIT(5) |
| 565 | #define FACTORY_MODE_ICL_3A_4A_BIT BIT(4) |
| 566 | #define FACTORY_MODE_DIS_CHGING_CFG_BIT BIT(3) |
| 567 | #define SUSPEND_NON_COMPLIANT_CFG_BIT BIT(2) |
| 568 | #define VCONN_OC_CFG_BIT BIT(1) |
| 569 | #define TYPE_C_OR_U_USB_BIT BIT(0) |
| 570 | |
| 571 | #define TYPE_C_CFG_2_REG (USBIN_BASE + 0x59) |
| 572 | #define TYPE_C_DFP_CURRSRC_MODE_BIT BIT(7) |
| 573 | #define VCONN_ILIM500MA_CFG_BIT BIT(6) |
| 574 | #define VCONN_SOFTSTART_CFG_MASK GENMASK(5, 4) |
| 575 | #define EN_TRY_SOURCE_MODE_BIT BIT(3) |
| 576 | #define USB_FACTORY_MODE_ENABLE_BIT BIT(2) |
| 577 | #define TYPE_C_UFP_MODE_BIT BIT(1) |
| 578 | #define EN_80UA_180UA_CUR_SOURCE_BIT BIT(0) |
| 579 | |
Abhijeet Dharmapurikar | a8075d7 | 2016-10-06 12:59:04 -0700 | [diff] [blame] | 580 | #define TYPE_C_CFG_3_REG (USBIN_BASE + 0x5A) |
| 581 | #define TVBUS_DEBOUNCE_BIT BIT(7) |
| 582 | #define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(6) |
| 583 | #define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT BIT(5) |
| 584 | #define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(4) |
| 585 | #define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(3) |
| 586 | #define EN_TRYSINK_MODE_BIT BIT(2) |
| 587 | #define EN_LEGACY_CABLE_DETECTION_BIT BIT(1) |
| 588 | #define ALLOW_PD_DRING_UFP_TCCDB_BIT BIT(0) |
| 589 | |
Harry Yang | 3d515b8 | 2018-04-06 16:01:04 -0700 | [diff] [blame] | 590 | #define HVDCP_PULSE_COUNT_MAX_REG (USBIN_BASE + 0x5B) |
| 591 | #define HVDCP_PULSE_COUNT_MAX_QC2_MASK GENMASK(7, 6) |
| 592 | enum { |
| 593 | HVDCP_PULSE_COUNT_MAX_QC2_5V, |
| 594 | HVDCP_PULSE_COUNT_MAX_QC2_9V, |
| 595 | HVDCP_PULSE_COUNT_MAX_QC2_12V, |
| 596 | HVDCP_PULSE_COUNT_MAX_QC2_INVALID |
| 597 | }; |
| 598 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 599 | #define USBIN_ADAPTER_ALLOW_CFG_REG (USBIN_BASE + 0x60) |
| 600 | #define USBIN_ADAPTER_ALLOW_MASK GENMASK(3, 0) |
| 601 | enum { |
| 602 | USBIN_ADAPTER_ALLOW_5V = 0, |
| 603 | USBIN_ADAPTER_ALLOW_9V = 2, |
| 604 | USBIN_ADAPTER_ALLOW_5V_OR_9V = 3, |
| 605 | USBIN_ADAPTER_ALLOW_12V = 4, |
| 606 | USBIN_ADAPTER_ALLOW_5V_OR_12V = 5, |
| 607 | USBIN_ADAPTER_ALLOW_9V_TO_12V = 6, |
| 608 | USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V = 7, |
| 609 | USBIN_ADAPTER_ALLOW_5V_TO_9V = 8, |
| 610 | USBIN_ADAPTER_ALLOW_5V_TO_12V = 12, |
| 611 | }; |
| 612 | |
| 613 | #define USBIN_OPTIONS_1_CFG_REG (USBIN_BASE + 0x62) |
| 614 | #define CABLE_R_SEL_BIT BIT(7) |
| 615 | #define HVDCP_AUTH_ALG_EN_CFG_BIT BIT(6) |
| 616 | #define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT BIT(5) |
| 617 | #define INPUT_PRIORITY_BIT BIT(4) |
| 618 | #define AUTO_SRC_DETECT_BIT BIT(3) |
| 619 | #define HVDCP_EN_BIT BIT(2) |
| 620 | #define VADP_INCREMENT_VOLTAGE_LIMIT_BIT BIT(1) |
| 621 | #define VADP_TAPER_TIMER_EN_BIT BIT(0) |
| 622 | |
| 623 | #define USBIN_OPTIONS_2_CFG_REG (USBIN_BASE + 0x63) |
| 624 | #define WIPWR_RST_EUD_CFG_BIT BIT(7) |
| 625 | #define SWITCHER_START_CFG_BIT BIT(6) |
| 626 | #define DCD_TIMEOUT_SEL_BIT BIT(5) |
| 627 | #define OCD_CURRENT_SEL_BIT BIT(4) |
| 628 | #define SLOW_PLUGIN_TIMER_EN_CFG_BIT BIT(3) |
Nicholas Troast | 597acfe | 2016-07-20 16:03:15 -0700 | [diff] [blame] | 629 | #define FLOAT_OPTIONS_MASK GENMASK(2, 0) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 630 | #define FLOAT_DIS_CHGING_CFG_BIT BIT(2) |
| 631 | #define SUSPEND_FLOAT_CFG_BIT BIT(1) |
| 632 | #define FORCE_FLOAT_SDP_CFG_BIT BIT(0) |
| 633 | |
| 634 | #define TAPER_TIMER_SEL_CFG_REG (USBIN_BASE + 0x64) |
Harry Yang | 88acff4 | 2016-09-21 14:56:06 -0700 | [diff] [blame] | 635 | #define TYPEC_SPARE_CFG_BIT BIT(7) |
Harry Yang | 8bdaa32 | 2017-10-03 13:56:55 -0700 | [diff] [blame] | 636 | #define TYPEC_DRP_DFP_TIME_CFG_BIT BIT(5) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 637 | #define TAPER_TIMER_SEL_MASK GENMASK(1, 0) |
| 638 | |
| 639 | #define USBIN_LOAD_CFG_REG (USBIN_BASE + 0x65) |
| 640 | #define USBIN_OV_CH_LOAD_OPTION_BIT BIT(7) |
Nicholas Troast | 11af51b | 2017-03-15 10:45:28 -0700 | [diff] [blame] | 641 | #define ICL_OVERRIDE_AFTER_APSD_BIT BIT(4) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 642 | |
| 643 | #define USBIN_ICL_OPTIONS_REG (USBIN_BASE + 0x66) |
| 644 | #define CFG_USB3P0_SEL_BIT BIT(2) |
| 645 | #define USB51_MODE_BIT BIT(1) |
| 646 | #define USBIN_MODE_CHG_BIT BIT(0) |
| 647 | |
| 648 | #define TYPE_C_INTRPT_ENB_REG (USBIN_BASE + 0x67) |
| 649 | #define TYPEC_CCOUT_DETACH_INT_EN_BIT BIT(7) |
| 650 | #define TYPEC_CCOUT_ATTACH_INT_EN_BIT BIT(6) |
| 651 | #define TYPEC_VBUS_ERROR_INT_EN_BIT BIT(5) |
| 652 | #define TYPEC_UFP_AUDIOADAPT_INT_EN_BIT BIT(4) |
| 653 | #define TYPEC_DEBOUNCE_DONE_INT_EN_BIT BIT(3) |
| 654 | #define TYPEC_CCSTATE_CHANGE_INT_EN_BIT BIT(2) |
| 655 | #define TYPEC_VBUS_DEASSERT_INT_EN_BIT BIT(1) |
| 656 | #define TYPEC_VBUS_ASSERT_INT_EN_BIT BIT(0) |
| 657 | |
| 658 | #define TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG (USBIN_BASE + 0x68) |
Abhijeet Dharmapurikar | f8a7a4a | 2016-10-07 18:46:45 -0700 | [diff] [blame] | 659 | #define EXIT_SNK_BASED_ON_CC_BIT BIT(7) |
Harry Yang | 88acff4 | 2016-09-21 14:56:06 -0700 | [diff] [blame] | 660 | #define VCONN_EN_ORIENTATION_BIT BIT(6) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 661 | #define TYPEC_VCONN_OVERCURR_INT_EN_BIT BIT(5) |
| 662 | #define VCONN_EN_SRC_BIT BIT(4) |
| 663 | #define VCONN_EN_VALUE_BIT BIT(3) |
| 664 | #define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0) |
| 665 | #define UFP_EN_CMD_BIT BIT(2) |
| 666 | #define DFP_EN_CMD_BIT BIT(1) |
| 667 | #define TYPEC_DISABLE_CMD_BIT BIT(0) |
| 668 | |
| 669 | #define USBIN_SOURCE_CHANGE_INTRPT_ENB_REG (USBIN_BASE + 0x69) |
| 670 | #define SLOW_IRQ_EN_CFG_BIT BIT(5) |
| 671 | #define ENUMERATION_IRQ_EN_CFG_BIT BIT(4) |
| 672 | #define VADP_IRQ_EN_CFG_BIT BIT(3) |
| 673 | #define AUTH_IRQ_EN_CFG_BIT BIT(2) |
| 674 | #define HVDCP_IRQ_EN_CFG_BIT BIT(1) |
| 675 | #define APSD_IRQ_EN_CFG_BIT BIT(0) |
| 676 | |
| 677 | #define USBIN_CURRENT_LIMIT_CFG_REG (USBIN_BASE + 0x70) |
| 678 | #define USBIN_CURRENT_LIMIT_MASK GENMASK(7, 0) |
| 679 | |
| 680 | #define USBIN_AICL_OPTIONS_CFG_REG (USBIN_BASE + 0x80) |
| 681 | #define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7) |
| 682 | #define USBIN_AICL_HDC_EN_BIT BIT(6) |
| 683 | #define USBIN_AICL_START_AT_MAX_BIT BIT(5) |
| 684 | #define USBIN_AICL_RERUN_EN_BIT BIT(4) |
| 685 | #define USBIN_AICL_ADC_EN_BIT BIT(3) |
| 686 | #define USBIN_AICL_EN_BIT BIT(2) |
| 687 | #define USBIN_HV_COLLAPSE_RESPONSE_BIT BIT(1) |
| 688 | #define USBIN_LV_COLLAPSE_RESPONSE_BIT BIT(0) |
| 689 | |
| 690 | #define USBIN_5V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x81) |
| 691 | #define USBIN_5V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0) |
| 692 | |
| 693 | #define USBIN_9V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x82) |
| 694 | #define USBIN_9V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0) |
| 695 | |
| 696 | #define USBIN_12V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x83) |
| 697 | #define USBIN_12V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0) |
| 698 | |
| 699 | #define USBIN_CONT_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x84) |
| 700 | #define USBIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0) |
| 701 | |
| 702 | /* DCIN Peripheral Registers */ |
| 703 | #define DCIN_INPUT_STATUS_REG (DCIN_BASE + 0x06) |
| 704 | #define DCIN_INPUT_STATUS_7_BIT BIT(7) |
| 705 | #define DCIN_INPUT_STATUS_6_BIT BIT(6) |
| 706 | #define DCIN_12V_BIT BIT(5) |
| 707 | #define DCIN_9V_TO_12V_BIT BIT(4) |
| 708 | #define DCIN_9V_BIT BIT(3) |
| 709 | #define DCIN_5V_TO_12V_BIT BIT(2) |
| 710 | #define DCIN_5V_TO_9V_BIT BIT(1) |
| 711 | #define DCIN_5V_BIT BIT(0) |
| 712 | |
| 713 | #define WIPWR_STATUS_REG (DCIN_BASE + 0x07) |
| 714 | #define WIPWR_STATUS_7_BIT BIT(7) |
| 715 | #define WIPWR_STATUS_6_BIT BIT(6) |
| 716 | #define WIPWR_STATUS_5_BIT BIT(5) |
| 717 | #define DCIN_WIPWR_OV_DG_BIT BIT(4) |
| 718 | #define DIV2_EN_DG_BIT BIT(3) |
| 719 | #define SHUTDOWN_N_LATCH_BIT BIT(2) |
| 720 | #define CHG_OK_PIN_BIT BIT(1) |
| 721 | #define WIPWR_CHARGING_ENABLED_BIT BIT(0) |
| 722 | |
| 723 | #define WIPWR_RANGE_STATUS_REG (DCIN_BASE + 0x08) |
| 724 | #define WIPWR_RANGE_STATUS_MASK GENMASK(4, 0) |
| 725 | |
| 726 | /* DCIN Interrupt Bits */ |
| 727 | #define WIPWR_VOLTAGE_RANGE_RT_STS_BIT BIT(7) |
| 728 | #define DCIN_ICL_CHANGE_RT_STS_BIT BIT(6) |
| 729 | #define DIV2_EN_DG_RT_STS_BIT BIT(5) |
| 730 | #define DCIN_PLUGIN_RT_STS_BIT BIT(4) |
| 731 | #define DCIN_OV_RT_STS_BIT BIT(3) |
| 732 | #define DCIN_UV_RT_STS_BIT BIT(2) |
| 733 | #define DCIN_LT_3P6V_RT_STS_BIT BIT(1) |
| 734 | #define DCIN_COLLAPSE_RT_STS_BIT BIT(0) |
| 735 | |
| 736 | #define DCIN_CMD_IL_REG (DCIN_BASE + 0x40) |
| 737 | #define WIRELESS_CHG_DIS_BIT BIT(3) |
| 738 | #define SHDN_N_CLEAR_CMD_BIT BIT(2) |
| 739 | #define SHDN_N_SET_CMD_BIT BIT(1) |
| 740 | #define DCIN_SUSPEND_BIT BIT(0) |
| 741 | |
| 742 | #define DC_SPARE_REG (DCIN_BASE + 0x58) |
| 743 | #define DC_SPARE_MASK GENMASK(3, 0) |
| 744 | |
| 745 | #define DCIN_ADAPTER_ALLOW_CFG_REG (DCIN_BASE + 0x60) |
| 746 | #define DCIN_ADAPTER_ALLOW_MASK GENMASK(3, 0) |
| 747 | |
| 748 | #define DCIN_LOAD_CFG_REG (DCIN_BASE + 0x65) |
| 749 | #define DCIN_OV_CH_LOAD_OPTION_BIT BIT(7) |
| 750 | |
| 751 | #define DCIN_CURRENT_LIMIT_CFG_REG (DCIN_BASE + 0x70) |
| 752 | #define DCIN_CURRENT_LIMIT_MASK GENMASK(7, 0) |
| 753 | |
| 754 | #define DCIN_AICL_OPTIONS_CFG_REG (DCIN_BASE + 0x80) |
| 755 | #define SUSPEND_ON_COLLAPSE_DCIN_BIT BIT(7) |
| 756 | #define DCIN_AICL_HDC_EN_BIT BIT(6) |
| 757 | #define DCIN_AICL_START_AT_MAX_BIT BIT(5) |
| 758 | #define DCIN_AICL_RERUN_EN_BIT BIT(4) |
| 759 | #define DCIN_AICL_ADC_EN_BIT BIT(3) |
| 760 | #define DCIN_AICL_EN_BIT BIT(2) |
| 761 | #define DCIN_HV_COLLAPSE_RESPONSE_BIT BIT(1) |
| 762 | #define DCIN_LV_COLLAPSE_RESPONSE_BIT BIT(0) |
| 763 | |
| 764 | #define DCIN_AICL_REF_SEL_CFG_REG (DCIN_BASE + 0x81) |
| 765 | #define DCIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0) |
| 766 | |
| 767 | #define DCIN_ICL_START_CFG_REG (DCIN_BASE + 0x82) |
| 768 | #define DCIN_ICL_START_CFG_BIT BIT(0) |
| 769 | |
| 770 | #define DIV2_EN_GF_TIME_CFG_REG (DCIN_BASE + 0x90) |
| 771 | #define DIV2_EN_GF_TIME_CFG_MASK GENMASK(1, 0) |
| 772 | |
| 773 | #define WIPWR_IRQ_TMR_CFG_REG (DCIN_BASE + 0x91) |
| 774 | #define WIPWR_IRQ_TMR_MASK GENMASK(2, 0) |
| 775 | |
| 776 | #define ZIN_ICL_PT_REG (DCIN_BASE + 0x92) |
| 777 | #define ZIN_ICL_PT_MASK GENMASK(7, 0) |
| 778 | |
| 779 | #define ZIN_ICL_LV_REG (DCIN_BASE + 0x93) |
| 780 | #define ZIN_ICL_LV_MASK GENMASK(7, 0) |
| 781 | |
| 782 | #define ZIN_ICL_HV_REG (DCIN_BASE + 0x94) |
| 783 | #define ZIN_ICL_HV_MASK GENMASK(7, 0) |
| 784 | |
| 785 | #define WI_PWR_OPTIONS_REG (DCIN_BASE + 0x95) |
| 786 | #define CHG_OK_BIT BIT(7) |
| 787 | #define WIPWR_UVLO_IRQ_OPT_BIT BIT(6) |
| 788 | #define BUCK_HOLDOFF_ENABLE_BIT BIT(5) |
| 789 | #define CHG_OK_HW_SW_SELECT_BIT BIT(4) |
| 790 | #define WIPWR_RST_ENABLE_BIT BIT(3) |
| 791 | #define DCIN_WIPWR_IRQ_SELECT_BIT BIT(2) |
| 792 | #define AICL_SWITCH_ENABLE_BIT BIT(1) |
| 793 | #define ZIN_ICL_ENABLE_BIT BIT(0) |
| 794 | |
| 795 | #define ZIN_ICL_PT_HV_REG (DCIN_BASE + 0x96) |
| 796 | #define ZIN_ICL_PT_HV_MASK GENMASK(7, 0) |
| 797 | |
| 798 | #define ZIN_ICL_MID_LV_REG (DCIN_BASE + 0x97) |
| 799 | #define ZIN_ICL_MID_LV_MASK GENMASK(7, 0) |
| 800 | |
| 801 | #define ZIN_ICL_MID_HV_REG (DCIN_BASE + 0x98) |
| 802 | #define ZIN_ICL_MID_HV_MASK GENMASK(7, 0) |
| 803 | |
Abhijeet Dharmapurikar | 5cf5faf | 2016-06-21 14:20:24 -0700 | [diff] [blame] | 804 | enum { |
| 805 | ZIN_ICL_PT_MAX_MV = 8000, |
| 806 | ZIN_ICL_PT_HV_MAX_MV = 9000, |
| 807 | ZIN_ICL_LV_MAX_MV = 5500, |
| 808 | ZIN_ICL_MID_LV_MAX_MV = 6500, |
| 809 | ZIN_ICL_MID_HV_MAX_MV = 8000, |
| 810 | ZIN_ICL_HV_MAX_MV = 11000, |
| 811 | }; |
| 812 | |
Nicholas Troast | b11015f | 2017-01-17 17:56:45 -0800 | [diff] [blame] | 813 | #define DC_ENG_SSUPPLY_CFG2_REG (DCIN_BASE + 0xC1) |
| 814 | #define ENG_SSUPPLY_IVREF_OTG_SS_MASK GENMASK(2, 0) |
| 815 | #define OTG_SS_SLOW 0x3 |
| 816 | |
Harry Yang | 360bd53 | 2016-09-26 11:03:22 -0700 | [diff] [blame] | 817 | #define DC_ENG_SSUPPLY_CFG3_REG (DCIN_BASE + 0xC2) |
| 818 | #define ENG_SSUPPLY_HI_CAP_BIT BIT(6) |
| 819 | #define ENG_SSUPPLY_HI_RES_BIT BIT(5) |
| 820 | #define ENG_SSUPPLY_CFG_SKIP_TH_V0P2_BIT BIT(3) |
| 821 | #define ENG_SSUPPLY_CFG_SYSOV_TH_4P8_BIT BIT(2) |
| 822 | #define ENG_SSUPPLY_5V_OV_OPT_BIT BIT(0) |
| 823 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 824 | /* MISC Peripheral Registers */ |
| 825 | #define REVISION1_REG (MISC_BASE + 0x00) |
| 826 | #define DIG_MINOR_MASK GENMASK(7, 0) |
| 827 | |
| 828 | #define REVISION2_REG (MISC_BASE + 0x01) |
| 829 | #define DIG_MAJOR_MASK GENMASK(7, 0) |
| 830 | |
| 831 | #define REVISION3_REG (MISC_BASE + 0x02) |
| 832 | #define ANA_MINOR_MASK GENMASK(7, 0) |
| 833 | |
| 834 | #define REVISION4_REG (MISC_BASE + 0x03) |
| 835 | #define ANA_MAJOR_MASK GENMASK(7, 0) |
| 836 | |
| 837 | #define TEMP_RANGE_STATUS_REG (MISC_BASE + 0x06) |
| 838 | #define TEMP_RANGE_STATUS_7_BIT BIT(7) |
| 839 | #define THERM_REG_ACTIVE_BIT BIT(6) |
| 840 | #define TLIM_BIT BIT(5) |
Nicholas Troast | b021dd9 | 2017-01-31 18:43:38 -0800 | [diff] [blame] | 841 | #define TEMP_RANGE_MASK GENMASK(4, 1) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 842 | #define ALERT_LEVEL_BIT BIT(4) |
| 843 | #define TEMP_ABOVE_RANGE_BIT BIT(3) |
| 844 | #define TEMP_WITHIN_RANGE_BIT BIT(2) |
| 845 | #define TEMP_BELOW_RANGE_BIT BIT(1) |
| 846 | #define THERMREG_DISABLED_BIT BIT(0) |
| 847 | |
| 848 | #define ICL_STATUS_REG (MISC_BASE + 0x07) |
| 849 | #define INPUT_CURRENT_LIMIT_MASK GENMASK(7, 0) |
| 850 | |
| 851 | #define ADAPTER_5V_ICL_STATUS_REG (MISC_BASE + 0x08) |
| 852 | #define ADAPTER_5V_ICL_MASK GENMASK(7, 0) |
| 853 | |
| 854 | #define ADAPTER_9V_ICL_STATUS_REG (MISC_BASE + 0x09) |
| 855 | #define ADAPTER_9V_ICL_MASK GENMASK(7, 0) |
| 856 | |
| 857 | #define AICL_STATUS_REG (MISC_BASE + 0x0A) |
| 858 | #define AICL_STATUS_7_BIT BIT(7) |
| 859 | #define SOFT_ILIMIT_BIT BIT(6) |
| 860 | #define HIGHEST_DC_BIT BIT(5) |
| 861 | #define USBIN_CH_COLLAPSE_BIT BIT(4) |
| 862 | #define DCIN_CH_COLLAPSE_BIT BIT(3) |
| 863 | #define ICL_IMIN_BIT BIT(2) |
| 864 | #define AICL_FAIL_BIT BIT(1) |
| 865 | #define AICL_DONE_BIT BIT(0) |
| 866 | |
| 867 | #define POWER_PATH_STATUS_REG (MISC_BASE + 0x0B) |
| 868 | #define INPUT_SS_DONE_BIT BIT(7) |
| 869 | #define USBIN_SUSPEND_STS_BIT BIT(6) |
| 870 | #define DCIN_SUSPEND_STS_BIT BIT(5) |
| 871 | #define USE_USBIN_BIT BIT(4) |
| 872 | #define USE_DCIN_BIT BIT(3) |
| 873 | #define POWER_PATH_MASK GENMASK(2, 1) |
| 874 | #define VALID_INPUT_POWER_SOURCE_STS_BIT BIT(0) |
| 875 | |
| 876 | #define WDOG_STATUS_REG (MISC_BASE + 0x0C) |
| 877 | #define WDOG_STATUS_7_BIT BIT(7) |
| 878 | #define WDOG_STATUS_6_BIT BIT(6) |
| 879 | #define WDOG_STATUS_5_BIT BIT(5) |
| 880 | #define WDOG_STATUS_4_BIT BIT(4) |
| 881 | #define WDOG_STATUS_3_BIT BIT(3) |
| 882 | #define WDOG_STATUS_2_BIT BIT(2) |
| 883 | #define WDOG_STATUS_1_BIT BIT(1) |
| 884 | #define BARK_BITE_STATUS_BIT BIT(0) |
| 885 | |
Harry Yang | 3b113a5 | 2016-12-08 12:37:40 -0800 | [diff] [blame] | 886 | #define SYSOK_REASON_STATUS_REG (MISC_BASE + 0x0D) |
| 887 | #define SYSOK_REASON_DCIN_BIT BIT(1) |
| 888 | #define SYSOK_REASON_USBIN_BIT BIT(0) |
| 889 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 890 | /* MISC Interrupt Bits */ |
| 891 | #define SWITCHER_POWER_OK_RT_STS_BIT BIT(7) |
| 892 | #define TEMPERATURE_CHANGE_RT_STS_BIT BIT(6) |
| 893 | #define INPUT_CURRENT_LIMITING_RT_STS_BIT BIT(5) |
| 894 | #define HIGH_DUTY_CYCLE_RT_STS_BIT BIT(4) |
| 895 | #define AICL_DONE_RT_STS_BIT BIT(3) |
| 896 | #define AICL_FAIL_RT_STS_BIT BIT(2) |
| 897 | #define WDOG_BARK_RT_STS_BIT BIT(1) |
| 898 | #define WDOG_SNARL_RT_STS_BIT BIT(0) |
| 899 | |
| 900 | #define WDOG_RST_REG (MISC_BASE + 0x40) |
| 901 | #define WDOG_RST_BIT BIT(0) |
| 902 | |
| 903 | #define AFP_MODE_REG (MISC_BASE + 0x41) |
| 904 | #define AFP_MODE_EN_BIT BIT(0) |
| 905 | |
| 906 | #define GSM_PA_ON_ADJ_EN_REG (MISC_BASE + 0x42) |
| 907 | #define GSM_PA_ON_ADJ_EN_BIT BIT(0) |
| 908 | |
| 909 | #define BARK_BITE_WDOG_PET_REG (MISC_BASE + 0x43) |
| 910 | #define BARK_BITE_WDOG_PET_BIT BIT(0) |
| 911 | |
| 912 | #define PHYON_CMD_REG (MISC_BASE + 0x44) |
| 913 | #define PHYON_CMD_BIT BIT(0) |
| 914 | |
| 915 | #define SHDN_CMD_REG (MISC_BASE + 0x45) |
| 916 | #define SHDN_CMD_BIT BIT(0) |
| 917 | |
| 918 | #define FINISH_COPY_COMMAND_REG (MISC_BASE + 0x4F) |
| 919 | #define START_COPY_BIT BIT(0) |
| 920 | |
| 921 | #define WD_CFG_REG (MISC_BASE + 0x51) |
| 922 | #define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7) |
| 923 | #define BARK_WDOG_INT_EN_BIT BIT(6) |
| 924 | #define BITE_WDOG_INT_EN_BIT BIT(5) |
| 925 | #define SFT_AFTER_WDOG_IRQ_MASK GENMASK(4, 3) |
| 926 | #define WDOG_IRQ_SFT_BIT BIT(2) |
Nicholas Troast | 15dc0c8 | 2016-10-18 15:15:21 -0700 | [diff] [blame] | 927 | #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 928 | #define WDOG_TIMER_EN_BIT BIT(0) |
| 929 | |
| 930 | #define MISC_CFG_REG (MISC_BASE + 0x52) |
| 931 | #define GSM_PA_ON_ADJ_SEL_BIT BIT(0) |
Ashay Jaiswal | d633b92 | 2017-03-21 22:46:06 +0530 | [diff] [blame] | 932 | #define STAT_PARALLEL_1400MA_EN_CFG_BIT BIT(3) |
Harry Yang | 755a34b | 2016-11-01 01:18:51 -0700 | [diff] [blame] | 933 | #define TCC_DEBOUNCE_20MS_BIT BIT(5) |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 934 | |
| 935 | #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53) |
| 936 | #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) |
| 937 | #define SNARL_WDOG_TIMEOUT_MASK GENMASK(6, 4) |
| 938 | #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) |
| 939 | #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) |
| 940 | |
| 941 | #define PHYON_CFG_REG (MISC_BASE + 0x54) |
| 942 | #define USBPHYON_PUSHPULL_CFG_BIT BIT(1) |
| 943 | #define PHYON_SW_SEL_BIT BIT(0) |
| 944 | |
| 945 | #define CHGR_TRIM_OPTIONS_7_0_REG (MISC_BASE + 0x55) |
| 946 | #define TLIM_DIS_TBIT_BIT BIT(0) |
| 947 | |
| 948 | #define CH_OV_OPTION_CFG_REG (MISC_BASE + 0x56) |
| 949 | #define OV_OPTION_TBIT_BIT BIT(0) |
| 950 | |
| 951 | #define AICL_CFG_REG (MISC_BASE + 0x60) |
| 952 | #define TREG_ALLOW_DECREASE_BIT BIT(1) |
| 953 | #define AICL_HIGH_DC_INC_BIT BIT(0) |
| 954 | |
| 955 | #define AICL_RERUN_TIME_CFG_REG (MISC_BASE + 0x61) |
| 956 | #define AICL_RERUN_TIME_MASK GENMASK(1, 0) |
| 957 | |
| 958 | #define AICL_RERUN_TEMP_TIME_CFG_REG (MISC_BASE + 0x62) |
| 959 | #define AICL_RERUN_TEMP_TIME_MASK GENMASK(1, 0) |
| 960 | |
| 961 | #define THERMREG_SRC_CFG_REG (MISC_BASE + 0x70) |
| 962 | #define SKIN_ADC_CFG_BIT BIT(3) |
| 963 | #define THERMREG_SKIN_ADC_SRC_EN_BIT BIT(2) |
| 964 | #define THERMREG_DIE_ADC_SRC_EN_BIT BIT(1) |
| 965 | #define THERMREG_DIE_CMP_SRC_EN_BIT BIT(0) |
| 966 | |
| 967 | #define TREG_DIE_CMP_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x71) |
| 968 | #define TREG_DIE_CMP_INC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 969 | |
| 970 | #define TREG_DIE_CMP_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x72) |
| 971 | #define TREG_DIE_CMP_DEC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 972 | |
| 973 | #define TREG_DIE_ADC_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x73) |
| 974 | #define TREG_DIE_ADC_INC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 975 | |
| 976 | #define TREG_DIE_ADC_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x74) |
| 977 | #define TREG_DIE_ADC_DEC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 978 | |
| 979 | #define TREG_SKIN_ADC_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x75) |
| 980 | #define TREG_SKIN_ADC_INC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 981 | |
| 982 | #define TREG_SKIN_ADC_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x76) |
| 983 | #define TREG_SKIN_ADC_DEC_CYCLE_TIME_MASK GENMASK(1, 0) |
| 984 | |
| 985 | #define BUCK_OPTIONS_CFG_REG (MISC_BASE + 0x80) |
| 986 | #define CHG_EN_PIN_SUSPEND_CFG_BIT BIT(6) |
| 987 | #define HICCUP_OPTIONS_MASK GENMASK(5, 4) |
| 988 | #define INPUT_CURRENT_LIMIT_SOFTSTART_EN_BIT BIT(3) |
| 989 | #define HV_HIGH_DUTY_CYCLE_PROTECT_EN_BIT BIT(2) |
| 990 | #define BUCK_OC_PROTECT_EN_BIT BIT(1) |
| 991 | #define INPUT_MISS_POLL_EN_BIT BIT(0) |
| 992 | |
| 993 | #define ICL_SOFTSTART_RATE_CFG_REG (MISC_BASE + 0x81) |
| 994 | #define ICL_SOFTSTART_RATE_MASK GENMASK(1, 0) |
| 995 | |
| 996 | #define ICL_SOFTSTOP_RATE_CFG_REG (MISC_BASE + 0x82) |
| 997 | #define ICL_SOFTSTOP_RATE_MASK GENMASK(1, 0) |
| 998 | |
| 999 | #define VSYS_MIN_SEL_CFG_REG (MISC_BASE + 0x83) |
| 1000 | #define VSYS_MIN_SEL_MASK GENMASK(1, 0) |
| 1001 | |
| 1002 | #define TRACKING_VOLTAGE_SEL_CFG_REG (MISC_BASE + 0x84) |
| 1003 | #define TRACKING_VOLTAGE_SEL_BIT BIT(0) |
| 1004 | |
| 1005 | #define STAT_CFG_REG (MISC_BASE + 0x90) |
| 1006 | #define STAT_SW_OVERRIDE_VALUE_BIT BIT(7) |
| 1007 | #define STAT_SW_OVERRIDE_CFG_BIT BIT(6) |
| 1008 | #define STAT_PARALLEL_OFF_DG_CFG_MASK GENMASK(5, 4) |
| 1009 | #define STAT_POLARITY_CFG_BIT BIT(3) |
| 1010 | #define STAT_PARALLEL_CFG_BIT BIT(2) |
| 1011 | #define STAT_FUNCTION_CFG_BIT BIT(1) |
| 1012 | #define STAT_IRQ_PULSING_EN_BIT BIT(0) |
| 1013 | |
| 1014 | #define LBC_EN_CFG_REG (MISC_BASE + 0x91) |
| 1015 | #define LBC_DURING_CHARGING_CFG_BIT BIT(1) |
| 1016 | #define LBC_EN_BIT BIT(0) |
| 1017 | |
| 1018 | #define LBC_PERIOD_CFG_REG (MISC_BASE + 0x92) |
| 1019 | #define LBC_PERIOD_MASK GENMASK(2, 0) |
| 1020 | |
| 1021 | #define LBC_DUTY_CYCLE_CFG_REG (MISC_BASE + 0x93) |
| 1022 | #define LBC_DUTY_CYCLE_MASK GENMASK(2, 0) |
| 1023 | |
| 1024 | #define SYSOK_CFG_REG (MISC_BASE + 0x94) |
| 1025 | #define SYSOK_PUSHPULL_CFG_BIT BIT(5) |
| 1026 | #define SYSOK_B_OR_C_SEL_BIT BIT(4) |
| 1027 | #define SYSOK_POL_BIT BIT(3) |
| 1028 | #define SYSOK_OPTIONS_MASK GENMASK(2, 0) |
| 1029 | |
Harry Yang | f6df8b0 | 2016-10-05 15:38:03 -0700 | [diff] [blame] | 1030 | #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0) |
Harry Yang | d89ff1f | 2016-12-05 14:59:11 -0800 | [diff] [blame] | 1031 | #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1) |
Harry Yang | f6df8b0 | 2016-10-05 15:38:03 -0700 | [diff] [blame] | 1032 | |
Jack Pham | 54a39bd | 2017-03-29 18:59:37 -0700 | [diff] [blame] | 1033 | #define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9) |
| 1034 | |
Nicholas Troast | 8f12c81 | 2017-08-22 17:57:25 -0700 | [diff] [blame] | 1035 | #define ENG_SDCDC_CFG7_REG (MISC_BASE + 0xC6) |
| 1036 | #define ENG_SDCDC_BST_SET_POINT_MASK GENMASK(7, 6) |
| 1037 | |
Anirudh Ghayal | 4da3df9 | 2017-01-25 18:55:57 +0530 | [diff] [blame] | 1038 | /* CHGR FREQ Peripheral registers */ |
| 1039 | #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50) |
| 1040 | |
Nicholas Troast | 34db503 | 2016-03-28 12:26:44 -0700 | [diff] [blame] | 1041 | #endif /* __SMB2_CHARGER_REG_H */ |