Yan He | 50222ad | 2017-11-17 18:22:17 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __MSM_EP_PCIE_H |
| 14 | #define __MSM_EP_PCIE_H |
| 15 | |
| 16 | #include <linux/types.h> |
| 17 | |
| 18 | enum ep_pcie_link_status { |
| 19 | EP_PCIE_LINK_DISABLED, |
| 20 | EP_PCIE_LINK_UP, |
| 21 | EP_PCIE_LINK_ENABLED, |
| 22 | }; |
| 23 | |
| 24 | enum ep_pcie_event { |
| 25 | EP_PCIE_EVENT_INVALID = 0, |
| 26 | EP_PCIE_EVENT_PM_D0 = 0x1, |
| 27 | EP_PCIE_EVENT_PM_D3_HOT = 0x2, |
| 28 | EP_PCIE_EVENT_PM_D3_COLD = 0x4, |
| 29 | EP_PCIE_EVENT_PM_RST_DEAST = 0x8, |
| 30 | EP_PCIE_EVENT_LINKDOWN = 0x10, |
| 31 | EP_PCIE_EVENT_LINKUP = 0x20, |
| 32 | EP_PCIE_EVENT_MHI_A7 = 0x40, |
| 33 | EP_PCIE_EVENT_MMIO_WRITE = 0x80, |
| 34 | }; |
| 35 | |
| 36 | enum ep_pcie_irq_event { |
| 37 | EP_PCIE_INT_EVT_LINK_DOWN = 1, |
| 38 | EP_PCIE_INT_EVT_BME, |
| 39 | EP_PCIE_INT_EVT_PM_TURNOFF, |
| 40 | EP_PCIE_INT_EVT_DEBUG, |
| 41 | EP_PCIE_INT_EVT_LTR, |
| 42 | EP_PCIE_INT_EVT_MHI_Q6, |
| 43 | EP_PCIE_INT_EVT_MHI_A7, |
| 44 | EP_PCIE_INT_EVT_DSTATE_CHANGE, |
| 45 | EP_PCIE_INT_EVT_L1SUB_TIMEOUT, |
| 46 | EP_PCIE_INT_EVT_MMIO_WRITE, |
| 47 | EP_PCIE_INT_EVT_CFG_WRITE, |
| 48 | EP_PCIE_INT_EVT_BRIDGE_FLUSH_N, |
| 49 | EP_PCIE_INT_EVT_LINK_UP, |
| 50 | EP_PCIE_INT_EVT_MAX = 13, |
| 51 | }; |
| 52 | |
| 53 | enum ep_pcie_trigger { |
| 54 | EP_PCIE_TRIGGER_CALLBACK, |
| 55 | EP_PCIE_TRIGGER_COMPLETION, |
| 56 | }; |
| 57 | |
| 58 | enum ep_pcie_options { |
| 59 | EP_PCIE_OPT_NULL = 0, |
| 60 | EP_PCIE_OPT_AST_WAKE = 0x1, |
| 61 | EP_PCIE_OPT_POWER_ON = 0x2, |
| 62 | EP_PCIE_OPT_ENUM = 0x4, |
| 63 | EP_PCIE_OPT_ENUM_ASYNC = 0x8, |
| 64 | EP_PCIE_OPT_ALL = 0xFFFFFFFF, |
| 65 | }; |
| 66 | |
| 67 | struct ep_pcie_notify { |
| 68 | enum ep_pcie_event event; |
| 69 | void *user; |
| 70 | void *data; |
| 71 | u32 options; |
| 72 | }; |
| 73 | |
| 74 | struct ep_pcie_register_event { |
| 75 | u32 events; |
| 76 | void *user; |
| 77 | enum ep_pcie_trigger mode; |
| 78 | void (*callback)(struct ep_pcie_notify *notify); |
| 79 | struct ep_pcie_notify notify; |
| 80 | struct completion *completion; |
| 81 | u32 options; |
| 82 | }; |
| 83 | |
| 84 | struct ep_pcie_iatu { |
| 85 | u32 start; |
| 86 | u32 end; |
| 87 | u32 tgt_lower; |
| 88 | u32 tgt_upper; |
| 89 | }; |
| 90 | |
| 91 | struct ep_pcie_msi_config { |
| 92 | u32 lower; |
| 93 | u32 upper; |
| 94 | u32 data; |
| 95 | u32 msg_num; |
| 96 | }; |
| 97 | |
| 98 | struct ep_pcie_db_config { |
| 99 | u8 base; |
| 100 | u8 end; |
| 101 | u32 tgt_addr; |
| 102 | }; |
| 103 | |
| 104 | struct ep_pcie_hw { |
| 105 | struct list_head node; |
| 106 | u32 device_id; |
| 107 | void **private_data; |
| 108 | int (*register_event)(struct ep_pcie_register_event *reg); |
| 109 | int (*deregister_event)(void); |
| 110 | enum ep_pcie_link_status (*get_linkstatus)(void); |
| 111 | int (*config_outbound_iatu)(struct ep_pcie_iatu entries[], |
| 112 | u32 num_entries); |
| 113 | int (*get_msi_config)(struct ep_pcie_msi_config *cfg); |
| 114 | int (*trigger_msi)(u32 idx); |
| 115 | int (*wakeup_host)(void); |
| 116 | int (*enable_endpoint)(enum ep_pcie_options opt); |
| 117 | int (*disable_endpoint)(void); |
| 118 | int (*config_db_routing)(struct ep_pcie_db_config chdb_cfg, |
| 119 | struct ep_pcie_db_config erdb_cfg); |
| 120 | int (*mask_irq_event)(enum ep_pcie_irq_event event, |
| 121 | bool enable); |
| 122 | }; |
| 123 | |
| 124 | /* |
| 125 | * ep_pcie_register_drv - register HW driver. |
| 126 | * @phandle: PCIe endpoint HW driver handle |
| 127 | * |
| 128 | * This function registers PCIe HW driver to PCIe endpoint service |
| 129 | * layer. |
| 130 | * |
| 131 | * Return: 0 on success, negative value on error |
| 132 | */ |
| 133 | int ep_pcie_register_drv(struct ep_pcie_hw *phandle); |
| 134 | |
| 135 | /* |
| 136 | * ep_pcie_deregister_drv - deregister HW driver. |
| 137 | * @phandle: PCIe endpoint HW driver handle |
| 138 | * |
| 139 | * This function deregisters PCIe HW driver to PCIe endpoint service |
| 140 | * layer. |
| 141 | * |
| 142 | * Return: 0 on success, negative value on error |
| 143 | */ |
| 144 | int ep_pcie_deregister_drv(struct ep_pcie_hw *phandle); |
| 145 | |
| 146 | /* |
| 147 | * ep_pcie_get_phandle - get PCIe endpoint HW driver handle. |
| 148 | * @id: PCIe endpoint device ID |
| 149 | * |
| 150 | * This function deregisters PCIe HW driver from PCIe endpoint service |
| 151 | * layer. |
| 152 | * |
| 153 | * Return: PCIe endpoint HW driver handle |
| 154 | */ |
| 155 | struct ep_pcie_hw *ep_pcie_get_phandle(u32 id); |
| 156 | |
| 157 | /* |
| 158 | * ep_pcie_register_event - register event with PCIe driver. |
| 159 | * @phandle: PCIe endpoint HW driver handle |
| 160 | * @reg: event structure |
| 161 | * |
| 162 | * This function gives PCIe client driver an option to register |
| 163 | * event with PCIe driver. |
| 164 | * |
| 165 | * Return: 0 on success, negative value on error |
| 166 | */ |
| 167 | int ep_pcie_register_event(struct ep_pcie_hw *phandle, |
| 168 | struct ep_pcie_register_event *reg); |
| 169 | |
| 170 | /* |
| 171 | * ep_pcie_deregister_event - deregister event with PCIe driver. |
| 172 | * @phandle: PCIe endpoint HW driver handle |
| 173 | * |
| 174 | * This function gives PCIe client driver an option to deregister |
| 175 | * existing event with PCIe driver. |
| 176 | * |
| 177 | * Return: 0 on success, negative value on error |
| 178 | */ |
| 179 | int ep_pcie_deregister_event(struct ep_pcie_hw *phandle); |
| 180 | |
| 181 | /* |
| 182 | * ep_pcie_get_linkstatus - indicate the status of PCIe link. |
| 183 | * @phandle: PCIe endpoint HW driver handle |
| 184 | * |
| 185 | * This function tells PCIe client about the status of PCIe link. |
| 186 | * |
| 187 | * Return: status of PCIe link |
| 188 | */ |
| 189 | enum ep_pcie_link_status ep_pcie_get_linkstatus(struct ep_pcie_hw *phandle); |
| 190 | |
| 191 | /* |
| 192 | * ep_pcie_config_outbound_iatu - configure outbound iATU. |
| 193 | * @entries: iatu entries |
| 194 | * @num_entries: number of iatu entries |
| 195 | * |
| 196 | * This function configures the outbound iATU for PCIe |
| 197 | * client's access to the regions in the host memory which |
| 198 | * are specified by the SW on host side. |
| 199 | * |
| 200 | * Return: 0 on success, negative value on error |
| 201 | */ |
| 202 | int ep_pcie_config_outbound_iatu(struct ep_pcie_hw *phandle, |
| 203 | struct ep_pcie_iatu entries[], |
| 204 | u32 num_entries); |
| 205 | |
| 206 | /* |
| 207 | * ep_pcie_get_msi_config - get MSI config info. |
| 208 | * @phandle: PCIe endpoint HW driver handle |
| 209 | * @cfg: pointer to MSI config |
| 210 | * |
| 211 | * This function returns MSI config info. |
| 212 | * |
| 213 | * Return: 0 on success, negative value on error |
| 214 | */ |
| 215 | int ep_pcie_get_msi_config(struct ep_pcie_hw *phandle, |
| 216 | struct ep_pcie_msi_config *cfg); |
| 217 | |
| 218 | /* |
| 219 | * ep_pcie_trigger_msi - trigger an MSI. |
| 220 | * @phandle: PCIe endpoint HW driver handle |
| 221 | * @idx: MSI index number |
| 222 | * |
| 223 | * This function allows PCIe client to trigger an MSI |
| 224 | * on host side. |
| 225 | * |
| 226 | * Return: 0 on success, negative value on error |
| 227 | */ |
| 228 | int ep_pcie_trigger_msi(struct ep_pcie_hw *phandle, u32 idx); |
| 229 | |
| 230 | /* |
| 231 | * ep_pcie_wakeup_host - wake up the host. |
| 232 | * @phandle: PCIe endpoint HW driver handle |
| 233 | * |
| 234 | * This function asserts WAKE GPIO to wake up the host. |
| 235 | * |
| 236 | * Return: 0 on success, negative value on error |
| 237 | */ |
| 238 | int ep_pcie_wakeup_host(struct ep_pcie_hw *phandle); |
| 239 | |
| 240 | /* |
| 241 | * ep_pcie_enable_endpoint - enable PCIe endpoint. |
| 242 | * @phandle: PCIe endpoint HW driver handle |
| 243 | * @opt: endpoint enable options |
| 244 | * |
| 245 | * This function is to enable the PCIe endpoint device. |
| 246 | * |
| 247 | * Return: 0 on success, negative value on error |
| 248 | */ |
| 249 | int ep_pcie_enable_endpoint(struct ep_pcie_hw *phandle, |
| 250 | enum ep_pcie_options opt); |
| 251 | |
| 252 | /* |
| 253 | * ep_pcie_disable_endpoint - disable PCIe endpoint. |
| 254 | * @phandle: PCIe endpoint HW driver handle |
| 255 | * |
| 256 | * This function is to disable the PCIe endpoint device. |
| 257 | * |
| 258 | * Return: 0 on success, negative value on error |
| 259 | */ |
| 260 | int ep_pcie_disable_endpoint(struct ep_pcie_hw *phandle); |
| 261 | |
| 262 | /* |
| 263 | * ep_pcie_config_db_routing - Configure routing of doorbells to another block. |
| 264 | * @phandle: PCIe endpoint HW driver handle |
| 265 | * @chdb_cfg: channel doorbell config |
| 266 | * @erdb_cfg: event ring doorbell config |
| 267 | * |
| 268 | * This function allows PCIe core to route the doorbells intended |
| 269 | * for another entity via a target address. |
| 270 | * |
| 271 | * Return: 0 on success, negative value on error |
| 272 | */ |
| 273 | int ep_pcie_config_db_routing(struct ep_pcie_hw *phandle, |
| 274 | struct ep_pcie_db_config chdb_cfg, |
| 275 | struct ep_pcie_db_config erdb_cfg); |
| 276 | |
| 277 | /* |
| 278 | * ep_pcie_mask_irq_event - enable and disable IRQ event. |
| 279 | * @phandle: PCIe endpoint HW driver handle |
| 280 | * @event: IRQ event |
| 281 | * @enable: true to enable that IRQ event and false to disable |
| 282 | * |
| 283 | * This function is to enable and disable IRQ event. |
| 284 | * |
| 285 | * Return: 0 on success, negative value on error |
| 286 | */ |
| 287 | int ep_pcie_mask_irq_event(struct ep_pcie_hw *phandle, |
| 288 | enum ep_pcie_irq_event event, |
| 289 | bool enable); |
| 290 | #endif |