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gerrit-public.fairphone.software / kernel / msm-4.9 / e4aa18d33c3a05f9ac51a8c8c7863318c807650f / . / include / linux / platform_data / spi-s3c64xx.h
blob: d3889b98a1a12de82558f85fdced79a2896fac89 [file] [log] [blame]
Sachin Kamat963eb4b2014-02-14 12:26:17 +0530[diff] [blame]1/*
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Sachin Kamat963eb4b2014-02-14 12:26:17 +0530[diff] [blame]10#ifndef __SPI_S3C64XX_H
11#define __SPI_S3C64XX_H
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]12
Arnd Bergmann78843722013-04-11 22:42:03 +0200[diff] [blame]13#include <linux/dmaengine.h>
14
Mark Brown5b0b34e2011-12-29 18:01:08 +0900[diff] [blame]15struct platform_device;
16
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]17/**
18 * struct s3c64xx_spi_csinfo - ChipSelect description
19 * @fb_delay: Slave specific feedback delay.
20 * Refer to FB_CLK_SEL register definition in SPI chapter.
21 * @line: Custom 'identity' of the CS line.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]22 *
23 * This is per SPI-Slave Chipselect information.
24 * Allocate and initialize one in machine init code and make the
25 * spi_board_info.controller_data point to it.
26 */
27struct s3c64xx_spi_csinfo {
28 u8 fb_delay;
29 unsigned line;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]30};
31
32/**
33 * struct s3c64xx_spi_info - SPI Controller defining structure
34 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]35 * @num_cs: Number of CS this controller emulates.
36 * @cfg_gpio: Configure pins for this SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]37 */
38struct s3c64xx_spi_info {
39 int src_clk_nr;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]40 int num_cs;
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]41 int (*cfg_gpio)(void);
Arnd Bergmann78843722013-04-11 22:42:03 +0200[diff] [blame]42 dma_filter_fn filter;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]43};
44
45/**
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]46 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]47 * initialization code.
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]48 * @cfg_gpio: Pointer to gpio setup function.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]49 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
50 * @num_cs: Number of elements in the 'cs' array.
51 *
52 * Call this from machine init code for each SPI Controller that
53 * has some chips attached to it.
54 */
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]55extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
56 int num_cs);
57extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
58 int num_cs);
59extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
60 int num_cs);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]61
62/* defined by architecture to configure gpio */
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]63extern int s3c64xx_spi0_cfg_gpio(void);
64extern int s3c64xx_spi1_cfg_gpio(void);
65extern int s3c64xx_spi2_cfg_gpio(void);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]66
67extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
68extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
Padmavathi Venna323d7712011-12-23 10:14:45 +0900[diff] [blame]69extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
Sachin Kamat963eb4b2014-02-14 12:26:17 +0530[diff] [blame]70#endif /*__SPI_S3C64XX_H */